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HEXFET
Power MOSFET
S
D
G
Parameter
Typ.
Max.
Units
R
JC
Junction-to-Case
3.3
R
JA
Case-to-Ambient (PCB mount)**
50
C/W
R
JA
Junction-to-Ambient
110
Thermal Resistance
V
DSS
= 55V
R
DS(on)
= 0.065
I
D
= 17A
Description
12/6/04
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1
l
Logic-Level Gate Drive
l
Surface Mount (IRLR024N)
l
Straight Lead (IRLU024N)
l
Advanced Process Technology
l
Fast Switching
l
Fully Avalanche Rated
l
Lead-Free
Fifth Generation HEXFET
Power MOSFETs from International Rectifier
utilize advanced processing techniques to achieve the lowest possible on-
resistance per silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET power MOSFETs are well
known for, provides the designer with an extremely efficient device for use in
a wide variety of applications.
The D-PAK is designed for surface mounting using vapor phase, infrared, or
wave soldering techniques. The straight lead version (IRFU series) is for
through-hole mounting applications. Power dissipation levels up to 1.5 watts
are possible in typical surface mount applications.
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
Parameter
Max.
Units
I
D
@ T
C
= 25C
Continuous Drain Current, V
GS
@ 10V
17
I
D
@ T
C
= 100C
Continuous Drain Current, V
GS
@ 10V
12
A
I
DM
Pulsed Drain Current
72
P
D
@T
C
= 25C
Power Dissipation
45
W
Linear Derating Factor
0.3
W/C
V
GS
Gate-to-Source Voltage
16
V
E
AS
Single Pulse Avalanche Energy
68
mJ
I
AR
Avalanche Current
11
A
E
AR
Repetitive Avalanche Energy
4.5
mJ
dv/dt
Peak Diode Recovery dv/dt
5.0
V/ns
T
J
Operating Junction and
-55 to + 175
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
300 (1.6mm from case )
C
Absolute Maximum Ratings
PD- 95081A
IRLR024NPbF
IRLU024NPbF
D-Pak
I-Pak
IRLR024NPbF IRLU024NPbF
IRLR/U024NPbF
2
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S
D
G
Parameter
Min. Typ. Max. Units
Conditions
I
S
Continuous Source Current
MOSFET symbol
(Body Diode)
showing the
I
SM
Pulsed Source Current
integral reverse
(Body Diode)
p-n junction diode.
V
SD
Diode Forward Voltage
1.3
V
T
J
= 25C, I
S
= 11A, V
GS
= 0V
t
rr
Reverse Recovery Time
60
90
ns
T
J
= 25C, I
F
= 11A
Q
rr
Reverse RecoveryCharge
130
200
nC
di/dt = 100A/s
t
on
Forward Turn-On Time
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Source-Drain Ratings and Characteristics
17
72
A
V
DD
= 25V, starting T
J
= 25C, L = 790H
R
G
= 25
, I
AS
= 11A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Pulse width
300s; duty cycle 2%.
Uses IRLZ24N data and test conditions.
This is applied for I-PAK, L
S
of D-PAK is measured between
lead and center of die contact
I
SD
11A, di/dt 290A/s, V
DD
V
(BR)DSS
,
T
J
175C
Notes:
Parameter
Min. Typ. Max. Units
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
55
V
V
GS
= 0V, I
D
= 250A
V
(BR)DSS
/
T
J
Breakdown Voltage Temp. Coefficient
0.061
V/C Reference to 25C, I
D
= 1mA
0.065
V
GS
= 10V, I
D
= 10A
0.080
V
GS
= 5.0V, I
D
= 10A
0.110
V
GS
= 4.0V, I
D
= 9.0A
V
GS(th)
Gate Threshold Voltage
1.0
2.0
V
V
DS
= V
GS
, I
D
= 250A
g
fs
Forward Transconductance
8.3
S
V
DS
= 25V, I
D
= 11A
25
A
V
DS
= 55V, V
GS
= 0V
250
V
DS
= 44V, V
GS
= 0V, T
J
= 150C
Gate-to-Source Forward Leakage
100
nA
V
GS
= 16V
Gate-to-Source Reverse Leakage
-100
V
GS
= -16V
Q
g
Total Gate Charge
15
I
D
= 11A
Q
gs
Gate-to-Source Charge
3.7
nC
V
DS
= 44V
Q
gd
Gate-to-Drain ("Miller") Charge
8.5
V
GS
= 5.0V, See Fig. 6 and 13
t
d(on)
Turn-On Delay Time
7.1
V
DD
= 28V
t
r
Rise Time
74
ns
I
D
= 11A
t
d(off)
Turn-Off Delay Time
20
R
G
= 12
, V
GS
= 5.0V
t
f
Fall Time
29
R
D
= 2.4
, See Fig. 10
Between lead,
6mm (0.25in.)
from package
and center of die contact
C
iss
Input Capacitance
480
V
GS
= 0V
C
oss
Output Capacitance
130
pF
V
DS
= 25V
C
rss
Reverse Transfer Capacitance
61
= 1.0MHz, See Fig. 5
Electrical Characteristics @ T
J
= 25C (unless otherwise specified)
nH
I
GSS
S
D
G
L
S
Internal Source Inductance
7.5
R
DS(on)
Static Drain-to-Source On-Resistance
L
D
Internal Drain Inductance
4.5
I
DSS
Drain-to-Source Leakage Current
IRLR/U024NPbF
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3
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.1
1
10
100
0.1
1
10
100
I , D
r
a
i
n
-
to
-S
o
u
r
c
e
C
u
rre
n
t
(A
)
D
V , Drain-to-Source Voltage (V)
DS
A
20s PULSE WIDTH
T = 25C
J
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
0.1
1
10
100
0.1
1
10
100
I , D
r
a
i
n
-
to
-S
o
u
rc
e
C
u
rre
n
t
(A
)
D
V , Drain-to-Source Voltage (V)
DS
A
20s PULSE WIDTH
T = 175C
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
J
0.1
1
10
100
2
3
4
5
6
7
8
9
10
T = 25C
J
GS
V , Gate-to-Source Voltage (V)
D
I
, Dra
i
n
-
to
-
S
o
u
rc
e
C
u
rre
n
t
(A)
T = 175C
J
A
V = 15V
20s PULSE WIDTH
DS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20
0
20
40
60
80 100 120 140 160 180
J
T , Junction Temperature (C)
R
, D
r
a
i
n
-
to
-S
o
u
rc
e
O
n
R
e
s
i
s
t
a
n
c
e
DS
(
o
n)
(
N
or
m
a
l
i
z
ed)
V = 10V
GS
A
I = 18A
D
17 A
IRLR/U024NPbF
4
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
200
400
600
800
1
10
100
C
,
Ca
pa
c
i
t
a
n
c
e (
p
F)
DS
V , Drain-to-Source Voltage (V)
A
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
0
3
6
9
12
15
0
4
8
12
16
20
Q , Total Gate Charge (nC)
G
V
, G
a
te
-to
-
S
o
u
r
c
e
V
o
lta
g
e
(V
)
GS
A
FOR TEST CIRCUIT
SEE FIGURE 13
V = 44V
V = 28V
I = 11A
DS
DS
D
1
10
100
0.4
0.8
1.2
1.6
2.0
T = 25C
J
V = 0V
GS
V , Source-to-Drain Voltage (V)
I
, R
e
v
e
rs
e
D
r
a
i
n
C
u
r
r
e
n
t (
A
)
SD
SD
A
T = 175C
J
1
10
100
1000
1
10
100
V , Drain-to-Source Voltage (V)
DS
I
,
D
r
ai
n
C
u
r
r
ent
(
A
)
OPERATION IN THIS AREA LIMITED
BY R
D
DS(on)
10s
100s
1ms
10ms
A
T = 25C
T = 175C
Single Pulse
C
J
IRLR/U024NPbF
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5
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
V
DS
Pulse Width 1 s
Duty Factor 0.1 %
R
D
V
GS
R
G
D.U.T.
5V
+
-
V
DD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
0.01
0.1
1
10
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
thJ
C
D = 0.50
0.01
0.02
0.05
0.10
0.20
SINGLE PULSE
(THERMAL RESPONSE)
A
T
h
e
r
ma
l
R
e
s
p
o
n
s
e
(
Z
)
P
t2
1
t
DM
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1
2
J
DM
thJC
C
25
50
75
100
125
150
175
0
5
10
15
20
T , Case Temperature ( C)
I , D
r
ain C
u
rrent (A
)
C
D
IRLR/U024NPbF
6
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Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T.
V
DS
I
D
I
G
3mA
V
GS
.3
F
50K
.2
F
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
RG
IAS
0.01
tp
D.U.T
L
VDS
+
- VDD
DRIVER
A
15V
20V
0
20
40
60
80
100
120
140
25
50
75
100
125
150
175
J
E
,
S
i
n
g
l
e
Pu
l
s
e
Av
al
anc
he E
n
er
gy
(m
J
)
AS
A
Starting T , Junction Temperature (C)
V = 25V
I
TOP 4.5A
7.8A
BOTTOM 11A
DD
D
IRLR/U024NPbF
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7
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple
5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel
HEXFET
MOSFET
s
*
V
GS
= 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
R
G
V
DD
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
*
IRLR/U024NPbF
8
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D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
12
IN THE ASSEMBLY LINE "A"
ASSEMBLED ON WW 16, 1999
EXAMPLE:
WITH ASSEMBLY
THIS IS AN IRFR120
LOT CODE 1234
YEAR 9 = 1999
DATE CODE
WEEK 16
PART NUMBER
LOGO
INTERNATIONAL
RECTIFIER
ASSEMBLY
LOT CODE
916A
IRFU120
34
YEAR 9 = 1999
DATE CODE
OR
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
Note: "P" in assembly line position
indicates "Lead-Free"
12
34
WEEK 16
A = ASSEMBLY SITE CODE
PART NUMBER
IRFU120
LINE A
LOGO
LOT CODE
ASSEMBLY
INTERNATIONAL
RECTIFIER
IRLR/U024NPbF
www.irf.com
9
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
ASSEMBLY
EXAMPLE:
WITH ASSEMBLY
THIS IS AN IRFU120
YEAR 9 = 1999
DATE CODE
LINE A
WEEK 19
IN THE ASSEMBLY LINE "A"
ASSEMBLED ON WW 19, 1999
LOT CODE 5678
PART NUMBER
56
IRFU120
INTERNATIONAL
LOGO
RECT IFIER
LOT CODE
919A
78
Note: "P" in assembly line
position indicates "Lead-Free"
OR
56
78
ASSEMBLY
LOT CODE
RECTIFIER
LOGO
INTERNATIONAL
IRFU120
PART NUMBER
WEEK 19
DATE CODE
YEAR 9 = 1999
A = ASSEMBLY SITE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
IRLR/U024NPbF
10
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Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
TRR
TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
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