FEATURES

· High-speed access time: 10, 12, 15, and 20 ns

· CMOS low power operation

-- 1650 mW (max) @ -10ns Cycle

-- 55

W (max) CMOS Standby

· TTL compatible interface levels

· Single 5V

10% power supply

· Fully static operation: no clock or refresh

required

· Three state outputs

· Industrial temperature available

· Available in 44-pin SOJ package and

44-pin TSOP (Type II)

IS61C6416

64K x 16 HIGH-SPEED CMOS STATIC RAM

DESCRIPTION

The

ISSI

IS61C6416 is a high-speed, 1,048,576-bit static

RAM organized as 65,536 words by 16 bits. It is fabricated
using

ISSI

's high-performance CMOS technology. This highly

reliable process coupled with innovative circuit design tech-
niques, yields access times as fast as 10 ns with low power
consumption.

When

is HIGH (deselected), the device assumes a standby

mode at which the power dissipation can be reduced down
with CMOS input levels.

Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,

and

. The active LOW Write

Enable (

) controls both writing and reading of the memory.A

data byte allows Upper Byte (

) and Lower Byte (

) access.

The IS61C6416 is packaged in the JEDEC standard 44-pin
400-mil SOJ and 44-pin TSOP (Type II).

FUNCTIONAL BLOCK DIAGRAM

MAY 1999

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.

A0-A15

64K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

Integrated Silicon Solution, Inc. -- 1-800-379-4774

SR005-1D
05/24/99

ISSI

IS61C6416

Integrated Silicon Solution, Inc. -- 1-800-379-4774

SR005-1D

05/24/99

ISSI

PIN CONFIGURATIONS

44-Pin SOJ

PIN DESCRIPTIONS

A0-A15

Address Inputs

I/O0-I/O15

Data Inputs/Outputs

Chip Enable Input

Output Enable Input

Write Enable Input

TRUTH TABLE

I/O PIN

Mode

I/O0-I/O7

I/O8-I/O15

Vcc Current

Not Selected

High-Z

, I

Output Disabled

High-Z

, I

High-Z

Read

OUT

High-Z

, I

High-Z

OUT

Write

High-Z

, I

High-Z

44-Pin TSOP (Type II)

Lower-byte Control (I/O0-I/O7)

Upper-byte Control (I/O8-I/O15)

No Connection

Vcc

Power

GND

Ground

A15

A14

A13

A12

A11

I/O0

I/O1

I/O2

I/O3

Vcc

GND

I/O4

I/O5

I/O6

I/O7

A10

I/O15

I/O14

I/O13

I/O12

GND

Vcc

I/O11

I/O10

I/O9

I/O8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A15
A14
A13
A12
A11

I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

A10

A9
A8
A7

A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC

IS61C6416

Integrated Silicon Solution, Inc. -- 1-800-379-4774

SR005-1D
05/24/99

ISSI

OPERATING RANGE

Range

Ambient Temperature

Speed

Commercial

C to +70

-10, -12

-15, -20

10%

Industrial

C to +85

-12

-15, -20

10%

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-10

-12

-15

-20

Symbol

Parameter

Test Conditions

Min. Max.

Unit

Vcc Dynamic Operating

= Max.,

Com.

300

280

260

235

Supply Current

OUT

= 0 mA, f =

MAX

Ind.

300

290

255

TTL Standby Current

= Max.,

Com.

(TTL Inputs)

= V

or V

Ind.

, f = max

CMOS Standby

= Max.,

Com.

Current (CMOS Inputs)

0.2V,

Ind.

0.2V, or

0.2V, f = 0

Note:
1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

= 100

3.95

Output LOW Voltage

= Min., I

= 8.0 mA

0.4

Input HIGH Voltage

2.2

+ 0.5

Input LOW Voltage

(1)

0.5

0.8

Input Leakage

GND

Output Leakage

GND

OUT

, Outputs Disabled

Notes:
1. V

(min.) = 3.0V for pulse width less than 10 ns.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter

Value

Unit

TERM

Terminal Voltage with Respect to GND

0.5 to +7.0

STG

Storage Temperature

65 to +150

Power Dissipation

1.5

OUT

DC Output Current (LOW)

Note:
1. Stress greater than those listed under ABSO-

LUTE MAXIMUM RATINGS may cause per-
manent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions above
those indicated in the operational sections of
this specification is not implied. Exposure to
absolute maximum rating conditions for ex-
tended periods may affect reliability.

IS61C6416

Integrated Silicon Solution, Inc. -- 1-800-379-4774

SR005-1D

05/24/99

ISSI

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-10

-12

-15

-20

Symbol

Parameter

Min. Max.

Min.

Max.

Min. Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

Access Time

DOE

Access Time

HZOE

(2)

to High-Z Output

LZOE

(2)

to Low-Z Output

HZCE

to High-Z Output

LZCE

(2)

to Low-Z Output

Access Time

HZB

to High-Z Output

LZB

to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured

500 mV from steady-state voltage. Not 100% tested.

3. Not 100% tested.

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Level

Output Load

See Figures 1 and 2

CAPACITANCE

(1)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Note:
1. Tested initially and after any design or process changes that may affect these parameters.

Figure 1

Figure 2

AC TEST LOADS

480

30 pF

Including

jig and

scope

255

OUTPUT

480

5 pF

Including

jig and

scope

255

OUTPUT

IS61C6416

Integrated Silicon Solution, Inc. -- 1-800-379-4774

SR005-1D
05/24/99

ISSI

READ CYCLE NO. 2

(1,3)

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

(Address Controlled) (

= V

)

Notes:
1.

is HIGH for a Read Cycle.

2. The device is continuously selected.

, or

= V

3. Address is valid prior to or coincident with

LOW transition.

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

UB_CEDR2.eps

HZB

ADDRESS

LB, UB

OUT

HZCE

LZB

DATA VALID

READ1.eps

PREVIOUS DATA VALID

OHA

OUT

ADDRESS

IS61C6416

Integrated Silicon Solution, Inc. -- 1-800-379-4774

SR005-1D

05/24/99

ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-10

-12

-15

-20

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

SCE

to Write End

Address Setup Time

to Write End

Address Hold from Write End

Address Setup Time

PWB

Valid to End of Write

PWE

Pulse Width (

=High)

PWE

Pulse Width (

=Low)

Data Setup to Write End

Data Hold from Write End

HZWE

(2)

LOW to High-Z Output

LZWE

(2)

HIGH to Low-Z Output

Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse

levels of 0 to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured

500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

LOW and

, and

LOW. All signals must be

in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.

IS61C6416

Integrated Silicon Solution, Inc. -- 1-800-379-4774

SR005-1D
05/24/99

ISSI

Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the

and

inputs and at least

one of the

and

inputs being in the LOW state.

2. WRITE = (

)

[

(

) = (

)

]

(

AC WAVEFORMS

WRITE CYCLE NO. 1 (

Controlled)

(1,2)

DATA UNDEFINED

VALID ADDRESS

SCE

PWE1

PWE2

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

UB_CEWR1.eps

IS61C6416

Integrated Silicon Solution, Inc. -- 1-800-379-4774

SR005-1D

05/24/99

ISSI

WRITE CYCLE NO. 2

(

is HIGH During Write Cycle)

(1,2)

WRITE CYCLE NO. 3

(

is LOW During Write Cycle)

(1)

Notes:
1. The internal write time is defined by the overlap of

LOW and

LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if

DATA UNDEFINED

LOW

VALID ADDRESS

PWE1

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

UB_CEWR2.eps

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

PBW

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

UB_CEWR3.eps

IS61C6416

Integrated Silicon Solution, Inc. -- 1-800-379-4774

SR005-1D
05/24/99

ISSI

ORDERING INFORMATION

Commercial Range: 0

C to +70

Speed (ns)

Order Part No.

Package

IS61C6416-10T

Plastic TSOP(II)

IS61C6416-10K

400-mil Plastic SOJ

IS61C6416-12T

Plastic TSOP(II)

IS61C6416-12K

400-mil Plastic SOJ

IS61C6416-15T

Plastic TSOP(II)

IS61C6416-15K

400-mil Plastic SOJ

IS61C6416-20T

Plastic TSOP(II)

IS61C6416-20K

400-mil Plastic SOJ

ORDERING INFORMATION

Industrial Range: 40

C to +85

Speed (ns)

Order Part No.

Package

IS61C6416-12TI

Plastic TSOP(II)

IS61C6416-12KI

400-mil Plastic SOJ

IS61C6416-15TI

Plastic TSOP(II)

IS61C6416-15KI

400-mil Plastic SOJ

IS61C6416-20TI

Plastic TSOP(II)

IS61C6416-20KI

400-mil Plastic SOJ

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774
Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

WRITE CYCLE NO. 4

(

Back to Back Write)

DATA UNDEFINED

ADDRESS 1

ADDRESS 2

HIGH-Z

PBW

WORD 1

LOW

WORD 2

UB_CEWR4.eps

HZWE

ADDRESS

UB, LB

OUT

DATA

VALID

LZWE

PBW

DATA

VALID

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