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Электронный компонент: IS61C64B

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IS61C64B
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
07/01/02
Copyright 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
FEATURES
High-speed access time: 10, 12, and 15 ns
Automatic power-down when chip is
deselected
CMOS low power operation
-- 450 mW (typical) operating
-- 250 W (typical) standby
TTL compatible interface levels
Single 5V power supply
Fully static operation: no clock or refresh
required
Three state outputs
One Chip Enables (
CE
) for increased speed
8K x 8 HIGH-SPEED CMOS STATIC RAM
DESCRIPTION
The
ISSI
IS61C64B is a very high-speed, low power,
8192-word by 8-bit static RAM. It is fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 10 ns with low power consumption.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 W (typical) with CMOS input levels.
Easy memory expansion is provided by using one Chip Enable
input,
CE
. The active LOW Write Enable (
WE
) controls both
writing and reading of the memory.
The IS61C64B is packaged in the JEDEC standard 28-pin,
300-mil SOJ, and TSOP.
FUNCTIONAL BLOCK DIAGRAM
A0-A12
CE
OE
WE
256 X 256
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
July 2002
IS61C64B
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
07/01/02
PIN CONFIGURATION
28-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
*
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
*
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTIONS
A0-A12
Address Inputs
CE
Chip Enable 1 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
*
Must be tied to either
Vcc or GND
Vcc
Power
GND
Ground
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
I/O Operation
Vcc Current
Not Selected
X
H
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
X
X
X
High-Z
I
SB
1
, I
SB
2
Output Disabled
H
L
H
High-Z
I
CC
Read
H
L
L
D
OUT
I
CC
Write
L
L
X
D
IN
I
CC
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
*
WE
VCC
*
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN CONFIGURATION
28-Pin TSOP (Type 1)
1
2
3
4
5
6
7
8
9
10
11
12
IS61C64B
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
07/01/02
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
10 to +85
C
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
Range
Ambient Temperature
Speed
V
CC
Commercial
0C to +70C
10 ns
5V 5%
12 ns
5V 10%
15 ns
5V 10%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.5
V
V
IL
Input LOW Voltage
(1)
0.5
0.8
V
I
LI
Input Leakage
GND - V
IN
- V
CC
2
2
A
I
LO
Output Leakage
GND - V
OUT
- V
CC
, Outputs Disabled
2
2
A
Notes:
1. V
IL
= 3.0V for pulse width less than 10 ns.
IS61C64B
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
07/01/02
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-10 ns
-12 ns
-15 ns
Symbol
Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
Vcc Dynamic Operating
V
CC
= Max.,
--
185
--
175
--
135
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
I
SB
1
TTL Standby Current
V
CC
= Max.,
--
30
--
30
--
30
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
CE1
V
IH
or
CE2 - V
IL
, f = 0
I
SB
2
CMOS Standby
V
CC
= Max.,
--
10
--
10
--
10
mA
Current (CMOS Inputs)
CE1
V
CC
0.2V,
CE2 - 0.2V,
V
IN
V
CC
0.2V, or
V
IN
- 0.2V, f = 0
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
8
pF
C
OUT
Output Capacitance
V
OUT
= 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, Vcc = 5.0V.
1
2
3
4
5
6
7
8
9
10
11
12
IS61C64B
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
07/01/02
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
10 ns
-12 ns
-15 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
10
--
12
--
15
--
ns
t
AA
Address Access Time
--
10
--
12
--
15
ns
t
OHA
Output Hold Time
2
--
2
--
2
--
ns
t
ACE
CE
Access Time
--
10
--
12
--
15
ns
t
DOE
OE
Access Time
--
5
--
6
--
7
ns
t
LZOE
(2)
OE
to Low-Z Output
0
--
0
--
0
--
ns
t
HZOE
(2)
OE
to High-Z Output
--
5
--
6
--
6
ns
t
LZCE
1
(2)
CE
to Low-Z Output
2
--
3
--
3
--
ns
t
HZCE
(2)
CE
to High-Z Output
--
5
--
7
--
8
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Level
Output Load
See Figures 1a and 1b
AC TEST LOADS
Figure 1a.
480
30 pF
Including
jig and
scope
255
OUTPUT
5V
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
Figure 1b.
IS61C64B
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
07/01/02
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
t
HZCE
ADDRESS
OE
CE
D
OUT
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
,
CE
= V
IL
.
3. Address is valid prior to or coincident with
CE
LOW transitions.
READ CYCLE NO. 2
(1,3)
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
1
2
3
4
5
6
7
8
9
10
11
12
IS61C64B
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
07/01/02
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
10 ns
-12 ns
-15 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
10
--
12
--
15
--
ns
t
SCE
CE
to Write End
9
--
10
--
12
--
ns
t
AW
Address Setup Time to Write End
9
--
10
--
12
--
ns
t
HA
Address Hold from Write End
0
--
0
--
0
--
ns
t
SA
Address Setup Time
0
--
0
--
0
--
ns
t
PWE
(4)
WE
Pulse Width
8
--
8
--
10
--
ns
t
SD
Data Setup to Write End
8
--
8
--
9
--
ns
t
HD
Data Hold from Write End
0
--
0
--
0
--
ns
t
HZWE
(2)
WE
LOW to High-Z Output
--
6
--
6
--
7
ns
t
LZWE
(2)
WE
HIGH to Low-Z Output
0
--
0
--
0
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
IS61C64B
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
07/01/02
WRITE CYCLE NO. 2 (
CE1
CE1
CE1
CE1
CE1
, CE2 Controlled)
(1,2)
HIGH-Z
DATA UNDEFINED
DATA-IN VALID
t
WC
t
SCE
t
SA
t
HA
t
PWE
t
AW
t
HZWE
t
SD
t
HD
t
LZWE
ADDRESS
D
IN
CE
WE
D
OUT
Notes:
1. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
AC WAVEFORMS
WRITE CYCLE NO. 1 (
WE
WE
WE
WE
WE
Controlled)
(1,2)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CE
WE
D
OUT
D
IN
1
2
3
4
5
6
7
8
9
10
11
12
IS61C64B
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
07/01/02
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed (ns)
Order Part No.
Package
10
IS61C64B-10J
300-mil Plastic SOJ
IS61C64B-10T
Plastic TSOP
12
IS61C64B-12J
300-mil Plastic SOJ
IS61C64B-12T
Plastic TSOP
15
IS61C64B-15J
300-mil Plastic SOJ
IS61C64B-15T
Plastic TSOP