Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
08/25/05

IS61LF6436A
IS61LF6432A

ISSI

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

· Internal self-timed write cycle

· Individual Byte Write Control and Global Write

· Clock controlled, registered address, data and

control

· Interleaved or linear burst sequence control

using MODE input

· Three chip enables for simple depth expansion

and address pipelining

· Common data inputs and data outputs

· Power-down control by ZZ input

· JEDEC 100-Pin TQFP package

· Power Supply:

+3.3V V

+3.3V or 2.5V V

DDQ

· Control pins mode upon power-up:

MODE in interleave burst mode
ZZ in normal operation mode

· Industrial Temperature Available:

(-40

C to +85

· Lead-free available

DESCRIPTION

The

ISSI

IS61LF6432A and IS61LF6436A are high-speed,

low-power synchronous static RAM designed to provide a
burstable, high-performance, memory. IS61LF6432A is
organized as 65,536 words by 32 bits. IS61LF6436A is
organized as 65,536 words by 36 bits. They are fabricated
with

ISSI

's advanced CMOS technology. The device inte-

grates a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BWa

controls DQa,

BWb

controls DQb,

BWc

controls DQc,

BWd

controls DQd, conditioned by

BWE

being LOW. A

LOW on

input would cause all bytes to be written.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated
internally by the IS61LF6432A/36A and controlled by the

ADV

(burst address advance) input pin.

The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.

64K x 32, 64Kx36
SYNCHRONOUS FLOW-THROUGH
STATIC RAM

OCTOBER 2005

FAST ACCESS TIME

Symbol

Parameter

8.5

Unit

Clock Access Time

8.5

Cycle Time

Frequency

MHz

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
08/25/05

PIN CONFIGURATION

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

Synchronous Address Inputs

CLK

Synchronous Clock

ADSP

Synchronous Processor Address
Status

ADSC

Synchronous Controller Address
Status

ADV

Synchronous Burst Address Advance

BWa

BWd

Individual Byte Write Enable

BWE

Synchronous Byte Write Enable

Synchronous Global Write Enable

CE2

, CE2 Synchronous Chip Enable

Output Enable

DQa-DQd

Synchronous Data Input/Output

MODE

Burst Sequence Mode Selection

+3.3V Power Supply

Vss

Ground

DDQ

Isolated Output Buffer Supply: +3.3V
or 2.5V

Snooze Enable

NC
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
NC

CE2

BWd

BWc

BWb

BWa

CE2

VDD

Vss

CLK

BWE

ADS

ADSP

ADV

DQc
DQc

VDDQ

Vss

DQc
DQc
DQc
DQc

Vss

VDDQ

DQc
DQc

VDD

Vss

DQd
DQd

VDDQ

Vss

DQd
DQd
DQd
DQd

Vss

VDDQ

DQd
DQd

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

Vss

VDD

46 47 48 49 50

64K x 32

100-Pin TQFP

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

08/25/05

PIN CONFIGURATION

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

Synchronous Address Inputs

CLK

Synchronous Clock

ADSP

Synchronous Processor Address
Status

ADSC

Synchronous Controller Address
Status

ADV

Synchronous Burst Address Advance

BWa

BWd

Individual Byte Write Enable

BWE

Synchronous Byte Write Enable

Synchronous Global Write Enable

CE2

, CE2 Synchronous Chip Enable

Output Enable

DQa-DQd

Synchronous Data Input/Output

MODE

Burst Sequence Mode Selection

+3.3V Power Supply

Vss

Ground

DDQ

Isolated Output Buffer Supply: +3.3V or
2.5V

Snooze Enable

DQPa-DQPd

Parity Data I/O

DQPb
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa

CE2

BWd

BWc

BWb

BWa

CE2

VDD

Vss

CLK

BWE

ADS

ADSP

ADV

DQPc

DQc
DQc

VDDQ

Vss

DQc
DQc
DQc
DQc

Vss

VDDQ

DQc
DQc

VDD

Vss

DQd
DQd

VDDQ

Vss

DQd
DQd
DQd
DQd

Vss

VDDQ

DQd
DQd

DQPd

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

Vss

VDD

46 47 48 49 50

64K x 36

100-Pin TQFP

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
08/25/05

TRUTH TABLE

Address

Operation

Used

CE2

ADSP

ADSP ADSC

ADSC

ADV

ADV WRITE

WRITE

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Read Cycle, Begin Burst

External

Read Cycle, Begin Burst

External

Read

Write Cycle, Begin Burst

External

Write

Read Cycle, Continue Burst

Read

Read Cycle, Continue Burst

Read

High-Z

Read Cycle, Continue Burst

Read

Read Cycle, Continue Burst

Read

High-Z

Write Cycle, Continue Burst

Write

Write Cycle, Continue Burst

Write

Read Cycle, Suspend Burst

Current

Read

Read Cycle, Suspend Burst

Current

Read

High-Z

Read Cycle, Suspend Burst

Current

Read

Read Cycle, Suspend Burst

Current

Read

High-Z

Write Cycle, Suspend Burst

Current

Write

Write Cycle, Suspend Burst

Current

Write

PARTIAL TRUTH TABLE

Function

BWE

BWa

BWb

BWc

BWd

Read

Write Byte 1

Write All Bytes

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

08/25/05

INTERLEAVED BURST ADDRESS TABLE (MODE = V

or No Connect)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A1 A0

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

STG

Storage Temperature

55 to +150

°C

Power Dissipation

1.6

OUT

Output Current (per I/O)

100

, V

OUT

Voltage Relative to Vss for I/O Pins

0.5 to V

DDQ

+ 0.3

Voltage Relative to Vss for

0.5 to V

+ 0.5

for Address and Control Inputs

Voltage on V

Supply Relative to Vss

0.5 to 4.6

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.

2. This device contains circuitry to protect the inputs against damage due to high static voltages

or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

0,0

1,0

0,1

A1', A0' = 1,1

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
08/25/05

DC ELECTRICAL CHARACTERISTICS

(1)

(Over Operating Range)

2.5V (I/O)

3.3V (I/O)

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

Output HIGH Voltage

= 4.0 mA (3.3V)

2.0

2.4

= 1.0 mA (2.5V)

Output LOW Voltage

= 8.0 mA (3.3V)

0.4

= 1.0 mA (2.5V)

Input HIGH Voltage

1.7

+ 0.3

2.0

+ 0.3

Input LOW Voltage

0.3

0.7

0.3

0.8

Input Leakage Current

Vss

µA

Output Leakage Current

Vss

OUT

DDQ

µA

= V

POWER SUPPLY CHARACTERISTICS

(Over Operating Range)

8.5

Symbol

Parameter

Test Conditions

Max.

Unit

AC Operating

Device Selected,

150

Supply Current

= V

, ZZ

All Inputs

0.2V or

0.2V,

Cycle Time

min.

Standby Current

Device Deselected,

CMOS Input

= Max.,

+ 0.2V or

0.2V

f = 0

Sleep Mode

ZZ>V

Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to Vss, or tied to V

2. The MODE pin should be tied to V

or Vss. It exhibits ±10 µA maximum leakage current when tied to

Vss + 0.2V

0.2V.

OPERATING RANGE

3.3V (I/O)

2.5V (I/O)

Range

Ambient Temperature

DDQ

Industrial

40°C to +85°C

3.3V, +10%, 5%

2.5V + 5%

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

08/25/05

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

= 25°C, f = 1 MHz, V

= 3.3V.

3.3V I/O AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

1.5 ns

Input and Output Timing

1.5V

and Reference Level

Output Load

See Figures 1 and 2

Output

= 50

1.5V

317

5 pF

Including

jig and

scope

351

OUTPUT

+3.3V

Figure 1

Figure 2

3.3V I/O OUTPUT LOAD EQUIVALENT

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

08/25/05

READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

8.5

Symbol

Parameter

Min.

Max.

Unit

MAX

(3)

Clock Frequency

MHz

(3)

Cycle Time

Clock High Time

4.5

(3)

Clock Low Time

4.5

(3)

Clock Access Time

8.5

KQX

(1)

Clock High to Output Invalid

KQLZ

(1,2)

Clock High to Output Low-Z

KQHZ

(1,2)

Clock High to Output High-Z

3.5

OEQ

(3)

Output Enable to Output Valid

4.0

OEQX

(1)

Output Enable to Output Invalid

OELZ

(1,2)

Output Enable to Output Low-Z

OEHZ

(1,2)

Output Disable to Output High-Z

5.0

(3)

Address Setup Time

(3)

Address Status Setup Time

(3)

Write Setup Time

CES

(3)

Chip Enable Setup Time

AVS

(3)

Address Advance Setup Time

(3)

Address Hold Time

(3)

Address Status Hold Time

0.5

(3)

Write Hold Time

0.5

CEH

(3)

Chip Enable Hold Time

0.5

AVH

(3)

Address Advance Hold Time

0.5

Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
08/25/05

READ/WRITE CYCLE TIMING

Single Read
Flow-through

Single Write

High-Z

DATA

OUT

DATA

CE2

BWd-BWa

BWE

Address

ADV

ADSC

ADSP

CLK

RD1

WR1

Unselected

Burst Read

KQX

ADSP is blocked by CE inactive

RD2

RD3

CES

CEH

CES

CEH

CES

CEH

CE2 and CE2 only sampled with ADSP or ADSC

CE Masks ADSP

Unselected with CE2

OEQX

OEHZ

KQX

KQHZ

KQLZ

KQX

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

08/25/05

WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

8.5

Symbol

Parameter

Min.

Max.

Unit

(1)

Cycle Time

(1)

Clock High Time

4.5

(1)

Clock Low Time

4.5

(1)

Address Setup Time

(1)

Address Status Setup Time

(1)

Write Setup Time

(1)

Data In Setup Time

CES

(1)

Chip Enable Setup Time

AVS

(1)

Address Advance Setup Time

(1)

Address Hold Time

(1)

Address Status Hold Time

0.5

(1)

Data In Hold Time

(1)

Write Hold Time

0.5

CEH

(1)

Chip Enable Hold Time

0.5

AVH

(1)

Address Advance Hold Time

0.5

Notes:
1. Tested with load in Figure 1.

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B
08/25/05

WRITE CYCLE TIMING

Single Write

DATA

OUT

DATA

CE2

BWd

BWa

BWE

ADV

ADSC

ADSP

CLK

WR1

WR2

Unselected

Burst Write

WR3

CES

CEH

CES

CEH

CES

CEH

CE2 and

CE2

only sampled with

ADSP

ADSC

Masks

ADSP

Unselected with CE2

ADSC initiate Write

ADSP is blocked by

inactive

AVH

AVS

ADV

must be inactive for

ADSP

Write

WR1

WR2

WR3

High-Z

BW4-BW1 only are applied to first cycle of WR2

Write

IS61LF6436A
IS61LF6432A

ISSI

Integrated Silicon Solution, Inc. -- 1-800-379-4774

Rev. B

08/25/05

SNOOZE MODE TIMING

Don't Care

Deselect or Read Only

RZZI

CLK

Isupply

All Inputs

(except ZZ)

Outputs

(Q)

SB2

ZZ setup cycle

ZZ recovery cycle

Normal

operation

cycle

PDS

PUS

ZZI

High-Z

SNOOZE MODE ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Conditions

Min.

Max.

Unit

Current during SNOOZE MODE

Vih

PDS

ZZ active to input ignored

cycle

PUS

ZZ inactive to input sampled

cycle

ZZI

ZZ active to SNOOZE current

cycle

RZZI

ZZ inactive to exit SNOOZE current

Integrated Silicon Solution, Inc. -- 1-800-379-4774

PACKAGING INFORMATION

ISSI

PK13197LQ Rev. D 05/08/03

TQFP (Thin Quad Flat Pack Package)
Package Code: TQ

Thin Quad Flat Pack (TQ)

Millimeters

Inches

Millimeters

Inches

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Ref. Std.

No. Leads (N)

100

128

1.60

0.063

1.60

0.063

0.05

0.15

0.002

0.006

0.05

0.15

0.002

0.006

1.35

1.45

0.053

0.057

1.35

1.45

0.053

0.057

0.22

0.38

0.009

0.015

0.17

0.27

0.007

0.011

21.90

22.10

0.862

0.870

21.80

22.20

0.858

0.874

19.90

20.10

0.783

0.791

19.90

20.10

0.783

0.791

15.90

16.10

0.626

0.634

15.80

16.20

0.622

0.638

13.90

14.10

0.547

0.555

13.90

14.10

0.547

0.555

0.65 BSC

0.026 BSC

0.50 BSC

0.020 BSC

0.45

0.75

0.018

0.030

0.45

0.75

0.018

0.030

1.00 REF.

0.039 REF.

1.00 REF.

0.039 REF.

Notes:
1. All dimensioning and

tolerancing conforms to
ANSI Y14.5M-1982.

2. Dimensions D1 and E1 do

not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.

3. Controlling dimension:

millimeters.

SEATING
PLANE

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