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Электронный компонент: IS61WV12816BLL

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ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
1
Rev. C
02/03/06
Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
IS61WV12816BLL
IS64WV12816BLL
FEATURES
High-speed access time:
12 ns: 3.3V + 10%
15 ns: 2.5V-3.6V
Operating Current: 25mA (typ.)
Stand by Current: 400A(typ.)
TTL and CMOS compatible interface levels
Fully static operation: no clock or refresh
required
Three state outputs
Data control for upper and lower bytes
Industrial and Automotive temperatures avail-
able
Lead-free available
128K x 16 HIGH-SPEED CMOS STATIC RAM
DESCRIPTION
The
ISSI
IS61WV12816BLL and IS64WV12816BLL are
high-speed, 2,097,152-bit static RAM organized as 131,072
words by 16 bits. They are fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When
CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE and OE. The active LOW
Write Enable (
WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (
UB) and Lower
Byte (
LB) access.
The IS61WV12816BLL and IS64WV12816BLL are packaged
in the JEDEC standard 44-pin TSOP (Type II) and 48-pin
mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
FEBRUARY 2006
A0-A16
CE
OE
WE
128Kx16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
V
DD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V
DD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
44-Pin TSOP (Type II) (T)
PIN DESCRIPTIONS
A0-A16
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
V
DD
Power
GND
Ground
TRUTH TABLE
I/O PIN
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
LB
LB
LB
LB
LB
UB
UB
UB
UB
UB
I/O0-I/O7
I/O8-I/O15
V
DD
Current
Not Selected
X
H
X
X
X
High-Z
High-Z
I
SB
1
, I
SB
2
Output Disabled
H
L
H
X
X
High-Z
High-Z
I
CC
X
L
X
H
H
High-Z
High-Z
Read
H
L
L
L
H
D
OUT
High-Z
I
CC
H
L
L
H
L
High-Z
D
OUT
H
L
L
L
L
D
OUT
D
OUT
Write
L
L
X
L
H
D
IN
High-Z
I
CC
L
L
X
H
L
High-Z
D
IN
L
L
X
L
L
D
IN
D
IN
PIN CONFIGURATION
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
3
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
PIN DESCRIPTIONS
A0-A16
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
V
DD
Power
GND
Ground
48-Pin mini BGA (B)
PIN CONFIGURATION
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
NC
I/O
8
UB
A3
A4
CE
I/O
0
I/O
9
I/O
10
A5
A6
I/O
1
I/O
2
GND
I/O
11
NC
A7
I/O
3
V
DD
V
DD
I/O
12
NC
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
NC
A8
A9
A10
A11
NC
4
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
OPERATING RANGE (V
DD
)
Range
Ambient Temperature
V
DD
(15 n
S
)
V
DD
(12 n
S
)
Industrial
40C to +85C
2.5V-3.6V
3.3V + 10%
Automotive
40C to +125C
2.5V-3.6V
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
DD
Power Supply Voltage Relative to GND
0.5 to 4.0V
V
V
TERM
Terminal Voltage with Respect to GND
0.5 to V
DD
+ 0.5
V
T
STG
Storage Temperature
65 to + 150
C
P
T
Power Dissipation
1.0
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
V
DD
= 2.5V-3.6V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
= 1.0 mA
1.8
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 1.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2.0
V
DD
+ 0.3
V
V
IL
Input LOW Voltage
(1)
0.3
0.4
V
I
LI
Input Leakage
GND
V
IN
V
DD
1
1
A
I
LO
Output Leakage
GND
V
OUT
V
DD
, Outputs Disabled
1
1
A
Note:
1.
V
IL
(min.) = 0.3V DC; V
IL
(min.) = 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
V
IH
(max.) = V
DD
+ 0.3V DC; V
IH
(max.) = V
DD
+ 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
V
DD
= 3.3V + 10%
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
DD
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
2
V
DD
+ 0.3
V
V
IL
Input LOW Voltage
(1)
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
DD
1
1
A
I
LO
Output Leakage
GND
V
OUT
V
DD
, Outputs Disabled
1
1
A
Note:
1.
V
IL
(min.) = 0.3V DC; V
IL
(min.) = 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
V
IH
(max.) = V
DD
+ 0.3V DC; V
IH
(max.) = V
DD
+ 2.0V AC (pulse width - 2.0 ns). Not 100% tested.
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
5
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-12ns
-15 ns
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
I
CC
V
DD
Operating
V
DD
= Max.,
CE = V
IL
Com.
--
35
--
30
mA
Supply Current
I
OUT
= 0 mA, f = Max.
Ind.
--
40
--
35
Auto
--
40
typ.
(2)
--
25
--
20
I
SB
1
TTL Standby
V
DD
= Max.,
Com.
--
20
--
20
mA
Current
V
IN
= V
IH
or V
IL
Ind.
--
20
--
20
(TTL Inputs)
CE
V
IH
, f = max
Auto
--
30
I
SB
2
CMOS Standby
V
DD
= Max.,
Com.
--
750
--
750
A
Current
CE
V
DD
0.2V,
Ind.
--
900
--
900
A
(CMOS Inputs)
V
IN
V
DD
0.2V, or
Auto
--
6
mA
V
IN
0.2V, f = 0
typ.
(2)
--
400
--
400
A
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
=3.3V, T
A
=25
0
C. Not 100% tested.
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Input/Output Capacitance
V
OUT
= 0V
8
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
6
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
AC TEST LOADS
Figure 1.
319
5 pF
Including
jig and
scope
353
OUTPUT
3.3V
Figure 2.
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-12 ns
-15 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
12
--
15
--
ns
t
AA
Address Access Time
--
12
--
15
ns
t
OHA
Output Hold Time
3
--
3
--
ns
t
ACE
CE Access Time
--
12
--
15
ns
t
DOE
OE Access Time
--
5
--
7
ns
t
HZOE
(2)
OE to High-Z Output
--
5
--
6
ns
t
LZOE
(2)
OE to Low-Z Output
0
--
0
--
ns
t
HZCE
(2)
CE to High-Z Output
0
5
0
6
ns
t
LZCE
(2)
CE to Low-Z Output
3
--
3
--
ns
t
BA
LB, UB Access Time
--
5
--
7
ns
t
HZB
(2)
LB, UB to High-Z Output
0
5
0
6
ns
t
LZB
(2)
LB, UB to Low-Z Output
0
--
0
--
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
Z
O
= 50
1.5V
50
OUTPUT
30 pF
Including
jig and
scope
AC TEST CONDITIONS
Parameter
Unit
Unit
(2.5V-3.6V)
(3.3V + 10%)
Input Pulse Level
0.4V to V
DD
-0.3V
0.4V to V
DD
-0.3V
Input Rise and Fall Times
1.5ns
1.5ns
Input and Output Timing
V
DD
/2
V
DD
/2 + 0.05
and Reference Level (V
Ref
)
Output Load
See Figures 1 and 2
See Figures 1 and 2
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
7
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
UB_CEDR2.eps
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB
READ CYCLE NO. 2
(1,3)
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (
CE = OE = V
IL
,
UB or LB = V
IL
)
Notes:
1.
WE is HIGH for a Read Cycle.
2. The device is continuously selected.
OE, CE, UB, or LB = V
IL
.
3. Address is valid prior to or coincident with
CE LOW transition.
8
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-12 ns
-15 ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
WC
Write Cycle Time
12
--
15
--
ns
t
SCE
CE to Write End
8
--
10
--
ns
t
AW
Address Setup Time
8
--
10
--
ns
to Write End
t
HA
Address Hold from Write End
0
--
0
--
ns
t
SA
Address Setup Time
0
--
0
--
ns
t
PBW
LB, UB Valid to End of Write
9
--
10
--
ns
t
PWE
1
WE Pulse Width (OE = HIGH)
8
--
10
--
ns
t
PWE
2
WE Pulse Width (OE = LOW)
10
--
12
--
ns
t
SD
Data Setup to Write End
6
--
7
--
ns
t
HD
Data Hold from Write End
0
--
0
--
ns
t
HZWE
(3)
WE LOW to High-Z Output
--
5
--
7
ns
t
LZWE
(3)
WE HIGH to Low-Z Output
0
--
0
--
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
9
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
WRITE CYCLE NO. 1
(1,2)
(
CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR1.eps
10
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
WRITE CYCLE NO. 2
(1)
(
WE Controlled, OE = HIGH during Write Cycle)
WRITE CYCLE NO. 3
(
WE Controlled: OE is LOW During Write Cycle)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
UB_CEWR3.eps
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
11
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
DATA UNDEFINED
t
WC
ADDRESS 1
ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
UB_CEWR4.eps
t
HD
t
SA
t
HZWE
ADDRESS
CE
UB, LB
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
WRITE CYCLE NO. 4
(
LB, UB Controlled, Back-to-Back Write)
(1,3)
Notes:
1. The internal Write time is defined by the overlap of
CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t
SA
, t
HA
, t
SD
, and t
HD
timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before
WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the
LB, UB pins can be used to control the Write function.
12
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
DATA RETENTION WAVEFORM
(
CE Controlled)
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Options
Min.
Typ.
(1)
Max.
Unit
V
DR
V
DD
for Data Retention
See Data Retention Waveform
1.8
--
3.6
V
I
DR
Data Retention Current
V
DD
= 2.0V,
CE
V
DD
0.2V
Ind.
--
0.4
0.9
mA
Auto
--
0.4
6
mA
t
SDR
Data Retention Setup Time
See Data Retention Waveform
0
--
--
ns
t
RDR
Recovery Time
See Data Retention Waveform
t
RC
--
--
ns
Note 1:
Typical values are measured at V
DD
= 3.3V, T
A
= 25
O
C. Not 100% tested.
V
DD
CE V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
13
Rev. C
02/03/06
ISSI
IS61WV12816BLL
IS64WV12816BLL
ORDERING INFORMATION:
Industrial Range: 40C to +85C
Speed (ns)
Order Part No.
Package
12 (15
1
)
IS61WV12816BLL-12BI
mini BGA (6mm x 8mm)
IS61WV12816BLL-12BLI
mini BGA (6mm x 8mm), Lead-free
IS61WV12816BLL-12TI
Plastic TSOP (Type II)
IS61WV12816BLL-12TLI
Plastic TSOP (Type II), Lead-free
Note:
1. Speed = 12ns for V
DD
= 3.3V + 10%. Speed = 15ns for V
DD
= 2.5V-3.6V
Automotive Range: 40C to +125C
Speed (ns)
Order Part No.
Package
15
IS64WV12816BLL-15BA3
mini BGA (6mm x 8mm)
IS64WV12816BLL-15TA3
Plastic TSOP (Type II)
IS64WV12816BLL-15TLA3
Plastic TSOP (Type II), Lead-free
PACKAGING INFORMATION
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. D
01/15/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Mini Ball Grid Array
Package Code: B (48-pin)
Notes:
1. Controlling dimensions are in millimeters.
mBGA - 6mm x 8mm
MILLIMETERS
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
--
--
1.20
--
--
0.047
A1
0.24
--
0.30
0.009
--
0.012
A2
0.60
--
--
0.024
--
--
D
7.90
--
8.10
0.311
--
0.319
D1
5.25 BSC
0.207 BSC
E
5.90
--
6.10
0.232
--
0.240
E1
3.75 BSC
0.148 BSC
e
0.75 BSC
0.030 BSC
b
0.30
0.35
0.40
0.012 0.014 0.016
mBGA - 8mm x 10mm
MILLIMETER
INCHES
Sym.
Min. Typ. Max.
Min. Typ. Max.
N0.
Leads
48
A
--
--
1.20
--
--
0.047
A1
0.24
--
0.30
0.009
--
0.012
A2
0.60
--
--
0.024
--
--
D
9.90
--
10.10
0.390
--
0.398
D1
5.25 BSC
0.207 BSC
E
7.90
--
8.10
0.311
--
0.319
E1
3.75 BSC
0.148 BSC
e
0.75 BSC
0.030 BSC
b
0.30
0.35
0.40
0.012 0.014 0.016
SEATING PLANE
A
A1
A2
A
B
C
D
E
F
G
H
e
e
D1
E1
E
D
b (48x)
Top View
Bottom View
6 5 4 3 2 1
1 2 3 4 5 6
A
B
C
D
E
F
G
H
PACKAGING INFORMATION
ISSI
Integrated Silicon Solution, Inc. -- www.issi.com --
1-800-379-4774
Rev. F
06/18/03
Copyright 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Plastic TSOP
Package Code: T (Type II)
D
SEATING PLANE
b
e
C
1
N/2
N/2+1
N
E1
A1
A
E
L
ZD
.
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
Plastic TSOP (T - Type II)
Millimeters
Inches
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
32
44
50
A
--
1.20
--
0.047
--
1.20
--
0.047
--
1.20
--
0.047
A1
0.05
0.15
0.002 0.006
0.05
0.15
0.002 0.006
0.05
0.15
0.002 0.006
b
0.30
0.52
0.012 0.020
0.30
0.45
0.012 0.018
0.30
0.45
0.012 0.018
C
0.12
0.21
0.005 0.008
0.12
0.21
0.005 0.008
0.12
0.21
0.005 0.008
D
20.82 21.08
0.820 0.830
18.31 18.52
0.721 0.729
20.82 21.08
0.820 0.830
E1
10.03 10.29
0.391 0.400
10.03 10.29
0.395 0.405
10.03 10.29
0.395 0.405
E
11.56 11.96
0.451 0.466
11.56 11.96
0.455 0.471
11.56 11.96
0.455 0.471
e
1.27 BSC
0.050 BSC
0.80 BSC
0.032 BSC
0.80 BSC
0.031 BSC
L
0.40
0.60
0.016 0.024
0.41
0.60
0.016 0.024
0.40
0.60
0.016 0.024
ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF
0
5
0
5
0
5
0
5
0
5
0
5