www.docs.chipfind.ru
1
LTC1477/LTC1478
The LTC
1477/LTC1478 protected high side switches
provide extremely low R
DS(ON)
switching with built-in
protection against short-circuit and thermal overload con-
ditions. A built-in charge pump generates gate drive
higher than the supply voltage to fully enhance the internal
NMOS switch. This switch has no parasitic body diode and
therefore no current flows through the switch when it is
turned off and the output is forced above the input supply
voltage. (DMOS switches have parasitic body diodes that
become forward biased under these conditions.)
Two levels of protection are provided by the
LTC1477/LTC1478. The first level of protection is short-
circuit current limit which is set at 2A. The short-circuit
current can be reduced to as low as 0.85A by disconnect-
ing portions of the power device (see Applications Infor-
mation). The second level of protection is provided by
thermal overload protection which limits the die tempera-
ture to approximately 130
C.
The LTC1477 single is available in 8-lead SO packaging.
The LTC1478 dual is available in 16-lead SO packaging.
Single and Dual Protected
High Side Switches
FEATURES
DESCRIPTIO
N
U
s
Extremely Low R
DS(ON)
Switch: 0.07
s
No Parasitic Body Diode
s
Built-In Short-Circuit Protection: 2A
s
Built-In Thermal Overload Protection
s
Operates from 2.7V to 5.5V
s
Inrush Current Limited
s
Ultralow Standby Current: 0.01
A
s
Built-In Charge Pump
s
Controlled Rise and Fall Times: t
R
= 1ms
s
Single Switch in 8-Pin SO Package
s
Dual Switch in Narrow 16-Pin SO Package
CHARGE
PUMP
GATE CHARGE
AND
DISCHARGE
CONTROL LOGIC
CURRENT LIMIT
AND THERMAL
SHUTDOWN
EN
V
INS
V
IN1
V
IN2
V
IN3
V
OUT
LTC1477/1478 TA01
*
*
*
*NMOS SWITCHES WITH NO PARASITIC BODY DIODES
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
Notebook Computer Power Management
s
Power Supply/Load Protection
s
Supply/Battery Switch-Over Circuits
s
Circuit Breaker Function
s
"Hot Swap" Board Protection
s
Peripheral Power Protection
APPLICATIO
N
S
U
Switch Output Voltage
OUTPUT CURRENT (A)
0
4.60
OUTPUT VOLTAGE (V)
4.70
4.80
4.90
5.00
5.20
0.25
0.5
0.75
1.00
LTC1477/1478 TP02
1.25
1.50
5.10
T
A
= 25
C
V
IN1
= V
IN2
= V
IN3
= V
INS
= 5V
SI PLIFIED BLOCK DIAGRA
M
W
W
2
LTC1477/LTC1478
Supply Voltage .......................................................... 7V
Enable Input Voltage ...................... (7V) to (GND 0.3V)
Output Voltage (OFF) (Note 1) ....... (7V) to (GND 0.3V)
Output Short-Circuit Duration .......................... Indefinite
Junction Temperature ........................................... 110
C
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
Operating Temperature
LTC1477C/LTC1478C .............................. 0
C to 70
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec) .................. 300
C
PACKAGE/ORDER I
N
FOR
M
ATIO
N
W
U
U
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Supply Voltage Range
2.7
5.5
V
I
VIN
Supply Current
Switch OFF, Enable = 0V
q
0.01
10
A
Switch ON, Enable = 5V, V
IN
= 5V
q
120
180
A
Switch ON, Enable = 3.3V, V
IN
= 3.3V
q
80
120
A
R
ON
ON Resistance
V
INS
= V
IN1
= V
IN2
= V
IN3
= 5V, I
OUT
= 1A
0.07
0.12
V
INS
= V
IN1
= V
IN2
= V
IN3
= 3.3V, I
OUT
= 1A
0.08
0.12
V
INS
= V
IN1
= 5V, V
IN2
= V
IN3
= NC, I
OUT
= 0.5A
0.12
0.20
V
INS
= V
IN1
= 3.3V, V
IN2
= V
IN3
= NC, I
OUT
= 0.5A
0.13
0.20
I
LKG
Output Leakage Current OFF
Switch OFF, Enable = 0V
q
20
A
I
SC
Short-Circuit Current Limit
V
INS
= V
IN1
= V
IN2
= V
IN3
= 5V, V
OUT
= 0V, (Note 4)
1.60
2.00
2.40
A
V
INS
= V
IN1
= 5V, V
IN2
= V
IN3
= NC, V
OUT
= 0V, (Note 4)
0.68
0.85
1.02
A
V
ENH
Enable Input High Voltage
3.0V
V
INS
5.5V
q
2.0
V
V
ENL
Enable Input Low Voltage
3.0V
V
INS
5.5V
q
0.8
V
I
EN
Enable Input Current
0V
V
EN
5.5V
q
1
A
t
D+R
Delay and Rise Time
R
OUT
= 100
, C
OUT
= 1
F, to 90% of Final Value
0.50
1.00
2.00
ms
increase the ON resistance of the switch. The LTC1478 GND pins must be
connected together. (See Pin Functions and Block Diagram for more detail.)
Note 3: Other channel turned OFF, i.e. AEN and BEN = 0V.
Note 4: The output is protected with fold-back current limit which reduces
the short-circuit (0V) currents below peak permissible current levels at
higher output voltages. (See Typical Performance Characteristics for
further detail on output current versus output voltage).
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: The V
OUT
pins must be connected together.
Note 2: The V
INS
and V
IN1
pins must be connected together. The V
IN2
and
V
IN3
pins are typically connected to V
INS
and V
IN1
pins but can be
selectively disconnected to reduce the short-circuit current limit and
Consult factory for Industrial and Military grade parts.
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AV
OUT
AV
IN
AV
INS
AEN
GND
BV
IN3
BV
IN2
BV
OUT
AV
OUT
AV
IN2
AV
IN3
GND
BEN
BV
INS
BV
IN1
BV
OUT
T
JMAX
= 110
C,
JA
= 100
C/ W
ELECTRICAL CHARACTERISTICS
V
INS
= V
IN1
= V
IN2
= V
IN3
= 5V (Note 2), T
A
= 25
C, unless otherwise noted. Each channel of the LTC1478 is tested separately (Note 3).
T
JMAX
= 110
C,
JA
= 120
C/ W
1
2
3
4
8
7
6
5
TOP VIEW
V
OUT
V
IN2
V
IN3
GND
V
OUT
V
IN1
V
INS
EN
S8 PACKAGE
8-LEAD PLASTIC SO
1477
S8 PART MARKING
LTC1477CS8
ORDER PART
NUMBER
LTC1478CS
ORDER PART
NUMBER
3
LTC1477/LTC1478
TYPICAL PERFOR
M
A
N
CE CHARACTERISTICS
U
W
Supply Current (ON)
Switch Resistance
Switch Resistance (5V)
SUPPLY VOLTAGE (V)
0
0
SUPPLY CURRENT (
A)
50
100
150
200
300
1
2
3
4
LTC1477/1478 TPC01
5
6
250
T
A
= 25
C
OUTPUT TURNED ON, NO LOAD
INPUT VOLTAGE (V)
1
0
SWITCH RESISTANCE (
)
0.05
0.10
0.15
0.20
0.30
2
3
4
5
LTC1477/1478 TPC02
6
7
0.25
T
A
= 25
C
V
IN2
= V
IN3
= NC
ALL V
IN
PINS
CONNECTED
JUNCTION TEMPERATURE (
C)
0
0
SWITCH RESISTANCE (
)
0.05
0.10
0.15
0.20
0.25
0.30
25
50
75
100
LTC1477/1478 TPC03
125
V
INS
= V
IN1
= 5V
V
IN2
= V
IN3
= NC
ALL V
IN
PINS = 5V
Switch Resistance (3.3V)
Short-Circuit Current
Output Current (5V)
JUNCTION TEMPERATURE (
C)
0
0
SWITCH RESISTANCE (
)
0.05
0.10
0.15
0.20
0.25
0.30
25
50
75
100
LTC1477/1478 TPC04
125
V
INS
= V
IN1
= 3.3V
V
IN2
= V
IN3
= NC
ALL V
IN
PINS = 3.3V
OUTPUT VOLTAGE (V)
0
0
OUTPUT CURRENT (A)
1
2
3
4
6
1
2
3
4
LTC1477/1478 TPC06
5
6
5
T
A
= 25
C
ALL V
IN
PINS = 5V
V
IN2
= V
IN3
= NC
SUPPLY VOLTAGE (V)
0
0
SHORT-CIRCUIT CURRENT (A) 0.5
1.0
1.5
2.0
3.0
1
2
3
4
LTC1477/1478 TPC05
5
6
2.5
T
J
= 25
C
ALL V
IN
PINS
CONNECTED
V
IN2
= V
IN3
= NC
Output Current (3.3V)
Inrush Current (5V)
Inrush Current (3.3V)
TIME (ms)
0.4
INRUSH CURRENT (A)
OUTPUT VOLTAGE (V)
0
1
2.8
LTC1477/1478 TPC09
6
4
0
0.4
1.2
2.0
2
3
2
0
0.8
1.6
2.4
C
OUT
= 470
F
R
OUT
= 10
C
OUT
= 10
F
R
OUT
= 10
CURRENT
LIMITED
T
J
= 25
C
ALL V
IN
PINS = 3.3V
OUTPUT VOLTAGE (V)
0
0
OUTPUT CURRENT (A)
1
2
3
4
6
1
2
3
4
LTC1477/1478 TPC07
5
6
5
T
A
= 25
C
ALL V
IN
PINS = 3.3V
V
IN2
= V
IN3
= NC
TIME (ms)
0.4
INRUSH CURRENT (A)
OUTPUT VOLTAGE (V)
0
1
2.8
LTC1477/1478 TPC08
6
4
0
0.4
1.2
2.0
2
3
2
0
0.8
1.6
2.4
C
OUT
= 470
F
R
OUT
= 10
C
OUT
= 10
F
R
OUT
= 10
CURRENT
LIMITED
T
J
= 25
C
ALL V
IN
PINS = 5V
4
LTC1477/LTC1478
LTC1477
EN (Pin 4): The enable input is a high impedance CMOS
gate with an ESD protection diode to ground and should
not be forced below ground. This input has about 100mV
of built-in hysteresis to ensure clean switching.
V
INS
, V
IN1
(Pins 3,2): The V
INS
supply pin must always be
connected to the V
IN1
supply pin (see Block Diagram). The
V
INS
supply pin provides power for the input control logic,
the current limit and thermal shutdown circuitry; plus
provides a sense connection to the input power supply.
The gate of the NMOS switch is powered by a charge pump
from the V
INS
supply pin (see Block Diagram). The V
IN1
supply pin provides connection to the drain of 1/2 of the
output power device.
V
IN2
, V
IN3
(Pins 7,6): The V
IN2
and V
IN3
supply pins are
typically tied to the V
INS
and V
IN1
supply pins for lowest ON
resistance; i.e., when all four V
IN
pins are connected
together the entire power device is connected (see Block
Diagram). Each auxiliary supply pin, V
IN2
and V
IN3
, is
connected to the drain of 1/4 of the power device. The V
IN2
and V
IN3
pins can be selectively disconnected to reduce
the short-circuit current limit at the expense of higher
R
DS(ON)
. (See Applications Information section for more
details.)
V
OUT
(Pins 1,8): The output pins of the LTC1477 must
always be tied together. The output is protected against
accidental short circuits to ground by a current limit circuit
which protects the system power supply and load against
damage. A second level of protection is provided by
thermal shutdown circuitry which limits the die tempera-
ture to 130
C.
LTC1478
AEN, BEN (Pins 4,12): The enable inputs are high imped-
ance CMOS gates with ESD protection diodes to ground
and should not be forced below ground. These inputs
have about 100mV of built-in hysteresis to ensure clean
switching.
AV
INS
, AV
IN1
, BV
INS
, BV
IN1
(Pins 3,2; 11,10): The AV
INS
or BV
INS
supply pin must always be connected to the
AV
IN1
or BV
IN1
supply pin (see Block Diagram). The AV
INS
and BV
INS
supply pins provide power for the input control
logic, the current limit and thermal shutdown circuitry;
plus, provides a sense connection to the input power
supply. The gate of the NMOS switch is powered by a
charge pump from the AV
INS
and BV
INS
supply pins (see
Block Diagram). The AV
IN1
and BV
IN1
supply pins provide
connection to the drain of 1/2 of the output power device.
AV
IN2
, AV
IN3
, BV
IN2
, BV
IN3
, (Pins 15,14; 7,6): The AV
IN2
,
AV
IN3
, BV
IN2
and BV
IN3
supply pins are typically tied to the
AV
INS
, AV
IN1
, BV
INS
and BV
IN1
supply pins for lowest ON
resistance; i.e., when all four AV
IN
, BV
IN
pins are con-
nected together the entire power device is connected (see
Block Diagram). Each auxiliary supply pin, AV
IN2
, AV
IN3
,
BV
IN2
and BV
IN3
, is connected to the drain of approxi-
mately 1/4 of the corresponding power device. The AV
IN2
,
AV
IN3
, BV
IN2
and BV
IN3
pins can be selectively discon-
nected to reduce the short-circuit current limit at the
expense of higher R
DS(ON)
. (See Applications Information
section for more details.)
AV
OUT
, BV
OUT
(Pins 1,16; 8,9): The outputs of the LTC1478
are protected against accidental short circuits to ground
by a current limit circuit which protects the system power
supplies and loads against damage. A second level of
protection is provided by thermal shutdown circuitry
which limits the die temperature to approximately 130
C.
PI
N
FU
N
CTIO
N
S
U
U
U
5
LTC1477/LTC1478
OPERATIO
N
U
(LTC1477 or single channel of LTC1478)
Input TTL-CMOS Converter
The LTC1477 enable input is designed to accommodate a
wide range of 3V and 5V logic families. The input threshold
voltage is approximately 1.4V with 100mV of hysteresis.
The input enables the bias generator, the gate charge
pump and the protection circuitry. Therefore, when the
enable input is turned off, the entire circuit is powered
down and the supply current drops below 1
A.
Ramped Switch Control
The LTC1477 gate charge pump includes circuitry which
ramps the NMOS switch on slowly (1ms typical rise time)
but turns it off much more quickly (typically 20
s).
Bias, Oscillator and Gate Charge Pump
When the switch is enabled, a bias current generator and
high frequency oscillator are turned on. The on-chip
capacitive charge pump generates approximately 12V of
gate drive for the internal low R
DS(ON)
NMOS switch from
the power supply. No external 12V supply is required to
switch the output.
Switch Protection
Two levels of protection are designed into the power
switch in the LTC1477. The switch is protected against
accidental short circuits with a current limit circuit which
limits the output current to typically 2A when the output is
shorted to ground. The LTC1477 also has thermal shut-
down set at approximately 130
C which limits the power
dissipation to safe levels.
LTC1478 Operation
The LTC1478 dual protected switch can be thought of as
two independent LTC1477 single protected switches. The
input supply voltages may be from separate power sources.
The ground connection, however, is common to both
channels and must be connected to the same potential.
(LTC1477 or single channel of LTC1478)
BLOCK DIAGRA
M
W
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Table 1. Effects of Disconnecting V
IN2
and V
IN3
ALL V
IN
PINS
V
IN3
V
IN2
AND V
IN3
CONNECTED
DISCONNECTED
DISCONNECTED
R
DS(ON)
0.07
0.09
0.12
I
LIMIT
2A
1.5A
0.85A
Note: 5V Operation
Note that there is an inverse relationship between output
current limit and switch resistance. This allows the tailor-
TTL-TO-CMOS
CONVERTER
OSCILLATOR
AND BIAS
CHARGE
PUMP
GATE CHARGE
AND
DISCHARGE
CONTROL LOGIC
CURRENT LIMIT
AND THERMAL
SHUTDOWN
EN
V
INS
V
IN1
V
IN2
V
IN3
V
OUT
LTC1477/1478 BD01
Tailoring I
LIMIT
and R
DS(ON)
for Load Requirements
The LTC1477 is designed to current limit at approximately
2A during a short circuit with all the V
IN
pins connected to
the input power supply. It is possible however, to reduce
this current by selectively disconnecting two of the four
power supply pins (V
IN2
and V
IN3
). Table 1 lists the effects
of disconnecting these pins on R
DS(ON)
and short-circuit
current limit
PDF 
ZIP