1
LTC1608
High Speed, 16-Bit, 500ksps
Sampling A/D Converter
with Shutdown
The LTC
1608 is a 500ksps, 16-bit sampling A/D con-
verter that draws only 270mW from
5V supplies. This
high performance device includes a high dynamic range
sample-and-hold, a precision reference and a high speed
parallel output. Two digitally selectable power shutdown
modes provide power savings for low power systems.
The LTC1608's full-scale input range is
2.5V. Outstand-
ing AC performance includes 90dB S/(N+D) and 100dB
THD at a sample rate of 500ksps.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 15MHz
bandwidth. The 68dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
The ADC has
P compatible,16-bit parallel output port.
There is no pipeline delay in conversion results. A separate
convert start input and a data ready signal (BUSY) ease
connections to FlFOs, DSPs and microprocessors.
s
A Complete, 500ksps 16-Bit ADC
s
90dB S/(N+D) and 100dB THD (Typ)
s
Power Dissipation: 270mW (Typ)
s
No Pipeline Delay
s
No Missing Codes Over Temperature
s
Nap (7mW) and Sleep (10
W) Shutdown Modes
s
Operates with Internal 15ppm/
C Reference
or External Reference
s
True Differential Inputs Reject Common Mode Noise
s
5MHz Full Power Bandwidth
s
2.5V Bipolar Input Range
s
36-Pin SSOP Package
s
Pin Compatible with the LTC1604
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
Telecommunications
s
Digital Signal Processing
s
Multiplexed Data Acquisition Systems
s
High Speed Data Acquisition
s
Spectrum Analysis
s
Imaging Systems
FREQUENCY (kHz)
0
40
20
0
150
200
1608 TA02
60
80
50
100
250
100
120
140
AMPLITUDE (dB)
f
SAMPLE
= 500kHz
f
IN
= 98.754kHz
SINAD = 86.7dB
THD = 92.6dB
LTC1608 4096 Point FFT
Circuitry in the LTC1608 is covered under US Patent #5,764,175
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2.2
F
10
F
10
F
10
22
F
4
6
DIFFERENTIAL
ANALOG INPUT
2.5V
REFCOMP
CONTROL
LOGIC
AND
TIMING
B15 TO B0
16-BIT
SAMPLING
ADC
+
10
F
5V OR
3V
P
CONTROL
LINES
D15 TO D0
OUTPUT
BUFFERS
16-BIT
PARALLEL
BUS
11 TO 26
1608 TA01
OGND
OV
DD
28
29
1
2
A
IN
+
A
IN
SHDN
CS
CONVST
RD
BUSY
33
32
31
30
27
7.5k
LTC1608
3
36
35
10
9
5V
5V
AV
DD
AV
DD
DV
DD
DGND
V
REF
8
AGND
AGND
7
AGND
5
AGND
34
5V
V
SS
10
F
2.5V
REF
10
F
1.75X
+
+
+
+
+
+
2
LTC1608
ORDER
PART NUMBER
AV
DD
= DV
DD
= OV
DD
= V
DD
(Notes 1, 2)
Supply Voltage (V
DD
) ................................................ 6V
Negative Supply Voltage (V
SS
) ............................... 6V
Total Supply Voltage (V
DD
to V
SS
) .......................... 12V
Analog Input Voltage
(Note 3) ......................... (V
SS
0.3V) to (V
DD
+ 0.3V)
V
REF
Voltage (Note 4) ................. 0.3V to (V
DD
+ 0.3V)
REFCOMP Voltage (Note 4) ......... 0.3V to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4) .................... 0.3V to 10V
Digital Output Voltage .................. 0.3V to (V
DD
+ 0.3V)
Power Dissipation ............................................. 500mW
Operating Temperature Range .................... 0
C to 70
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
LTC1608CG
LTC1608ACG
PUT
U
I
A
A
U
LOG
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Analog Input Range (Note 2)
4.75
V
DD
5.25V, 5.25
V
SS
4.75V,
2.5
V
V
SS
(A
IN
, A
IN
+
)
AV
DD
I
IN
Analog Input Leakage Current
CS = High
q
1
A
C
IN
Analog Input Capacitance
Between Conversions
43
pF
During Conversions
5
pF
t
ACQ
Sample-and-Hold Acquisition Time
380
ns
t
AP
Sample-and-Hold Acquisition Delay Time
1.5
ns
t
jitter
Sample-and-Hold Acquisition Delay Time Jitter
5
ps
RMS
CMRR
Analog Input Common Mode Rejection Ratio
2.5V < (A
IN
= A
IN
+
) < 2.5V
68
dB
The
q
denotes specifications that apply over the full operating temperature range, otherwise
specifications are at T
A
= 25
C.
T
JMAX
= 125
C,
JA
= 95
C/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TOP VIEW
G PACKAGE
36-LEAD PLASTIC SSOP
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
AV
DD
AV
DD
V
SS
SHDN
CS
CONV
RD
OV
DD
OGND
BUSY
D0
D1
D2
D3
D4
D5
D6
D7
A
IN
+
A
IN
V
REF
REFCOMP
AGND
AGND
AGND
AGND
DV
DD
DGND
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
C
C
HARA TERISTICS
CO
U
VERTER
LTC1608
LTC1608A
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
q
15
16
16
16
Bits
Integral Linearity Error
(Note 7)
q
1
4
0.5
2
LSB
Transition Noise
(Note 8)
0.7
0.7
LSB
RMS
Offset Error
(Note 9)
q
0.05
0.125
0.05
0.125
% FSR
Offset Tempco
(Note 9)
0.5
0.5
ppm/
C
Full-Scale Error
Internal Reference
0.125
0.25
0.125
0.25
%
External Reference
0.25
0.25
%
Full-Scale Tempco
I
OUT
(Reference) = 0, Internal Reference
15
15
ppm/
C
The
q
denotes specifications that apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. With Internal Reference (Notes 5, 6), unless otherwise noted.
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
Consult factory for parts specified with wider operating temperature ranges.
3
LTC1608
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/N
Signal-to-Noise Ratio
5kHz Input Signal
90
dB
100kHz Input Signal
88
dB
S/(N + D)
Signal-to-(Noise + Distortion) Ratio
5kHz Input Signal
90
dB
100kHz Input Signal (Note 10)
84
dB
THD
Total Harmonic Distortion
5kHz Input Signal
100
dB
Up to 5th Harmonic
100kHz Input Signal
91
dB
SFDR
Spurious Free Dynamic Range
100kHz Input Signal
94
dB
IMD
Intermodulation Distortion
f
IN1
= 29.37kHz, f
IN2
= 32.446kHz
88
dB
Full Power Bandwidth
5
MHz
Full Linear Bandwidth (S/(N + D)
84dB)
350
kHz
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
REF
Output Voltage
I
OUT
= 0
2.475
2.500
2.515
V
V
REF
Output Tempco
I
OUT
= 0
15
ppm/
C
V
REF
Line Regulation
4.75
V
DD
5.25V
0.01
LSB/V
5.25V
V
SS
4.75V
0.01
LSB/V
V
REF
Output Resistance
0
I
OUT
1mA
7.5
k
REFCOMP Output Voltage
I
OUT
= 0
4.375
V
DY
A
IC ACCURACY
U
W
T
A
= 25
C (Note 5)
I TER AL REFERE CE CHARACTERISTICS
U
U
U
T
A
= 25
C (Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
U
U
The
q
denotes specifications that apply over the full
operating temperature range, otherwise specifications are at T
A
= 25
C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
V
DD
= 5.25V
q
2.4
V
V
IL
Low Level Input Voltage
V
DD
= 4.75V
q
0.8
V
I
IN
Digital Input Current
V
IN
= 0V to V
DD
q
1 0
A
C
IN
Digital Input Capacitance
5
pF
V
OH
High Level Output Voltage
V
DD
= 4.75V, I
OUT
= 10
A
4.5
V
V
DD
= 4.75V, I
OUT
= 400
A
q
4.0
V
V
OL
Low Level Output Voltage
V
DD
= 4.75V, I
OUT
= 160
A
0.05
V
V
DD
= 4.75V, I
OUT
= 1.6mA
q
0.10
0.4
V
I
OZ
Hi-Z Output Leakage D15 to D0
V
OUT
= 0V to V
DD
, CS High
q
10
A
C
OZ
Hi-Z Output Capacitance D15 to D0
CS High (Note 11)
q
15
pF
I
SOURCE
Output Source Current
V
OUT
= 0V
1 0
mA
I
SINK
Output Sink Current
V
OUT
= V
DD
10
mA
4
LTC1608
POWER REQUIRE E TS
W
U
The
q
denotes specifications that apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
Positive Supply Voltage
(Notes 12, 13)
4.75
5.25
V
V
SS
Negative Supply Voltage
(Note 12)
4.75
5.25
V
I
DD
Positive Supply Current
CS = RD = 0V
q
22
35
mA
Nap Mode
CS = 0V, SHDN = 0V
1.5
2.4
mA
Sleep Mode
CS = 5V, SHDN = 0V
1
100
A
I
SS
Negative Supply Current
CS = RD = 0V
q
32
49
mA
Nap Mode
CS = 0V, SHDN = 0V
1
100
A
Sleep Mode
CS = 5V, SHDN = 0V
1
100
A
P
D
Power Dissipation
CS = RD = 0V
q
270
420
mW
Nap Mode
CS = 0V, SHDN = 0V
7.5
12
mW
Sleep Mode
CS = 5V, SHDN = 0V
0.01
1
mW
TI I G CHARACTERISTICS
U
W
The
q
denotes specifications that apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
SMPL(MAX)
Maximum Sampling Frequency
q
500
600
kHz
t
CONV
Conversion Time
q
1.0
1.45
1.8
s
t
ACQ
Acquisition Time
(Notes 11, 14)
q
400
ns
t
ACQ+CONV(MIN)
Throughput Time (Acquisition + Conversion)
q
1.67
2
s
t
1
CS to RD Setup Time
(Notes 11, 12, 15)
q
0
ns
t
2
CS
to CONVST
Setup Time
(Notes 11, 12)
q
10
ns
t
3
SHDN
to CS
Setup Time
(Notes 11, 12)
q
10
ns
t
4
SHDN
to CONVST
Wake-Up Time
CS = Low (Note 12)
400
ns
t
5
CONVST Low Time
(Note 12)
q
40
ns
t
6
CONVST to BUSY Delay
C
L
= 25pF
36
ns
q
80
ns
t
7
Data Ready Before BUSY
60
ns
q
32
ns
t
8
Delay Between Conversions
(Note 12)
q
200
ns
t
9
Wait Time RD
After BUSY
(Note 12)
q
5
ns
t
10
Data Access Time After RD
C
L
= 25pF
25
40
ns
q
50
ns
C
L
= 100pF (Note 11)
45
60
ns
q
75
ns
t
11
Bus Relinquish Time
30
50
ns
q
60
ns
t
12
RD Low Time
(Note 12)
q
t
10
ns
t
13
CONVST High Time
(Note 12)
q
40
ns
t
14
Aperture Delay of Sample-and-Hold
2
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
5
LTC1608
Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion
is measured at 100kHz. These results are used to calculate Signal-to-Nosie
Plus Distortion (SINAD).
Note 11: Guaranteed by design, not subject to test.
Note 12: Recommended operating conditions.
Note 13: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best performance ensure that CONVST returns high either within 250ns
after conversion start or after BUSY rises.
Note 14: The acquisition time would go up to 400ns and the conversion
time would go up to 1.8
s. However, the throughput time (acquisition +
conversion) is guaranteed by test to be 2
s max.
Note 15: If RD
precedes CS
, the output enable will be gated by CS
.
Note 4: When these pin voltages are taken below V
SS
, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, V
SS
= 5V, f
SMPL
= 500kHz, and t
r
= t
f
= 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specification apply for a single-
ended A
IN
+
input with A
IN
grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Typical RMS noise at the code transitions.
Note 9: Bipolar offset is the offset voltage measured from 0.5LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111.
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Integral Nonlinearity
vs Output Code
CODE
32768
32767
INL (LSB)
0
0.5
16384
16384
0
1608 G01
1.0
1.5
2.0
0.5
1.0
1.5
2.0
Differential Nonlinearity
vs Output Code
CODE
32768
32767
1.0
DNL (LSB)
0.8
0.4
0.2
0
1.0
0.4
16384
16384
0
1608 G02
0.6
0.6
0.8
0.2
S/(N + D) vs Input Frequency
and Amplitude
FREQUENCY (Hz)
100
90
80
70
60
50
40
30
20
10
0
SINAD (dB)
1608 G03
1k
10k
100k
1M
V
IN
= 0dB
V
IN
= 20dB
V
IN
= 40dB
Signal-to-Noise Ratio
vs Input Frequency
Distortion vs Input Frequency
Spurious-Free Dynamic Range
vs Input Frequency
FREQUENCY (Hz)
100
90
80
70
60
50
40
30
20
10
0
SIGNAL-TO-NOISE RATIO (dB)
1608 G04
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
100
110
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
1608 G05
1k
10k
100k
1M
THD
3RD
2ND
INPUT FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
100
110
SPURIOUS-FREE DYNAMIC RANGE (dB)
1608 G06
1k
10k
100k
1M
6
LTC1608
A
IN
+
(Pin 1): Positive Analog Input. The ADC converts the
difference voltage between A
IN
+
and A
IN
with a differen-
tial range of
2.5V. A
IN
+
has a
2.5V input range when
A
IN
is grounded.
A
IN
(Pin 2): Negative Analog Input. Can be grounded, tied
to a DC voltage or driven differentially with A
IN
+
.
V
REF
(Pin 3): 2.5V Reference Output. Bypass to AGND with
2.2
F tantalum in parallel with 0.1
F ceramic.
REFCOMP (Pin 4): 4.375V (Nominal) Reference Compen-
sation Pin. Bypass to AGND with 22
F tantalum in parallel
with 0.1
F ceramic. This is not recommended for use as
an external reference due to part-to-part output voltage
variations and glitches that occur during the conversion.
AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground
plane.
DV
DD
(Pin 9): 5V Digital Power Supply. Bypass to DGND
with 10
F tantalum in parallel with 0.1
F ceramic.
DGND (Pin 10): Digital Ground for Internal Logic. Tie to
analog ground plane.
D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15
is the Most Significant Bit.
BUSY (Pin 27): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data is
valid on the rising edge of BUSY.
OGND (Pin 28): Digital Ground for Output Drivers.
OV
DD
(Pin 29): Digital Power Supply for Output Drivers.
Bypass to OGND with 10
F tantalum in parallel with 0.1
F
ceramic.
RD (Pin 30): Read Input. A logic low enables the output
drivers when CS is low.
CONVST (Pin 31): Conversion Start Signal. This active
low signal starts a conversion on its falling edge when CS
is low.
CS (Pin 32): The Chip Select Input. Must be low for the ADC
to recognize CONVST and RD inputs.
SHDN (Pin 33): Power Shutdown. Drive this pin low with
CS low for nap mode. Drive this pin low with CS high for
sleep mode.
V
SS
(Pin 34): 5V Negative Supply. Bypass to AGND with
10
F tantalum in parallel with 0.1
F ceramic.
AV
DD
(Pin 35): 5V Analog Power Supply. Bypass to AGND
with 10
F tantalum in parallel with 0.1
F ceramic.
AV
DD
(Pin 36): 5V Analog Power Supply. Bypass to AGND
with 10
F tantalum in parallel with 0.1
F ceramic and
connect this pin to Pin 35 with a 10
resistor.
U
U
U
PI FU CTIO S
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Intermodulation Distortion
Power Supply Feedthrough
vs Ripple Frequency
Input Common Mode Rejection
vs Input Frequency
FREQUENCY (kHz)
0
40
20
0
200
1608 G07
60
80
50
100
150
250
100
120
140
AMPLITUDE (dB)
f
SAMPLE
= 500kHz
f
IN1
= 96.56kHz
f
IN2
= 99.98kHz
INPUT FREQUENCY (Hz)
1k
AMPLITUDE OF POWER SUPPLY
FEEDTHROUGH (dB)
0
20
40
60
80
100
120
140
10k
100k
1M
1608 G08
f
SAMPLE
= 500kHz
V
RIPPLE
= 10mV
V
SS
A
VDD
INPUT FREQUENCY (Hz)
1k
COMMON MODE REJECTION (dB)
80
70
60
50
40
30
20
10
0
10k
100k
1608 G14a
1M
7
LTC1608
U
U
W
FU CTIO AL BLOCK DIAGRA
Load Circuits for Access Timing
Load Circuits for Output Float Delay
1k
(A) Hi-Z TO VOH AND VOL TO VOH
C
L
1k
5V
DN
DN
(B) Hi-Z TO VOL AND VOH TO VOL
C
L
1608 TC01
1k
(A) VOH TO Hi-Z
C
L
1k
5V
DN
DN
(B) VOL TO Hi-Z
C
L
1608 TC02
TEST CIRCUITS
2.2
F
10
F
10
F
10
22
F
4
6
DIFFERENTIAL
ANALOG INPUT
2.5V
REFCOMP
4.375V
CONTROL
LOGIC
AND
TIMING
B15 TO B0
16-BIT
SAMPLING
ADC
+
10
F
5V OR
3V
P
CONTROL
LINES
D15 TO D0
OUTPUT
BUFFERS
16-BIT
PARALLEL
BUS
11 TO 26
1608 BD
OGND
OV
DD
28
29
1
2
A
IN
+
A
IN
SHDN
CS
CONVST
RD
BUSY
33
32
31
30
27
7.5k
3
36
35
10
9
5V
5V
AV
DD
AV
DD
DV
DD
DGND
V
REF
8
AGND
AGND
7
AGND
5
AGND
34
5V
V
SS
10
F
2.5V
REF
10
F
1.75X
+
+
+
+
+
+
APPLICATIO S I FOR ATIO
W
U
U
U
CONVERSION DETAILS
The LTC1608 uses a successive approximation algorithm
and internal sample-and-hold circuit to convert an analog
signal to a 16-bit parallel output. The ADC is complete with
a sample-and-hold, a precision reference and an internal
clock. The control logic provides easy interface to micro-
processors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion, the successive
approximation register (SAR) resets. Once a conversion
cycle has begun, it cannot be restarted.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the A
IN
+
and A
IN
inputs are
acquired during the acquire phase and the comparator
offset is nulled by the zeroing switches. In this acquire
phase, a duration of 480ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase, the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the C
SMPL
capacitors to ground,
transferring the differential analog input charge onto the
summing junctions. This input charge is successively
8
LTC1608
+
COMP
A
IN
+
C
SMPL
HOLD
SAMPLE
A
IN
C
SMPL
+C
DAC
+V
DAC
C
DAC
V
DAC
HOLD
HOLD
SAMPLE
HOLD
SAR
OUTPUT
LATCHES
16
D15
D0
1608 F01
ZEROING SWITCHES
Figure 1. Simplified Block Diagram
compared with the binary-weighted charges supplied by
the differential capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
differential DAC output balances the A
IN
+
and A
IN
input
charges. The SAR contents (a 16-bit data word) which
represent the difference of A
IN
+
and A
IN
are loaded into
the 16-bit output latches.
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
Internal Clock
The A/D converter has an internal clock that runs the A/D
conversion. The internal clock is factory trimmed to achieve
a typical conversion time of 1.45
s and a maximum
conversion time of 1.8
s over the full temperature range.
No external adjustments are required. The guaranteed
maximum acquisition time is 400ns. In addition, a through-
put time (acquisition + conversion) of 2
s and a minimum
sampling rate of 500ksps are guaranteed.
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3V Input/Output Compatible
The LTC1608 operates on
5V supplies, which makes the
device easy to interface to 5V digital systems. This device
can also talk to 3V digital systems: the digital input pins
(SHDN, CS, CONVST and RD) of the LTC1608 recognize
3V or 5V inputs. The LTC1608 has a dedicated output
supply pin (OV
DD
) that controls the output swings of the
digital output pins (D0 to D15, BUSY) and allows the part
to talk to either 3V or 5V digital systems. The output is
two's complement binary.
Power Shutdown
The LTC1608 provides two power shutdown modes, Nap
and Sleep, to save power during inactive periods. The Nap
mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from Nap to active is 200ns. In Sleep mode, all bias
currents are shut down and only leakage current remains
(about 1
A). Wake-up time from Sleep mode is much
longer since the reference circuit must power up and
settle. Sleep mode wake-up time is dependent on the
value of the capacitor connected to the REFCOMP (Pin 4).
The wake-up time is 80ms with the recommended 22
F
capacitor.
Shutdown is controlled by Pin 33 (SHDN). The ADC is in
shutdown when SHDN is low. The shutdown mode is
selected with Pin 32 (CS). When SHDN is low, CS low
selects nap and CS high selects sleep.
Figure 2a. Nap Mode to Sleep Mode Timing
t
3
SHDN
CS
1608 F02a
t
4
SHDN
CONVST
1608 F02b
Figure 2b. SHDN to CONVST Wake-Up Timing
9
LTC1608
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A falling edge
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY is
low during a conversion.
We recommend using a narrow logic low or narrow logic
high CONVST pulse to start a conversion as shown in
Figures 5 and 6. A narrow low or high CONVST pulse
prevents the rising edge of the CONVST pulse from upset-
ting the critical bit decisions during the conversion time.
Figure 4 shows the change of the differential nonlinearity
error versus the low time of the CONVST pulse. As shown,
if CONVST returns high early in the conversion (e.g.,
CONVST low time <300ns), accuracy is unaffected. Simi-
larly, if CONVST returns high after the conversion is over
t
2
t
1
CS
CONVST
RD
1608 F03
Figure 3. CS top CONVST Setup Timing
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
CONVST Pulse Returns High Early in the Conversion or After
the End of Conversion
0
CHANGE IN DNL (LSB)
1750
2000
1608 F04
250
500
1000
750
1250
1500
4
3
2
1
0
CONVST LOW TIME, t
5
(ns)
t
CONV
t
ACQ
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(e.g., CONVST low time >t
CONV
), accuracy is unaffected.
For best results, keep t
5
less than 500ns or greater than
t
CONV
.
Figures 5 through 9 show several different modes of
operation. In modes 1a and 1b (Figures 5 and 6), CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 7) CS is tied low. The falling edge of
CONVST signal starts the conversion. Data outputs are in
three-state until read by the MPU with the RD signal. Mode
2 can be used for operation with a shared data bus.
In slow memory and ROM modes (Figures 8 and 9), CS is
tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the com-
bined CONVST-RD signal. Conversions are started by the
MPU or DSP (no external sample clock is needed).
In slow memory mode, the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high, releasing the
processor and the processor takes RD (= CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
DIFFERENTIAL ANALOG INPUTS
Driving the Analog Inputs
The differential analog inputs of the LTC1608 are easy to
drive. The inputs may be driven differentially or as a single-
ended input (i.e., the A
IN
input is grounded). The A
IN
+
and
A
IN
inputs are sampled at the same instant. Any un-
wanted signal that is common mode to both inputs will be
reduced by the common mode rejection of the sample-
and-hold circuit. The inputs draw only one small current
10
LTC1608
(CONVST = )
Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
DATA (N 1)
D15 TO D0
CONVST
CS = RD = 0
BUSY
1608 F05
t
5
t
CONV
t
6
t
8
t
7
DATA
Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD
CONVST
CS = 0
BUSY
1608 F07
t
5
t
CONV
t
8
t
13
t
6
t
9
t
12
DATA N
D15 TO D0
t
11
t
10
RD
DATA
DATA (N 1)
D15 TO D0
CONVST
BUSY
1608 F06
t
CONV
t
6
t
13
t
7
CS = RD = 0
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
DATA
t
5
t
6
t
8
Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )
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LTC1608
RD = CONVST
CS = 0
BUSY
1608 F08
t
CONV
t
6
DATA (N 1)
D15 TO D0
DATA
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
DATA N
D15 TO D0
t
11
t
8
t
10
t
7
RD = CONVST
BUSY
CS = 0
1608 F09
t
CONV
t
6
DATA (N 1)
D15 TO D0
DATA
DATA N
D15 TO D0
t
10
t
11
t
8
Figure 8. Mode 2. Slow Memory Mode Timing
Figure 9. ROM Mode Timing
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spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1608
inputs can be driven directly. As source impedance in-
creases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts (settling time must be 200ns for full throughput
rate).
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (< 100
) at the closed-loop band-
width frequency. For example, if an amplifier is used in a
gain of +1 and has a unity-gain bandwidth of 50MHz, then
Figure 10. t
ACQ
vs Source Resistance
SOURCE RESISTANCE (
)
1
10
100
1k
10k
ACQUISITION TIME (
s)
10
1
0.1
0.01
1608 F10
the output impedance at 50MHz should be less than
100
. The second requirement is that the closed-loop
bandwidth must be greater than 15MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
12
LTC1608
LinearView is a trademark of Linear Technology Corporation.
APPLICATIO S I FOR ATIO
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The best choice for an op amp to drive the LTC1608 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifi-
cations are most critical and time domain applications
where DC accuracy and settling time are most critical.
The following list is a summary of the op amps that are
suitable for driving the LTC1608. More detailed informa-
tion is available in the Linear Technology databooks, the
LinearView
TM
CD-ROM and on our web site at:
www.linear-tech. com.
LT
1007: Low Noise Precision Amplifier. 2.7mA supply
current,
5V to
15V supplies, gain bandwidth product
8MHz, DC applications.
LT1097: Low Cost, Low Power Precision Amplifier. 300
A
supply current,
5V to
15V supplies, gain bandwidth
product 0.7MHz, DC applications.
LT1227: 140MHz Video Current Feedback Amplifier. 10mA
supply current,
5V to
15V supplies, low noise and low
distortion.
LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA sup-
ply current,
5V to
15V supplies, good AC/DC specs.
LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA sup-
ply current, good AC/DC specs.
LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback
Amplifiers. 6.3mA supply current per amplifier, good
AC/DC specs.
LT1468: 90MHz, 22V/
s 16-Bit Accurate Operational
Amplifier. 3.8mA supply current, excellent DC specs and
very low distortion performance to 100kHz.
LT1469: Dual 90MHz, 22V/
s 16-Bit Accurate Operational
Amplifier. 4.1mA supply current, excellent DC specs and
very low distortion performance to 100kHz.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1608 noise and distortion. The small-signal band-
width of the sample-and-hold circuit is 15MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
LTC1608
A
IN
+
A
IN
V
REF
REFCOMP
AGND
1608 F11
1
2
3
4
5
22
F
3000pF
100
ANALOG INPUT
Figure 11. RC Input Filter
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 11 shows a 3000pF
capacitor from A
IN
+
to ground and a 100
source resistor
to limit the input bandwidth to 530kHz. The 3000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sam-
pling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors can
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Input Range
The
2.5V input range of the LTC1608 is optimized for low
noise and low distortion. Most op amps also perform well
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special transla-
tion circuitry.
Some applications may require other input ranges. The
LTC1608 differential inputs and reference circuitry can ac-
commodate other input ranges often with little or no addi-
tional circuitry. The following sections describe the refer-
ence and input circuitry and how they affect the input range.
Internal Reference
The LTC1608 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.500V. It is connected internally to a reference
amplifier and is available at V
REF
(Pin 3) (see Figure 12a).
13
LTC1608
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R2
12k
R3
16k
REFERENCE
AMP
22
F
REFCOMP
AGND
V
REF
R1
7.5k
3
4
5
2.500V
4.375V
LTC1608
1608 F12a
BANDGAP
REFERENCE
Figure 12a. LTC1608 Reference Circuit
1
2
3
0.1
F
22
F
ANALOG
INPUT
1608 F12b
LT1019A-2.5
V
OUT
V
IN
5V
A
IN
+
A
IN
V
REF
LTC1608
AGND
REFCOMP
5
4
+
Figure 12b. Using the LT1019-2.5 as an External Reference
A 7.5k resistor is in series with the output so that it can be
easily overdriven by an external reference or other
circuitry (see Figure 12b). The reference amplifier gains
the voltage at the V
REF
pin by 1.75 to create the required
internal reference voltage. This provides buffering
between the V
REF
pin and the high speed capacitive DAC.
The reference amplifier compensation pin (REFCOMP, Pin
4) must be bypassed with a capacitor to ground. The
reference amplifier is stable with capacitors of 22
F or
greater. Using a 0.1
F ceramic in parallel is recommended.
The V
REF
pin can be driven with a DAC or other means
shown in Figure 13. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1608 reference amplifier will limit
the bandwidth and settling time of this circuit. A settling
time of 20ms should be allowed for after a reference
adjustment.
LTC1608
A
IN
+
ANALOG INPUT
2V TO 2.7V
DIFFERENTIAL
A
IN
V
REF
REFCOMP
AGND
1608 F13
1
2
3
4
5
22
F
LTC1450
2V TO 2.7V
Figure 13. Driving V
REF
with a DAC
Figure 14a. CMRR vs Input Frequency
INPUT FREQUENCY (Hz)
1k
COMMON MODE REJECTION (dB)
80
70
60
50
40
30
20
10
0
10k
100k
1608 G14a
1M
Differential Inputs
The LTC1608 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of A
IN
+
A
IN
independent of the
common mode voltage (see Figure 15a). The common
mode rejection holds up to extremely high frequencies
(see Figure 14a). The only requirement is that both inputs
can not exceed the AV
DD
or V
SS
power supply voltages.
Integral nonlinearity errors (INL) and differential nonlin-
earity errors (DNL) are independent of the common mode
voltage, however, the bipolar zero error (BZE) will vary.
The change in BZE is typically less than 0.1% of the
common mode voltage. Dynamic performance is also
affected by the common mode voltage. THD will degrade
as the inputs approach either power supply rail, from 96dB
with a common mode of 0V to 86dB with a common mode
of 2.5V or 2.5V.
14
LTC1608
APPLICATIO S I FOR ATIO
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LTC1608
A
IN
+
A
IN
V
REF
0V TO
5V
2.5V
REFCOMP
AGND
1608 F14b
1
2
3
4
5
22
F
ANALOG INPUT
+
Figure 14b. Selectable 0V to 5V or
2.5V Input Range
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 14b shows a circuit that
converts a 0V to 5V analog input signal with only an
additional buffer that is not in the signal path.
Full-Scale and Offset Adjustment
Figure 15a shows the ideal input/output characteristics
for the LTC1608. The code transitions occur midway
between successive integer LSB values (i.e., FS +
0.5LSB, FS + 1.5LSB, FS + 2.5LSB,... FS 1.5LSB,
FS 0.5LSB). The output is two's complement binary with
1LSB = FS ( FS)/65536 = 5V/65536 = 76.3
V.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 15b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the A
IN
input. For zero offset error, apply
38
V (i.e., 0.5LSB) at A
IN
+
and adjust the offset at the
A
IN
input by varying the output voltage of pin V
OUTA
from
the LTC1662 until the output code flickers between 0000
0000 0000 0000 and 1111 1111 1111 1111. For full-scale
adjustment, an input voltage of 2.499886V (FS/2 1.5LSBs)
is applied to A
IN
+
and the output voltage of pin V
OUTB
is
adjusted until the output code flickers between 0111 1111
1111 1110 and 0111 1111 1111 1111.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best per-
formance from the LTC1608, a printed circuit board with
ANALOG
INPUT
1608 F15b
1
2
3
80.6k
1%
OFFSET ADJ RANGE:
0.125%
FULL-SCALE ADJ RANGE:
0.25%
R1
40.2k
4
5
0.1
F
5V
22
F
5V
R3
1.5M
R2
100
+
2.2
F
+
A
IN
+
A
IN
V
REF
REFCOMP
AGND
LTC1608
LTC1662
CS/LD
SCK
SDI
REF
V
OUTA
GND
V
CC
V
OUTB
Figure 15b. Offset and Full-Scale Adjust Circuit
1608 F15a
011...111
011...110
000...001
000...000
111...111
111...110
100...001
100...000
FS 1LSB
(FS 1LSB)
INPUT VOLTAGE (A
IN
+
A
IN
)
OUTPUT CODE
Figure 15a. LTC1608 Transfer Characteristics
ground plane is required. Layout should ensure that digital
and analog signal lines are separated as much as possible.
Particular care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.The
analog input should be screened by AGND.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC's DGND) and all other
analog grounds should be connected to this single analog
ground point. The REFCOMP bypass capacitor and the
DV
DD
bypass capacitor should also be connected to this
analog ground plane. No other digital grounds should be
connected to this analog ground plane. Low impedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as possible. In
15
LTC1608
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applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1608 has differential inputs to minimize noise
coupling. Common mode noise on the A
IN
+
and A
IN
leads
will be rejected by the input CMRR. The A
IN
input can be
used as a ground sense for the A
IN
+
input; the LTC1608
will hold and convert the difference voltage between A
IN
+
and A
IN
. The leads to A
IN
+
(Pin 1) and A
IN
(Pin 2) should
be kept as short as possible. In applications where this is
not possible, the A
IN
+
and A
IN
traces should be run side
by side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10
F or 22
F
bypass capacitors should be used at the V
DD
and REFCOMP
pins as shown in Figure 16 and in the Typical Application
on the first page of this data sheet. Surface mount ceramic
capacitors such as Taiyo Yuden's LMK325BJ106MN and
LMK432BJ226MM provide excellent bypassing in a small
board space. Alternatively, 10
F tantalum capacitors in
parallel with 0.1
F ceramic capacitors can be used. By-
pass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
EXAMPLE LAYOUT
Figures 17a, 17b, 17c, 17d and 17e show the schematic
and layout of an evaluation board. The layout demon-
strates the proper use of decoupling capacitors and ground
plane with a 4-layer printed circuit board.
DC PERFORMANCE
The noise of an ADC can be evaluated in two ways: signal-
to-noise raio (SNR) in frequency domain and histogram in
time domain. The LTC1608 excels in both. Figure 19a
demonstrates that the LTC1608 has an SNR of over 90dB
in frequency domain. The noise in the time domain histo-
gram is the transition noise associated with a high resolu-
tion ADC which can be measured with a fixed DC signal
applied to the input of the ADC. The resulting output codes
are collected over a large number of conversions. The
shape of the distribution of codes will give an indication of
the magnitude of the transition noise. In Figure 18, the
distribution of output codes is shown for a DC input that
has been digitized 4096 times. The distribution is Gaussian
and the RMS code transition noise is about 0.66LSB. This
corresponds to a noise level of 90.9dB relative to full scale.
Adding to that the theoretical 98dB of quantization error
for 16-bit ADC, the resultant corresponds to an SNR level
of 90.1dB which correlates very well to the frequency
domain measurements in Dynamic Performance section.
DYNAMIC PERFORMANCE
The LTC1608 has excellent high speed sampling capabil-
ity. Fast fourier transform (FFT) test techniques are used
to test the ADC's frequency response, distortions and
Figure 16. Power Supply Grounding Practice
1608 F16
A
IN
+
V
SS
OV
DD
DGND
AV
DD
LTC1608
DIGITAL
SYSTEM
ANALOG
INPUT
CIRCUITRY
AGND
5, 6, 7, 8
2
34
29
DV
DD
OGND
28
10
1
REFCOMP
4
22
F
V
REF
3
2.2
F
A
IN
10
F
36
10
F
AV
DD
35
10
F
10
F
+
9
10
F
16
LTC1608
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C4 1
F
OV
DD
AV
DD1
AV
DD2
V
SS
SHDN
CS
CONV
RD
OV
DD
OGND
BUSY
D0
D1
D2
D3
D4
D5
D6
D7
A
IN
+
A
IN
V
REF
REFCOMP
AGND
AGND
AGND
AGND
DV
DD
DGND
D15
D14
D13
D12
D11
D10
D9
D8
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
U1 LTC1608
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK
1
2
3
4
5
6
7
8
9
10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
U2 MC74HC574ADT
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
U3 74HC574
OV
DD
A
IN
+
A
IN
C11
2.2
F
C13
22
F
R6
10
C10 22
F
5V
C12
22
F
OV
DD
C9
1
F
E4
GND
E1
5V
E5
3V
E2
5V
E6
GND 5V
JP1
C7
1
F
C6
1
F
C5 1
F
5V
C8
0.1
F
R2
10k
C1
0.1
F
E7
GND
CLK
MSB
J1
CONN20
C28
22
F
R3
10
R1
51k
OV
DD
J2
CONVERT
START
R5
10k
JP3
OV
DD
U5
TC7SH08FUTE85L
R4 10k
E3
V
REF
C3 0.1
F
JP2
OV
DD
U6
TC7SH04F
LSB
+
U4A
LT1469
4
5V
8
5V
C21
0.1
F
C27
100pF
C20
0.1
F
C25
100pF
C24
100pF
C26
1000pF
A
IN
+
(U1-1)
A
IN
(U1-2)
R15
100
R16
10k
C17
10pF
C18
10pF
C15 10pF
C16 10pF
R8 402
R9
402
R12
50
R14
50
R11
50
R13
50
1
3
2
+
U4B
LT1469
7
6
5
C23
100pF
C22
100pF
C19
1000pF
R10
50
R17
10k
J3
A
IN
+
J4
A
IN
C14
1000pF
R7
50
+
+
+
Figure 17a. LTC1608 Suggested Evaluation Circuit Schematic
17
LTC1608
APPLICATIO S I FOR ATIO
W
U
U
U
CODE
5 4 3 2 1 0
1
2
3
4
5
COUNT
2500
2000
1500
1000
500
0
1608 F18
Figure 18. Histogram for 4096 Conversions
ANALOG GROUND PLANE
DIGITAL GROUND PLANE
ANALOG GROUND PLANE
DIGITAL GROUND PLANE
Figure 17b. Suggested Evaluation Circuit Board.
Component Side Silkscreen and Signal Traces
Figure 17c. Suggested Evaluation Circuit Board.
Bottom Side Showing Signal Traces
Figure 17d. Suggested Evaluation Circuit Board. Inner Layer 1
Showing Separate Analog and Digital Ground Planes
Figure 17e. Suggested Evaluation Circuit Board. Inner Layer 2
Showing Separate Analog and Digital Ground Planes
noise at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC's spectral content can be examined for
frequencies outside the fundamental. Figures 19a and 19b
show typical LTC1608 FFT plots.
Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental
input frequency to the RMS amplitude of all other fre-
quency components at the A/D output. The output is band
limited to frequencies from above DC and below half the
sampling frequency. Figure 19a shows a typical spectral
content with a 500kHz sampling rate and a 3kHz input.
18
LTC1608
APPLICATIO S I FOR ATIO
W
U
U
U
The dynamic performance is excellent for input frequen-
cies up to and beyond the Nyquist limit of 250kHz.
Effective Number of Bits
The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
ENOB = [S/(N + D) 1.76]/6.02
where ENOB is the effective number of bits of resolution
and S/(N + D) is expressed in dB. At the maximum
sampling rate of 500kHz, the LTC1608 maintains above 14
bits up to the Nyquist input frequency of 250kHz (refer to
Figure 20).
FREQUENCY (kHz)
0
40
20
0
200
1608 F19b
60
80
50
100
150
250
100
120
140
AMPLITUDE (dB)
f
SAMPLE
= 500kHz
f
IN
= 98.754kHz
SINAD = 86.7dB
THD = 92.6dB
Figure 19b. Even with Inputs at 100kHz, the
LTC1608's Dynamic Linearity Remains Robust
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD
Log
V
V
V
Vn
V
=
+
+
+
20
2
3
4
1
2
2
2
2
...
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is
shown in Figure 21. The LTC1608 has good distortion
performance up to the Nyquist frequency and beyond.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa
nfb, where m and n = 0,
1, 2, 3, etc. For example, the 2nd order IMD terms include
FREQUENCY (kHz)
0
40
20
0
200
1608 F19a
60
80
50
100
150
250
100
120
140
AMPLITUDE (dB)
f
SAMPLE
= 500kHz
f
IN
= 2.807kHz
SINAD = 88.9dB
THD = 98dB
Figure 19a. This FFT of the LTC1608's Conversion of a
Full-Scale 3kHz Sine Wave Shows Outstanding Response
with a Very Low Noise Floor When Sampling at 500ksps
FREQUENCY (Hz)
1k
EFFECTIVE BITS
SINAD (dB)
16
15
14
13
12
11
10
9
8
98
92
86
80
74
68
62
56
50
10k
100k
1M
1608 F20
Figure 20. Effective Bits and Signal/(Noise + Distortion)
vs Input Frequency
19
LTC1608
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Figure 22. Intermodulation Distortion Plot
FREQUENCY (kHz)
0
40
20
0
200
1608 F22
60
80
50
100
150
250
100
120
140
AMPLITUDE (dB)
f
SAMPLE
= 500kHz
f
IN1
= 96.56kHz
f
IN2
= 99.98kHz
(fa
fb). If the two input sine waves are equal in
magnitude, the value (in decibels) of the 2nd order IMD
products can be expressed by the following formula:
IMD fa
fb
Log
Amplitude
( )
=
20
at (fa
fb)
Amplitude at fa
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 84dB (13.66 effective bits).
The LTC1608 has been designed to optimize input band-
width, allowing the ADC to undersample input signals with
frequencies above the converter's Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
APPLICATIO S I FOR ATIO
W
U
U
U
INPUT FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
100
110
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
1608 F21
1k
10k
100k
1M
THD
3RD
2ND
Figure 21. Distortion vs Input Frequency
U
PACKAGE DESCRIPTIO
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
G36 SSOP 0501
.13 .22
(.005 .009)
0
8
.55 .95
(.022 .037)
5.20 5.38**
(.205 .212)
7.65 7.90
(.301 .311)
1 2 3 4 5 6 7 8 9 10 11 12
14 15 16 17 18
13
12.67 12.93*
(.499 .509)
25
26
22 21 20 19
23
24
27
28
29
30
31
32
33
34
35
36
1.73 1.99
(.068 .078)
.05 .21
(.002 .008)
.65
(.0256)
BSC
.25 .38
(.010 .015)
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
20
LTC1608
1608f LT/TP 0601 2K PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1410
12-Bit, 1.25Msps,
5V ADC
71.5dB SINAD at Nyquist, 150mW Dissipation
LTC1415
12-Bit, 1.25Msps, Single 5V ADC
55mW Power Dissipation, 72dB SINAD
LTC1418
14-Bit, 200ksps, Single 5V ADC
15mW, Serial/Parallel
10V
LTC1419
Low Power 14-Bit, 800ksps ADC
True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation
LTC1604
16-Bit, 333ksps,
5V ADC
90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608
LTC1605
16-Bit, 100ksps, Single 5V ADC
10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606
LTC1606
16-Bit, 250ksps, Single 5V ADC
10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605
SAMPLING ADCs
D15 TO D0
V
SS
AGND
AGND
AGND
AGND
REFCOMP
4.375V
11 TO 26
1608 TA03
CH7
+
+
+
+
CH0
+
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
LTC1391
LTC1391
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
V
+
D
V
D
OUT
D
IN
CS
CLK
GND
CH7
CH0
1
F
5V
D
IN
CS
CLK
5V
5V
10
2.2
F
10
F
5V
10
F
5V
10
34
9
35
36
3
4
10
F
5V
1
F
10
F
3000pF
3000pF
5
1
22
F
A
IN
+
V
REF
AV
DD
AV
DD
DV
DD
DGND
OV
DD
OGND 28
P
CONTROL
LINES
5V OR
3V
10
F
SHDN
CS
CONVST
RD
BUSY
33
32
31
30
27
A
IN
2
6
7
8
1
F
5V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
V
+
D
V
D
OUT
D
IN
CS
CLK
GND
16-BIT
SAMPLING
ADC
+
+
+
+
+
1.75X
2.5V
REF
CONTROL
LOGIC
AND
TIMING
OUTPUT
BUFFERS
16-BIT
PARALLEL
BUS
7.5k
LTC1608
B15 TO B0
+
29
P
CONTROL
LINES
+
DACs
PART NUMBER
DESCRIPTION
COMMENTS
LTC1595
16-Bit Serial Multiplying I
OUT
DAC in SO-8
1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
LTC1596
16-Bit Serial Multiplying I
OUT
DAC
1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
LTC1597/LTC1591
16-Bit/14-Bit Parallel, Multiplying DACs
1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
LTC1650
16-Bit Serial V
OUT
DAC
Low Power, Low Gritch, 4-Quadrant Multiplication
Using the LTC1608 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
TYPICAL APPLICATIO
U
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