1
LTC3413
sn3413 3413fs
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
3A, 2MHz Monolithic
Synchronous Regulator for
DDR/QDR Memory Termination
s
High Efficiency: Up to 90%
s
3A Output Current
s
Symmetrical Source and Sink Output Current Limit
s
Low R
DS(ON)
Internal Switch: 85m
s
No Schottky Diode Required
s
2.25V to 5.5V Input Voltage Range
s
V
OUT
= V
REF
/2
s
1% Output Voltage Accuracy
s
Programmable Switching Frequency: Up to 2MHz
s
Power Good Output Voltage Monitor
s
Overtemperature Protected
s
Available in 16-Lead TSSOP Exposed Pad Package
The LTC
3413 is a high efficiency monolithic synchro-
nous step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.25V to 5.5V and provides a
regulated output voltage equal to (0.5)V
REF
while sourcing
or sinking up to 3A of output current. An internal voltage
divider reduces component count and eliminates the need
for external resistors by dividing the reference voltage in
half. The internal synchronous power switch with 85m
on-resistance increases efficiency and eliminates the need
for an external Schottky diode. Switching frequencies up
to 2MHz are set by an external resistor.
Forced-continuous operation in the LTC3413 reduces
noise and RF interference. Fault protection is provided by
an overcurrent comparator that limits output current dur-
ing both sourcing and sinking operations. Adjustable
compensation allows the transient response to be opti-
mized over a wide range of loads and output capacitors.
s
Bus Termination: DDR and QDR
TM
Memory,
SSTL, HSTL, ...
s
Notebook Computers
s
Distributed Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
Figure 1a. High Efficiency Bus Termination Supply
Figure 1b. Efficiency vs Load Current
PV
IN
SV
IN
PGOOD
SW
V
REF
22
F
4.7M
309k
L1: VISHAY DALE IHLP-2525CZ-01 0.47
C
OUT
: TDK C4532X5R0J107M
V
IN
2.5V
C
OUT
100
F
2
3413 F01a
V
OUT
1.25V
3A
L1
0.47
H
LTC3413
PGND
RUN/SS
SGND
I
TH
R
T
V
FB
330pF
2200pF
5.11k
LOAD CURRENT (A)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.1
1
10
3413 F01b
30
20
10
0
90
100
V
IN
= 2.5V
f = 1MHz
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.
2
LTC3413
sn3413 3413fs
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Input Voltage Range
2.25
5.5
V
V
FB
Feedback Voltage Accuracy
(Note 3)
q
1
%
I
FB
Voltage Feedback Leakage Current
0.4
A
I
RUN
RUN/SS Leakage Current
1
A
V
FB
Feedback Voltage Line Regulation
V
IN
= 2.7V to 5.5V (Note 3)
q
0.04
0.2
%/V
V
LOADREG
Feedback Voltage Load Regulation
Measured in Servo Loop, V
ITH
= 0.36V
q
0.02
0.2
%
Measured in Servo Loop, V
ITH
= 0.84V
q
0.02
0.2
%
V
PGOOD
Power Good Range
10
12
%
R
PGOOD
Power Good Pull-Down Resistance
120
200
I
Q
Input DC Bias Current
(Note 4)
Active Current
V
FB
= 1.5V, V
ITH
= 1.4V, V
REF
= 2.5V
250
330
A
Shutdown
V
RUN
= 0V (Note 7)
0.02
1
A
f
OSC
Switching Frequency
R
OSC
= 309k
0.88
1.00
1.12
MHz
Switching Frequency Range
(Note 6)
0.30
2.00
MHz
R
PFET
R
DS(ON)
of P-Channel FET
I
SW
= 300mA
85
110
m
R
NFET
R
DS(ON)
of N-Channel FET
I
SW
= 300mA
65
90
m
I
LIMIT
Peak Current Limit
3.8
5.4
A
V
UVLO
Undervoltage Lockout Threshold
1.75
2
2.25
V
I
LSW
SW Leakage Current
V
RUN
= 0V, V
IN
= 5.5V (Note 7)
0.1
1
A
V
RUN
RUN Threshold
0.5
0.65
0.8
V
FE PACKAGE
16-LEAD PLASTIC TSSOP
EXPOSED PAD (PIN 17)
MUST BE SOLDERED TO SGND
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
SV
IN
PGOOD
I
TH
V
FB
R
T
V
REF
RUN/SS
SGND
PV
IN
SW
SW
PGND
PGND
SW
SW
PV
IN
17
(Note 1)
SV
IN
, PV
IN
Supply Voltages ........................ 0.3V to 6V
I
TH
, RUN/SS, V
FB
, PGOOD Voltages ........... 0.3V to V
IN
V
REF
Voltage .............................................. 0.3V to V
IN
SW Voltage .................................. 0.3V to (V
IN
+ 0.3V)
Peak SW Sink and Source Current ........................ 7.2A
Operating Ambient Temperature Range
(Note 2) .............................................. 40
C to 85
C
Junction Temperature (Notes 5, 8) ...................... 125
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
ORDER PART
NUMBER
LTC3413EFE
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
IN
= 3.3V, unless otherwise noted.
T
JMAX
= 125
C,
JA
= 38
C/ W,
JC
= 10
C/ W
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3413E is guaranteed to meet performance specifications
from 0
C to 70
C. Specifications over the 40
C to 85
C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3413E is tested in a feedback loop that adjusts V
FB
to
achieve a specified error amplifier output voltage (I
TH
).
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
as follows: LTC3413E: T
J
= T
A
+ (P
D
38
C/W)
Note 6: 2MHz operation is guaranteed by design and not production tested.
Note 7: Shutdown current and SW leakage current are only tested during
wafer sort.
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125
C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
FE PART
MARKING
3413EFE
3
LTC3413
sn3413 3413fs
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Switch On-Resistance
vs Temperature
Switch On-Resistance
vs Input Voltage
TEMPERATURE (
C)
40
0
ON-RESISTANCE (m
)
20
40
60
80
0
40
80
120
3413 G04
100
120
20
20
60
100
PFET
ON-RESISTANCE
NFET
ON-RESISTANCE
V
IN
= 3.3V
INPUT VOLTAGE (V)
2.5
0
ON-RESISTANCE (m
)
20
40
60
80
100
120
3
3.5
4
4.5
3413 G05
5
PFET ON-RESISTANCE
NFET ON-RESISTANCE
T
A
= 25
C
INPUT VOLTAGE (V)
2.5
0
LEAKAGE CURRENT (nA)
0.5
1.0
1.5
2.0
2.5
3
3.5
4
4.5
3413 G06
5
5.5
PFET
NFET
T
A
= 25
C
Switch Leakage vs Input Voltage
Frequency vs R
OSC
Frequency vs Input Voltage
Frequency vs Temperature
R
OSC
(k
)
54
0
FREQUENCY (kHz)
500
1500
2000
2500
654 754 854 954
4500
3413 G07
1000
154 254 354 454 554
3000
3500
4000
V
IN
= 3.3V
T
A
= 25
C
INPUT VOLTAGE (V)
2.5
990
FREQUENCY (kHz)
1000
1010
1020
1030
1050
3
3.5
4
4.5
3213 G08
5
5.5
1040
T
A
= 25
C
TEMPERATURE (
C)
40
990
FREQUENCY (kHz)
992
996
998
1000
1010
1004
0
40
60
3413 G09
994
1006
1008
1002
20
20
80
100 120
V
IN
= 3.3V
LOAD CURRENT (A)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.1
1
10
3413 G01
30
20
10
0
90
100
V
IN
= 2.5V
V
OUT
= 1.25V
T
A
= 25
C
V
IN
= 3.3V
INPUT VOLTAGE (V)
2.5
EFFICIENCY (%)
50
60
70
4.0
5.0
3413 G02
40
30
20
3.0
3.5
4.5
80
90
100
5.5
LOAD = 1A
LOAD = 3A
LOAD = 100mA
V
OUT
= 1.25V
T
A
= 25
C
LOAD CURRENT (A)
0
0.30
V
OUT
/V
OUT
(%)
0.25
0.20
0.15
0.10
0
0.5
1.0
1.5
2.0
3413 G03
2.5
3.0
0.05
T
A
= 25
C
Efficiency vs Load Current
Efficiency vs Input Voltage
Load Regulation
4
LTC3413
sn3413 3413fs
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Quiescent Current vs Input Voltage
Load Step Transient
INPUT VOLTAGE (V)
2.0
200
250
350
3.5
4.5
3413 G10
150
100
2.5
3.0
4.0
5.0
5.5
50
0
300
QUIESCENT CURRENT (
A)
T
A
= 25
C
OUTPUT
VOLTAGE
100mV/DIV
INDUCTOR
CURRENT
1A/DIV
V
IN
= 2.5V
20
s/DIV
3413 G11
V
OUT
= 1.25V
LOAD STEP = 0A TO 3A
Load Step Transient
OUTPUT
VOLTAGE
100mV/DIV
INDUCTOR
CURRENT
1A/DIV
V
IN
= 2.5V
20
s/DIV
3413 G12
V
OUT
= 1.25V
LOAD STEP = 0A TO 3A
Start-Up
INDUCTOR
CURRENT
1A/DIV
V
IN
= 2.5V
1ms/DIV
3413 G13
V
OUT
= 1.25V
LOAD = 0.4
OUTPUT
VOLTAGE
500mV/DIV
5
LTC3413
sn3413 3413fs
FU CTIO AL DIAGRA
U
U
W
+
+
+
+
+
9
16
10
PV
IN
3
I
TH
6
V
REF
1
8
SV
IN
SGND
4
V
FB
PGOOD
SV
IN
PV
IN
SLOPE
COMPENSATION
RECOVERY
SLOPE
COMPENSATION
PMOS CURRENT
COMPARATOR
NMOS CURRENT
COMPARATOR
OSCILLATOR
ERROR
AMPLIFIER
LOGIC
RUN
RUN/SS
R
T
11
14
15
SW
SW
SW
SW
13
7
5
PGND
3413 BD
12 PGND
2
1.1V
REF
2
0.9V
REF
2
U
U
U
PI FU CTIO S
SV
IN
(Pin 1): Signal Input Supply. Decouple this pin to
SGND with a capacitor. SV
IN
must be greater or equal to
PV
IN
, however, the difference between SV
IN
and PV
IN
must
be less than 0.5V.
PGOOD (Pin 2): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage is
not within
10% of regulation point.
I
TH
(Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.2V to
1.4V with 0.6V corresponding to the zero-sense voltage
(zero current).
V
FB
(Pin 4): Feedback Pin. Receives the feedback voltage
from the output.
R
T
(Pin 5): Oscillator Resistor Input. Connecting a resistor
to ground from this pin sets the switching frequency.
V
REF
(Pin 6): Reference Voltage Input. The positive input
of the internal error amplifier senses one-half of the
voltage at this pin through a resistor divider.
RUN/SS (Pin 7): Run Control and Soft-Start Input. Forcing
this pin below 0.5V shuts down the LTC3413. In shutdown
all functions are disabled drawing < 1
A of supply current.
A capacitor to ground from this pin sets the ramp time to
full output current.
SGND (Pin 8): Signal Ground. All small-signal compo-
nents and compensation components should connect to
this ground, which in turn connects to PGND at one point.
PV
IN
(Pins 9, 16): Power Input Supply. Decouple this pin
to PGND with a capacitor.
SW (Pins 10, 11, 14, 15): Switch Node Connection to
Inductor. This pin connects to the drains of the internal
main and synchronous power MOSFET switches.
PGND (Pins 12, 13): Power Ground. Connect this pin
closely to the () terminal of C
IN
and C
OUT
.
EXPOSED PAD (Pin 17): Should be connected to SGND.
6
LTC3413
sn3413 3413fs
OPERATIO
U
Main Control Loop
The LTC3413 is a monolithic, constant frequency, current
mode step-down DC/DC converter that is capable of sourc-
ing and sinking current at the output. During normal op-
eration, the internal top power switch (P-channel MOSFET)
is turned on at the beginning of each clock cycle. Current
in the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the I
TH
pin.
The error amplifier adjusts the voltage on the I
TH
pin by
comparing the feedback signal on the V
FB
pin with a refer-
ence voltage that is equal to one-half of the voltage on the
V
REF
pin. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the I
TH
voltage until the average
inductor current matches the new load current. When the
top power MOSFET shuts off, the synchronous power
switch (N-channel MOSFET) turns on until either the bot-
tom current limit is reached or the beginning of the next
clock cycle. The bottom current limit is set at 7A.
The operating frequency is set by an external resistor
connected between the R
T
pin and ground. The switching
frequency can range from 300kHz to 2MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by
10%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET's current limit is reached.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle until it reaches 100% duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the internal P-channel MOSFET and
the inductor.
Low Supply Operation
The LTC3413 is designed to operate down to an SV
IN
input
supply voltage of 2.25V. One important consideration at
low input supply voltages is that the R
DS(ON)
of the P-
channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3413 is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when slope
compensation is added. In the LTC3413, however, slope
compensation recovery is implemented to keep the maxi-
mum inductor peak current constant throughout the range
of duty cycles.
Short-Circuit Protection
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. To
prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases greater than 5A, the top
power MOSFET will be held off and switching cycles will be
skipped until the inductor current is reduced.
7
LTC3413
sn3413 3413fs
APPLICATIO S I FOR ATIO
W
U
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U
The basic LTC3413 application circuit is shown in Figure
1a. External component selection is determined by the
maximum load current and begins with the selection of the
inductor value and operating frequency followed by C
IN
and C
OUT
.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3413 is determined by
an external resistor that is connected between pin R
T
and
ground. The value of the resistor sets the ramp current that
is used to charge and discharge an internal timing capaci-
tor within the oscillator and can be calculated by using the
following equation.
R
f
k
OSC
=
( )
3 23 10
10
11
.
Although frequencies as high as 2MHz are possible, the
minimum on-time of the LTC3413 imposes a minimum
limit on the operating duty cycle. The minimum on-time is
typically 110ns. Therefore, the minimum duty cycle is
equal to 100 110ns f (Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current
I
L
increases with higher V
IN
or V
OUT
and
decreases with higher inductance.
=
I
V
f
V
V
L
OUT
L
OUT
IN
1
Having a lower ripple current reduces the core losses in
the inductor, the ESR losses in the output capacitors and
the output voltage ripple. Highest efficiency operation is
achieved at low frequency with small ripple current. This,
however, requires a large inductor.
A reasonable starting point for selecting the ripple current
is
I
L
= 0.4(I
MAX
). The largest ripple current occurs at the
highest V
IN
. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
L
V
f I
V
V
OUT
L MAX
OUT
IN MAX
=
(
)
(
)
1
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. Actual core loss is independent of core size for
a fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core losses and are used
often at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates "hard," which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy
materials are small and don't radiate much energy, but
generally cost more than powdered iron core inductors
with similar characteristics. The choice of which style
inductor to use mainly depends on the price versus size
requirements and any radiated field/EMI requirements.
8
LTC3413
sn3413 3413fs
APPLICATIO S I FOR ATIO
W
U
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The output ripple is highest at maximum input voltage
since
I
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and RMS
current handling requirements. Dry tantalum, special poly-
mer, aluminum electrolytic and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies.
Aluminum electrolytic capacitors have significantly higher
ESR, but can be used in cost-sensitive applications pro-
vided that consideration is given to ripple current ratings
and long term reliability. Ceramic capacitors have excel-
lent low ESR characteristics but can have a high voltage
coefficient and audible piezoelectric effects. The high Q of
ceramic capacitors with trace inductance can also lead to
significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
V
IN
. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at V
IN
large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
Table 1 shows some recommended surface mount
inductors for LTC3413 applications.
Table 1. Recommended Surface Mount Inductors
Value
DCR
Manufacturer
Part Number
(
H)
(m
)
Murata
LQH55DNR47M01
0.47
13.0
Vishay/Dale
IHLP2525CZPJR47M01
0.47
4.2
Pulse
P1166.681T
0.44
6.0
Cooper
SD20-R47
0.47
20.0
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the trapezoi-
dal wave current at the source of the top MOSFET. To
prevent large voltage transients from occurring, a low ESR
input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
I
I
V
V
V
V
RMS
OUT MAX
OUT
IN
IN
OUT
=
(
)
1
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate the
capacitor, or choose a capacitor rated at a higher tempera-
ture than required. Several capacitors may also be paral-
leled to meet size or height requirements in the design.
The selection of C
OUT
is determined by the effective series
resistance (ESR) that is required to minimize voltage
ripple and load step transients as well as the amount of
bulk capacitance that is necessary to ensure that the
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple,
V
OUT
, is determined by:
+
V
I ESR
fC
OUT
L
OUT
1
8
9
LTC3413
sn3413 3413fs
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Output Voltage Programming
In most applications, V
OUT
is connected directly to V
FB
.
The output voltage will be equal to one-half of the voltage
on the V
REF
pin for this case.
V
V
OUT
REF
=
2
If a different output voltage relationship is desired, an
external resistor divider from V
OUT
to V
FB
can be used. The
output voltage will then be set according to the following
equation:
pulled above 2V. The full current range becomes available
on I
TH
after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on I
TH
can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1a. The soft-start duration can be calculated by
using the following formula:
t
R
V
V
SS
SS
IN
=
C
ln
V
(Seconds)
SS
IN
.
1 8
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
IN
quiescent current and I
2
R losses.
The V
IN
quiescent current loss dominates the efficiency
loss at very low load currents whereas the I
2
R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the Electrical Characteris-
tics and the internal main switch and synchronous switch
gate charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
APPLICATIO S I FOR ATIO
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R2
V
OUT
R1
3413 F02
V
FB
SGND
LTC3413
Figure 2. Setting the Output Voltage
V
V
R
R
OUT
REF
=
+
2
1
2
1
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3413 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3413 in a low
quiescent current shutdown state (I
Q
< 1
A).
The LTC3413 contains an internal soft-start clamp that
gradually raises the clamp on I
TH
after the RUN/SS pin is
10
LTC3413
sn3413 3413fs
high to low to high again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current out
of V
IN
that is typically larger than the DC bias current. In
continuous mode, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V
IN
and thus their effects will be more
pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In con-
tinuous mode the average output current flowing through
inductor L is "chopped" between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3413 does not dissipate
much heat due to its high efficiency.
But, in applications where the LTC3413 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150
C,
both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3413 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(
JA
)
where P
D
is the power dissipated by the regulator and
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3413 in dropout at an
input voltage of 3.3V, a load current of 3A and an ambient
temperature of 70
C. From the Typical Performance graph
of switch resistance, the R
DS(ON)
of the P-channel switch
at 70
C is approximately 97m
. Therefore, power dissi-
pated by the part is:
P
D
= (I
LOAD
2
)(R
DS(ON)
) = (3A)
2
(97m
) = 0.87W
For the TSSOP package, the
JA
is 38
C/W. Thus the
junction temperature of the regulator is:
T
J
= 70
C + (0.87W)(38
C/W) = 103
C
which is below the maximum junction temperature of
APPLICATIO S I FOR ATIO
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LTC3413
sn3413 3413fs
APPLICATIO S I FOR ATIO
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125
C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to
I
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
.
I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components and output capaci-
tor shown in Figure 1a will provide adequate compensa-
tion for most applications.
Output Voltage Tracking of V
REF
For applications in which the V
REF
pin is connected to the
V
IN
pin, the output voltage will be equal to one-half of the
voltage on the V
IN
pin. Because the output voltage will
track the input voltage, any disturbance on V
IN
will appear
on V
OUT
. For example, a load step transient could cause
the input voltage to drop if there is insufficient bulk
capacitance at the V
IN
pin. The corresponding drop in the
output voltage during the load step transient is caused by
the V
OUT
tracking of V
IN
and should not be confused with
poor load regulation.
Design Example
As a design example, consider using the LTC3413 in an
application with the following specifications: V
IN
= 2.5V,
V
OUT
= 1.25V, I
OUT(MAX)
=
3A, f = 1MHz.
First, calculate the timing resistor:
R
k
k
OSC
=
=
3 23 10
1 10
10
313
11
6
.
Use a standard value of 309k. Next, calculate the inductor
value for about 40% ripple current:
L
V
MHz
A
V
V
H
=
=
1 25
1
1 2
1
1 25
2 5
0 47
.
.
.
.
.
Using a 0.47
H inductor results in a maximum ripple
current of:
=
=
I
V
MHz
H
V
V
A
L
1 25
1
0 47
1
1 25
2 5
1 33
.
.
.
.
.
C
OUT
will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100
F ceramic capacitors will be used. C
IN
should be sized
for a maximum current rating of:
I
A
V
V
V
V
A
RMS
RMS
=
=
3
1 25
2 5
2 5
1 25
1 1 5
.
.
.
.
.
Decoupling the PV
IN
pins with two 100
F capacitors is
12
LTC3413
sn3413 3413fs
Figure 3. One-Half V
REF
,
3A DDR Memory Termination Supply at 1MHz
(Efficiency Curve is Shown in Figure 1b)
R
PG
100k
R
ITH
5.11k
R
OSC
309k
*VISHAY DALE IHLP-2525CZ-01 0.47
H
**TDK C4532X5R0J107M
R
SS
4.7M
C
SS
330pF X7R
C
ITH
2200pF
X7R
C
C
100pF
PGOOD
SV
IN
PGOOD
I
TH
V
FB
R
T
V
REF
RUN/SS
SGND
PV
IN
SW
SWV
FB
PGND
PGND
SW
SW
PV
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC3413
L1*
0.47
H
C
IN1
**
100
F
C
IN2
**
100
F
C
OUT
**
100
F
2
GND
3413 F03
V
OUT
1.25V
3A
V
IN
2.5V
adequate for most applications. Connect the V
REF
pin
directly to SV
IN
. Connecting the V
FB
pin directly to V
OUT
will set the output voltage equal to one-half of the voltage
on the V
REF
pin. The complete circuit for this design
example is illustrated in Figure 3.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3413. Check the following in your layout.
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3413.
2. Connect the (+) terminal of the input capacitor(s), C
IN
,
as close as possible to the PV
IN
pin. This capacitor
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (PV
IN
, SV
IN
, V
OUT
, PGND, SGND or any other DC rail in
your system).
5. Connect the V
FB
pin directly to the V
OUT
pin.
APPLICATIO S I FOR ATIO
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13
LTC3413
sn3413 3413fs
Figure 4. LTC3413 Layout Diagram
APPLICATIO S I FOR ATIO
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(4c) PCB Photo
(4a) Top Layer
(4b) Bottom Layer
14
LTC3413
sn3413 3413fs
TYPICAL APPLICATIO
U
1.25V,
3A DDR Memory Termination Supply at 1MHz
R
PG
100k
R
ITH
5.11k
R
OSC
309k
*VISHAY DALE IHLP-2525CZ-01 0.47
H
**TDK C4532X5R0J107M
R
SS
4.7M
C
SS
330pF X7R
C
ITH
2200pF
X7R
C
C
100pF
PGOOD
2.5V
SV
IN
PGOOD
I
TH
V
FB
R
T
V
REF
RUN/SS
SGND
PV
IN
SW
SWV
FB
PGND
PGND
SW
SW
PV
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC3413
L1*
0.47
H
C
IN1
**
100
F
C
IN2
**
100
F
C
OUT
**
100
F
2
GND
3413 TA01
V
OUT
1.25V
3A
V
IN
3.3V
LOAD CURRENT (A)
0.01
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0
0.1
1
10
3413 TA01b
Efficiency vs Load Current,
V
IN
= 3.3V, V
OUT
= 1.25V, f = 1MHz
15
LTC3413
sn3413 3413fs
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663,
Exposed Pad Variation BA)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
FE16 (BA) TSSOP 0203
0.09 0.20
(.0036 .0079)
0
8
0.45 0.75
(.018 .030)
4.30 4.50*
(.169 .177)
6.40
BSC
1
3
4
5
6 7 8
10
9
4.90 5.10*
(.193 .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 0.15
(.002 .006)
0.65
(.0256)
BSC
2.74
(.108)
2.74
(.108)
0.195 0.30
(.0077 .0118)
2
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
RECOMMENDED SOLDER PAD LAYOUT
3. DRAWING NOT TO SCALE
0.45
0.05
0.65 BSC
4.50
0.10
6.60
0.10
1.05
0.10
2.74
(.108)
2.74
(.108)
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
16
LTC3413
sn3413 3413fs
LT/TP 0703 1K PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2002
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear.com
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3.3V to 0.75V,
3A HSTL Application
R
PG
100k
R
ITH
10k
R
OSC
309k
*VISHAY DALE IHLP-2525CZ-01 0.47
H
**TDK C4532X5R0J107M
TAIYO YUDEN JMK325BJ226MM
SANYO POSCAP 4TPD470M
R
SS
4.7M
C
SS
330pF X7R
C
ITH
2200pF
X7R
C
C
100pF
PGOOD
1.5V
SV
IN
PGOOD
I
TH
V
FB
R
T
V
REF
RUN/SS
SGND
PV
IN
SW
SWV
FB
PGND
PGND
SW
SW
PV
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LTC3413
L1*
0.47
H
C
IN1
**
100
F
C
IN2
**
100
F
C
OUT1
22
F
C
OUT2
470
F
GND
3413 TA02
V
OUT
0.75V
3A
V
IN
3.3V
+
TYPICAL APPLICATIO
U
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