LTC3421

3421f

Handheld Computers

Cordless Phones

GPS Receivers

Battery Backup Supplies

, LTC and LT are registered trademarks of Linear Technology Corporation.

Synchronous Rectification: Up to 96% Efficiency

True Output Disconnect

Inrush Current Limiting

Very Low Quiescent Current: 12

Up to 1.5A Continuous Output Current

Fixed Frequency Operation Up to 3MHz

0.5V to 4.5V Input Range

2.4V to 5.25V Adjustable Output Voltage

Guaranteed 1V Start-Up

Programmable Current Limit

Programmable Soft-Start

Synchronizable Oscillator

Manual or Automatic Burst Mode

Operation

Low-Battery Comparator

< 1

A Shutdown Current

1.22V Reference Output Voltage

Small (4mm

4mm) Thermally Enhanced QFN

Package

3A, 3MHz Micropower

Synchronous Boost Converter

with Output Disconnect

Burst Mode is a registered trademark of Linear Technology Corporation.

The LTC

3421 is a high efficiency, current mode, fixed

frequency, step-up DC/DC converter with true output dis-
connect and inrush current limiting. The device includes a
0.10

N-channel MOSFET switch and a 0.14

P-channel

synchronous rectifier. This product has the ability to sim-
ply program the output voltage, switching frequency, cur-
rent limit, soft-start, Burst Mode threshold and loop
compensation with external passive components.

Quiescent current is only 12

A during Burst Mode opera-

tion, maximizing battery life in portable applications. The
oscillator frequency can be programmed up to 3MHz and
can be synchronized to an external clock applied to the
SYNC pin. An open-drain uncommitted low-battery com-
parator is included. The part maintains operation in
applications with a secondary cell powering the output
voltage during shutdown.

Other features include: 1

A shutdown, antiringing control,

thermal limit and reference output.

The LTC3421 is available in a small 4mm

4mm QFN

package.

SHDN

ENB

REF

LBI

LBO

SYNC

LIM

OUTS

OUT

BURST

SW SW

4.7

GND

LTC3421

0.1

470pF

C5*
22

C1*
4.7

1.8V TO 3V

2
CELLS

28k

20k

100k

340k

OUT

3.3V
1.2A

200k

3421 TA01

45.3k

*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM

PGND PGND PGND

C5: TAIYO YUDEN JMK325BJ226MM
L1: TDK RLF7030T-4R7M3R4

2-Cell to 3.3V Efficiency

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1

100

1000

3421 G02

Burst Mode OPERATION

= 3V

OUT

= 3.3V

OSC

= 1MHz

= 2.4V

= 2V

DESCRIPTIO

FEATURES

APPLICATIO S

TYPICAL APPLICATIO

LTC3421

3421f

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Minimum V

Start-Up Voltage

LOAD

< 1mA

0.88

Minimum V

Operating Voltage

(Note 4)

0.5

Output Voltage Adjust Range

2.25

5.25

2.40

5.25

Feedback Voltage

1.196

1.220

1.244

Feedback Input Current

= 1.22V

Quiescent Current--Burst Mode Operation

= 0V, ENB = 0V (Note 3)

= 0V, ENB = 2V (Note 3)

Quiescent Current--Shutdown

SHDN = 0V, ENB = 0V

0.1

SHDN = 0V, ENB > 1.4V

0.2

Quiescent Current--Active

(Note 3)

0.6

1.1

NMOS Switch Leakage

0.1

PMOS Switch Leakage

0.1

NMOS Switch On Resistance

0.1

PMOS Switch On Resistance

0.14

NMOS Current Limit

LIM

Resistor = 105k

1.5

LIM

Resistor = 36.5k

4.2

Max Duty Cycle

Min Duty Cycle

, V

OUT

, V

OUTS

Voltage ............................ 0.3V to 6V

BURST, SHDN, SS, ENB, SW,
LBO, LBI, SYNC Voltages .......................... 0.3V to 6V
Operating Temperature Range
(Notes 2, 5) ............................................. 40

C to 85

Storage Temperature Range ................. 65

C to 125

Lead Temperature (Soldering, 10 sec).................. 300

ORDER PART NUMBER

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LTC3421EUF

ABSOLUTE AXI U

RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

JMAX

= 125

= 40

C/W 1 LAYER BOARD,

= 35

C/W 4 LAYER BOARD,

= 2.6

C/W

EXPOSED PAD IS GND (PIN 25) MUST BE SOLDERED TO PCB

ELECTRICAL CHARACTERISTICS

The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 1.2V, V

OUT

= 3.3V, R

= 28k, unless otherwise noted.

24 23 22 21 20 19

TOP VIEW

UF PACKAGE

24-LEAD (4mm

4mm) PLASTIC QFN

10 11 12

SHDN

REF

ENB

OUTS

OUT

PGND

LBI

LBO

OUT

SYNC

LIM

BURST

GND

PGND

UF PART MARKING

3421

LTC3421

3421f

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Frequency Accuracy

0.85

1.15

MHz

SYNC Input High

2.2

SYNC Input Low

0.8

SYNC Input Current

0.01

ENB Input High

1.2

ENB Input Low

0.4

ENB Input Current

SHDN Input High

OUT

= 0V (Initial Start-Up)

1.00

OUT

> 2.4V

0.65

SHDN Input Low

0.25

SHDN Input Current

0.01

REF Output Voltage

1.183

1.22

1.257

REF Output Current Range

100

Error Amp Transconductance

LBI Threshold

Falling Edge

0.58

0.6

0.62

LBI Input Current

0.01

LBO Low Voltage

= 0V, I

SINK

= 1mA

12.0

= 0V, I

SINK

= 20mA

0.25

0.5

LBO Leakage

PGOOD

= 5.5V

0.01

SS Current Source

= 1V

1.2

2.4

BURST Threshold Voltage

Falling Edge

0.87

0.97

1.07

ELECTRICAL CHARACTERISTICS

The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 1.2V, V

OUT

= 3.3V, R

= 28k, unless otherwise noted.

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The LTC3421E is guaranteed to meet performance specifications
from 0

C to 70

C. Specifications over the 40

C to 85

C operating

temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: Current is measured into the V

OUTS

pin since the supply current is

bootstrapped to the output. The current will reflect to the input supply by
(V

OUT

) · Efficiency. The outputs are not switching.

Note 4: Once V

OUT

is greater than 2.4V, the IC is not dependent on the V

supply.

Note 5: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125

C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction
temperature may impair device reliability.

LTC3421

3421f

TYPICAL PERFOR A CE CHARACTERISTICS

Single Cell to 3.3V Efficiency

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1

100

1000

3421 G01

Burst Mode OPERATION

= 1.5V

OUT

= 3.3V

OSC

= 1MHz

= 1V

= 1.2V

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1

100

1000

3421 G02

Burst Mode OPERATION

= 3V

OUT

= 3.3V

OSC

= 1MHz

= 2.4V

= 2V

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1

100

1000

3421 G03

Burst Mode

OPERATION

OUT

= 5V

OSC

= 1MHz

= 4.2V

= 3.6V

= 2.7V

2-Cell to 3.3V Efficiency

Li-Ion to 5V Efficiency

Burst Mode Operation

Load Transient Response

Inrush Current Control

Efficiency vs Frequency

Efficiency vs V

Start-Up Voltage vs Output Current

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

1000

3421 G07

100

= 2.4V

OUT

= 3.3V

f = 300kHz

f = 3MHz

f = 1MHz

INPUT VOLTAGE (V)

EFFICIENCY (%)

100

3.5

3421 G08

1.5

2.5

4.5

> V

OUT

PMOS LDO MODE

OUT

= 3.3V

OUT

= 200mA

OUTPUT CURRENT (mA)

START VOLTAGE (V)

1.00

1.05

1.10

200

3421 G09

0.95

0.90

0.80

100

150

0.85

1.20

1.15

OUT

50mV/DIV

AC COUPLED

INDUCTOR

CURRENT

0.5A/DIV

2.5

s/DIV

3421 G04

OUT

100mV/DIV

AC COUPLED

600mA

= 2.4V

2.5ms/DIV

3421 G05

OUT

= 3.3V

OUT

= 44

50mA

OUT

1V/DIV

INDUCTOR

CURRENT

0.5A/DIV

= 0V TO 2.4V

500

s/DIV

3421 G06

OUT

= 44

= 25

C, unless otherwise specified)

LTC3421

3421f

Burst Mode Threshold vs R

BURST

FB Voltage

Frequency Accuracy

Burst Mode Quiescent Current

Current Limit Accuracy

DS(ON)

BURST

)

OUTPUT CURRENT (mA)

100

INTO BURST

OUT OF BURST

120

180

3421 G10

120

140

160

TEMPERATURE (

1.20

VOLTAGE (V)

1.21

1.22

1.23

1.24

30 15

3421 G11

TEMPERATURE (

0.95

FREQUENCY (MHz)

0.97

0.99

1.01

1.03

30 15

3421 G12

TEMPERATURE (

CURRENT (

30 15

3421 G13

FB (Pin 1): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 2.4V to
5.25V. The feedback reference voltage is typically 1.220V.

SHDN (Pin 2): Shutdown Pin. Less than 0.25V on this pin
shuts down the IC. The IC is enabled when the SHDN
voltage is greater than 1V. Once V

OUT

is above 2.2V,

hysteresis is applied to the pin (500nA out of the pin)
allowing it to operate at a logic high while the battery can
drop to 0.5V.

REF

(Pin 3): Buffered 1.22V Reference Output. This pin

can source up to 100

A and sink up to 8

A. This pin must

be decoupled with a 0.1

F capacitor for stability.

PI FU CTIO S

ENB (Pin 4): Reference Output (V

REF

) and Low-Battery

Comparator Enable. When ENB = Low, the V

REF

output and

low-battery comparator are disabled, which lowers the
quiescent current by 5

A. When ENB = High, the V

REF

output and the low-battery comparator are enabled. Dur-
ing shutdown, if the ENB = High and the output voltage is
pulled up to greater than 2.5V from a secondary source
such as a coin cell through a Schottky diode, the V

REF

output and low-battery comparator becomes powered
from the output voltage and enabled.

TEMPERATURE (

1.20

CURRENT (A)

1.25

1.35

1.40

1.45

1.70

1.55

3421 G14

1.30

1.60

1.65

1.50

LIM

= 105k

TEMPERATURE (

RESISTANCE (

)

0.02

0.06

0.08

0.10

0.20

0.14

3421 G15

0.04

0.16

0.18

0.12

PMOS

NMOS

TYPICAL PERFOR A CE CHARACTERISTICS

= 25

C, unless otherwise specified)

LTC3421

3421f

PI FU CTIO S

(Pin 5): Connect a resistor to ground to program the

oscillator frequency according to the formula:

OSC

28 100

where f

OSC

is in kHz and R

is in k

SS (Pin 6): Soft-Start Pin. Connect a capacitor from this
pin to ground to set the soft-start time according to the
formula:

t(ms) = C

(

F) · 320

The nominal soft-start charging current is 2.5

A. The

active range of SS is from 0.8V to 1.6V.

SYNC (Pin 7): Oscillator Synchronization Pin. A clock
pulse width of 100ns to 2

s is required to synchronize the

internal oscillator. If not used SYNC should be grounded.

LIM

(Pin 8): Current Limit Adjust Pin. Connect a resistor

from this pin to ground to set the peak current limit thresh-
old for the N-channel MOSFET according to the formula
(note that this is the peak current in the inductor):

LIM

150

where I is in amps and R is in k

BURST (Pin 9): Burst Mode

Threshold Adjust Pin. A

resistor/capacitor combination from this pin to ground
programs the average load current at which automatic
Burst Mode operation is entered, according to the formula:

BURST

where R

BURST

is in k

and I

BURST

is in amps.

BURST

OUT

10 000

where C

BURST(MIN)

and C

OUT

are in

For manual control of Burst Mode operation, ground the
BURST pin to force Burst Mode operation or connect it to
V

OUT

to force fixed frequency PWM mode. Note that the

BURST pin must not be pulled higher than V

OUT

GND (Pin 10): Signal Ground Pin. Connect to ground plane
near the R

resistor, error amp compensation compo-

nents and feedback divider.

PGND (Pins 11 to 13): Source Terminal of Power Internal
N-Channel MOSFET.

SW (Pins 14 to 16): Switch Pin for Inductor Connection.
For applications where V

OUT

> 4.3V, a Schottky diode from

SW to V

OUT

or to a snubber circuit is required to maintain

absolute maximum rating for SW. (see Application Cir-
cuits for 5V).

OUT

(Pins 17, 19 and 20): The output of the synchronous

rectifier and bootstrapped power source for the IC. A
ceramic bypass capacitor is required to be very close to
the V

OUT

and PGND pins of the IC.

OUTS

(Pin 18): V

OUT

Sense Pin. Connect V

OUTS

directly to

an output filter capacitor. The top of the feedback divider
network should also be tied to this point.

(Pin 21): Input Supply Pin. Connect this pin to the

input supply and decouple with at least a 4.7

F ceramic

capacitor.

LBO (Pin 22): Open-Drain Output. This pin pulls low when
the LBI input is below 0.6V. The open-drain output can
sink up to 20mA. During Burst Mode operation LBO is only
active during the time the IC wakes up to service the
output.

LBI (Pin 23): Low-Battery Comparator Input. Typical
threshold voltage is 0.6V with 30mV hysteresis. This
function is enabled when the ENB pin is high. The low-
battery comparator will operate off V

or V

OUT

, whichever

is greater.

(Pin 24): Error Amp Output. A frequency compensation

network is connected from this pin to ground to compen-
sate the loop. See the section Compensating the Feedback
Loop for guidelines.

Exposed Pad (Pin 25): Ground. This pin must be soldered
to the PCB and is typically connected through the power
GND plane.

LTC3421

3421f

OPERATIO

LOW VOLTAGE START-UP

The LTC3421 includes an independent start-up oscillator
designed to start-up at input voltages of 0.85V typical. The
frequency and peak current limit during start-up are inter-
nally controlled. The device can start-up under some load
(see graph of Start-Up Current vs Input Voltage). Soft-
start and inrush current limiting are provided during start-
up as well as normal mode. The same soft-start capacitor
is used for each operating mode.

When either V

or V

OUT

exceeds 2.25V, the IC enters

normal operating mode. Once the output voltage exceeds
the input by 0.3V, the IC powers itself from V

OUT

instead

of V

. At this point the internal circuitry has no depen-

dency on the V

input voltage, eliminating the require-

ment for a large input capacitor. The input voltage can drop
as low as 0.5V without affecting circuit operation. The
limiting factor for the application becomes the availability
of the power source to supply sufficient energy to the
output at the low voltages and the maximum duty cycle,
which is clamped at 91% typical.

LOW NOISE FIXED FREQUENCY OPERATION

Shutdown

The part is shut down by pulling SHDN below 0.3V, and
activated by pulling the pin initially above 1V and maintain-
ing a high state down to 0.5V. Note that the SHDN pin can
be driven above V

or V

OUT

as long as it is limited to less

than the absolute maximum rating.

Soft-Start

The soft-start time is programmed with an external capaci-
tor to ground on the SS pin. An internal current source
charges it with a nominal 2.5

A. The voltage on the SS pin

(in conjunction with the external resistor on the I

LIM

pin)

is used to control the peak current limit until the voltage on
the capacitor exceeds 1.6V, at which point the external
resistor sets the peak current. In the event of a com-
manded shutdown or a thermal shutdown, the capacitor is
discharged automatically. Note that Burst Mode operation
is inhibited during the soft-start time.

t(ms) = C

(

F) · 320

Oscillator

The frequency of operation is set through a resistor from
the R

pin to ground. An internally trimmed timing capaci-

tor resides inside the IC. The oscillator can be synchro-
nized with an external clock applied to the SYNC pin. When
synchronizing the oscillator, the free running frequency
must be set to an approximately 30% lower frequency
than the desired synchronized frequency.

Current Sensing

Lossless current sensing converts the peak current signal
to a voltage to sum in with the internal slope compensa-
tion. This summed signal is compared to the error ampli-
fier output to provide a peak current control command for
the PWM. The slope compensation in the IC is adaptive to
the input voltage and output voltage. Therefore, the con-
verter provides the proper amount of slope compensation
to ensure stability, but not an excess to cause a loss of
phase margin in the converter.

Error Amplifier

The error amplifier is a transconductance amplifier, with
its positive input internally connected to the 1.22V refer-
ence and its negative input connected to FB. A simple
compensation network is placed from COMP to ground.
Internal clamps limit the minimum and maximum error
amplifier output voltage for improved large-signal tran-
sient response. During sleep (in Burst Mode operation),
the compensation pin is high impedance; however, clamps
limit the voltage on the external compensation network,
preventing the compensation capacitor from discharging
to zero during the sleep time.

Current Limit

The programmable current limit circuit sets the maximum
peak current. This clamp level is programmed with a
resistor from I

LIM

to ground. In Burst Mode operation, the

current limit is automatically set to a nominal value of 0.6A
peak for optimal efficiency.

LIM

150

where I is in amps and R is in k

LTC3421

3421f

OPERATIO

Zero Current Amplifier

The zero current amplifier monitors the inductor current to
the output and shuts off the synchronous rectifier once the
current is below 50mA typical, preventing negative induc-
tor current.

Antiringing Control

The antiringing control places a resistor across the
inductor to damp the ringing on the SW pin in discontinu-
ous conduction mode. The LC

ringing (L = inductor,

= capacitance on SW pin) is low energy, but can

cause EMI radiation.

REF

The internal 1.22V reference is buffered and brought out
to REFOUT. It is active when the ENB pin is pulled high
(above 1.4V). For stability, a minimum of a 0.1

F capacitor

must be placed on the pin. The output can source up to
100

A and sink up to 8

A. For the lowest possible quies-

cent current in Burst Mode operation, the reference output
should be disabled by grounding the ENB pin.

Burst Mode OPERATION

Burst Mode operation can be automatic or user controlled.
In automatic operation, the IC will automatically enter
Burst Mode operation at light load and return to fixed
frequency PWM mode for heavier loads. The user can
program the average load current at which the mode
transition occurs using a single resistor.

The oscillator is shut down in this mode, since the on time
is determined by the time it takes the inductor current to
reach a fixed peak current and the off time is determined
by the time it takes for the inductor current to return to
zero.

In Burst Mode operation, the IC delivers energy to the
output until it is regulated and then goes into a sleep mode
where the outputs are off and the IC is consuming only
12

A of quiescent current. In this mode, the output ripple

has a variable frequency component with load current and
will be typically 2% peak-peak. This maximizes efficiency
at very light loads by minimizing switching and quiescent
losses. Burst Mode ripple can be reduced slightly by

increasing the output capacitance. Another method of
reducing Burst Mode ripple is to place a small feed-
forward capacitor across the upper resistor in the V

OUT

feedback divider network.

During Burst Mode operation, the V

pin is disconnected

from the error amplifier in an effort to hold the voltage on
the external compensation network where it was before
entering Burst Mode operation. To minimize the effects of
leakage current and stray resistance, voltage clamps limit
the min and max voltage on V

during Burst Mode opera-

tion. This minimizes the transient experienced when a
heavy load is suddenly applied to the converter after being
in Burst Mode operation for an extended period of time.

For automatic operation, an RC network should be con-
nected from BURST to ground. The value of the resistor
will control the average load current (I

BURST

) at which

Burst Mode operation will be entered and exited (there is
hysteresis to prevent oscillation between modes). The
equation given for the capacitor on BURST is for the
minimum value to prevent ripple on BURST from causing
the part to oscillate in and out of Burst Mode operation at
the current where the mode transition occurs.

BURST

where R

BURST

is in k

and I

BURST

is in amps.

BURST

OUT

10 000

where C

BURST(MIN)

and C

OUT

are in

In the event that a sudden load transient causes FB to
deviate by more than 4% from the regulation value, an
internal pull-up is applied to BURST, forcing the part
quickly out of Burst Mode operation. For optimum tran-
sient response when going between Burst Mode operation
and PWM mode, the mode should be controlled manually
by the host. This way PWM mode can be commanded
before the load step occurs, minimizing output voltage
droop. For manual control of Burst Mode operation, the
RC network can be eliminated. To force fixed frequency
PWM mode, BURST should be connected to V

OUT

. To

force Burst Mode operation, BURST should be grounded.

LTC3421

3421f

OPERATIO

The circuit connected to BURST should be able to sink or
source up to 2mA. Note that Burst Mode operaton is
inhibited during start-up and soft-start.

Note that if V

is above V

OUT

0.3V, the part will exit Burst

Mode operation and the synchronous rectifier will be
disabled.

Note that if the load applied during forced Burst Mode
operation exceeds the current that can be supplied, the
output voltage will start to droop and the part will auto-
matically come out of Burst Mode operation and enter fixed
frequency mode, raising V

OUT

. The maximum current that

can be supplied in Burst Mode operation is given by:

Simplified Diagram of Automatic Burst Mode Control Circuit

TO
MODULATOR

CLAMP

0.5V TO 1V

SLEEP

3421 TA03

ERROR AMP/
SLEEP COMP

COMP

REF

9 BURST

0.9V/

1.1V

SSDONE

MODE
1 = Burst Mode
OPERATION
0 = PWM MODE

SSDONE

REF

1mA

OUT

/3000

in amps

O MAX

OUT

(

)

(

)

0 55

OUTPUT DISCONNECT AND INRUSH LIMITING

The LTC3421 is designed to allow true output disconnect
by eliminating body diode conduction of the internal
P-channel MOSFET rectifier. This allows V

OUT

to go to zero

volts during shutdown without drawing any current from
the input source. It also allows for inrush current limiting
at turn-on, minimizing surge currents seen by the input
supply. Note that to obtain the advantages of output

LTC3421

3421f

OPERATIO

disconnect, there must not be any external Schottky
diodes connected between the SW pins and V

OUT

Note: Board layout is extremely critical to minimize volt-
age overshoot on the SW pins due to stray inductance.
Keep the output filter capacitors as close as possible to the

OUT

pins and use very low ESR/ESL ceramic capacitors,

tied to a good ground plane. In V

OUT

> 4.3V applications,

a Schottky diode is required from the switch nodes to V

OUT

to limit the peak switch voltage to less than 6V unless
some form of external snubbing is employed. (See 5V
Applications section.)

APPLICATIO S I FOR ATIO

COMPONENT SELECTION

Inductor Selection

The high frequency operation of the LTC3421 allows the
use of small surface mount inductors. The minimum
inductance value is proportional to the operating fre-
quency and is limited by the following constraints:

and L

f Ripple V

IN MIN

OUT MAX

IN MIN

OUT MAX

(

)

(

)

(

)

(

)

(

)

LBI

LBO

OUT

SYNC I

LIM

BURST GND PGND PGND

GND

3421 F01

MULTIPLE VIAS
TO GROUND
PLANE

SHDN

REF

ENB

OUTS

OUT

PGND

Figure 1. Recommended Component Placement. Traces Carrying
High Current are Direct (PGND, SW, V

OUT

). Trace Area at FB and

are Kept Low. Lead Length to Battery Should be Kept Short.

and V

OUT

Ceramic Capacitors Should be as Close to the IC

Pins as Possible

where

f = Operating Frequency in MHz

Ripple = Allowable Inductor Current Ripple (Amps
Peak-Peak)

IN(MIN)

= Minimum Input Voltage

OUT(MAX)

= Maximum Output Voltage

The inductor current ripple is typically set to 20% to 40%
of the maximum inductor current.

For high efficiency, choose an inductor with high fre-
quency core material, such as ferrite, to reduce core loses.
The inductor should have low ESR (equivalent series
resistance) to reduce the I

R losses and must be able to

handle the peak inductor current without saturating. Molded
chokes or chip inductors usually do not have enough core
to support peak inductor currents in the 1A to 4A region.
To minimize radiated noise, use a toroidal or shielded
inductor. See Table 1 for suggested inductor suppliers and
Table 2 for a list of capacitor suppliers.

Table 1. Inductor Vendor Information

SUPPLIER PHONE

FAX

WEB SITE

Coilcraft

(847) 639-6400

(847) 639-1469 www.coilcraft.com

Coiltronics (561) 241-7876

(516) 241-9339

Murata

USA:

www.murata.com

(814) 237-1431

(814) 238-0490

(800) 831-9172

Sumida

USA:

www.sumida.com

(847) 956-0666

(847) 956-0702

Japan:

81-3-3607-5111 81-3-3607-5144

TDK

(847) 803-6100

(847) 803-6296 www.component.tdk.com

TOKO

(847) 297-0070

(847) 669-7864 www.toko.com

LTC3421

3421f

APPLICATIO S I FOR ATIO

Output Capacitor Selection

The output voltage ripple has two components to it. The
bulk value of the capacitor is set to reduce the ripple due
to charge into the capacitor each cycle. The maximum
ripple due to charge is given by:

RBULK

OUT

where I

= peak inductor current.

The ESR (equivalent series resistance) is usually the most
dominant factor for ripple in most power converters. The
ripple due to capacitor ESR is simply given by:

RCESR

= I

· C

ESR

where C

ESR

= capacitor series resistance.

Low ESR capacitors should be used to minimize output
voltage ripple. For surface mount applications, AVX TPS
series tantalum capacitors, Sanyo POSCAP or Taiyo Yuden
ceramic capacitors are recommended. For through-hole
applications, Sanyo OS-CON capacitors offer low ESR in a
small package size.

In some layouts it may be necessary to place a 1

F low ESR

ceramic capacitor as close to the V

OUT

and GND pins as

possible.

Input Capacitor Selection

The input filter capacitor reduces peak currents drawn
from the input source and reduces input switching noise.
Since the IC can operate at voltages below 0.5V once the
output is regulated, the demand on the input capacitor is
much less. In most applications 1

F per amp of peak input

current is recommended. Taiyo Yuden offers very low ESR
ceramic capacitors, for example the 1

F in a 0603 case

(JMK107BJ105MA).

Table 2. Capacitor Vendor Information

SUPPLIER

PHONE

FAX

WEB SITE

AVX

(803) 448-9411 (803) 448-1943 www.avxcorp.com

Sanyo

(619) 661-6322 (619) 661-1055 www.sanyovideo.com

TDK

(847) 803-6100 (847) 803-6296 www.component.tdk.com

Murata

USA:

www.murata.com

(814) 237-1431 (814) 238-0490
(800) 831-9172

Taiyo Yuden (408) 573-4150 (408) 573-4159 www.t-yuden.com

Operating Frequency Selection

There are several considerations in selecting the operating
frequency of the converter. The first is, which are the sen-
sitive frequency bands that cannot tolerate any spectral
noise? The second consideration is the physical size of the
converter. As the operating frequency goes up, the induc-
tor and filter capacitors go down in value and size. The trade
off is in efficiency since the switching losses due to gate
charge are going up proportional with frequency.

Another operating frequency consideration is whether the
application can allow "pulse skipping." In this mode, the
minimum on time of the converter cannot support the duty
cycle, so the converter ripple will go up and there will be
a low frequency component of the output ripple. In many
applications where physical size is the main criterion,
running the converter in this mode is acceptable. In appli-
cations where it is preferred not to enter this mode, the
maximum operating frequency is given by:

MAX NOSKIP

OUT

ON MIN

(

)

where t

ON(MIN)

= minimum on time = 120ns.

Thermal Considerations

To deliver the power that the LTC3421 is capable of, it is
imperative that a good thermal path be provided to
dissipate the heat generated within the package. This can
be accomplished by taking advantage of the large thermal
pad on the underside of the IC. It is recommended that mul-
tiple vias in the printed circuit board be used to conduct
heat away from the IC and into a copper plane with as much
area as possible. In the event that the junction tempera-
ture gets too high, the peak current limit will automatically
be decreased. If the junction temperature continues to rise,
the part will go into thermal shutdown, and all switching
will stop until the temperature drops.

> V

OUT

Operation

The LTC3421 will maintain voltage regulation when the
input voltage is above the output voltage. This is achieved
by terminating the switching on the synchronous PMOS
and applying V

statically on the gate. This will ensure the

LTC3421

3421f

APPLICATIO S I FOR ATIO

volts · seconds of the inductor will reverse during the time
current is flowing to the output. Since this mode will
dissipate more power in the IC, the maximum output
current is limited in order to maintain an acceptable
junction temperature.

OUT MAX

OUT

(

)

(

)

(

)

125

1 5

where T

= ambient temperature.

For example at V

= 4.5V and V

OUT

= 3.3V, the maximum

output current is 370mA.

Short Circuit

The LTC3421 output disconnect feature allows output short
circuit while maintaining a maximum set current limit. The
IC has incorporated internal features such as current limit
and thermal shutdown for protection from an excessive
overload or short circuit. In applications that require a pro-
longed short circuit, it is recommended to limit the power
dissipation in the IC to maintain an acceptable junction
temperature. The circuit in Figure 2 will limit the maximum
current during a prolonged short by reducing the current
limit value in a short circuit by disconnecting R2 with the
N-channel MOSFET switch. R3 and C1 provide a soft-start
function after a short circuit. Resistor R1 lowers the cur-
rent limit value as V

rises, maintaining a relatively con-

stant power. The current limit equation for the circuit in
Figure 2 is given by:

LIMIT

LIM

0 6

250

where I

LIMIT

is in Amps; R

LIM

and R1 are in k

Closing the Feedback Loop

The LTC3421 uses current mode control with internal
adaptive slope compensation. Current mode control elimi-
nates the 2nd order filter due to the inductor and output
capacitor exhibited in voltage mode controllers, and sim-
plifies it to a single pole filter response. The product of the
modulator control to output DC gain and the error amp
open-loop gain gives the DC gain of the system:

REF

OUT

CONTROL

OUT

CONTROL_OUTPUT

2000

The output filter pole is given by:

FILTER POLE

OUT

where C

OUT

is the output filter capacitor.

The output filter zero is given by:

FILTER ZERO

ESR

OUT

where R

ESR

is the capacitor equivalent series resistance.

A troublesome feature of the boost regulator topology is
the right-half plane zero (RHP) and is given by:

RHPZ

OUT

2 ·

At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.

The typical error amp compensation is shown in Figure 3.
The equations for the loop dynamics are as follows:

POLE

ZERO

POLE

20 6

which is extremely close to DC

Figure 2. Current Limit Foldback Circuit for
Extended Short Conditions

R2
50k

C1
0.1

3421 F02

R1
1M

10k

LIM

100k

VN2222

LIM

TO V

OUT

LTC3421

3421f

5V Applications

When the output voltage is programmed above 4.3V it is
necessary to add a Schottky diode either from SW to
V

OUT

, or to a snubber network in order to maintain an

acceptable peak voltage on SW. The Schottky to the

output will provide a peak efficiency improvement but will
negate the output disconnect feature. If output disconnect
is required, the Schottky to an active snubber network is
suggested as shown in Figure 4.

Figure 4. Lithium-Ion to 5V at 1A Application with an Active Snubber Circuit

TYPICAL APPLICATIO

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1

100

1000

3421 G03

Burst Mode

OPERATION

OUT

= 5V

OSC

= 1MHz

= 4.2V

= 3.6V

= 2.7V

Li-Ion to 5V Efficiency

SHDN

ENB

REF

LBI

LBO

SYNC

LIM

OUTS

OUT

BURST

SW SW

GND

LTC3421

0.1

470pF

C5*
22

C6*
1

C1*
10

2.7V TO

4.2V

Li-Ion

R2
28k

R3
10k

100k

R5
1.13M

D1*

OUT

5V
1A

R6
365k

3421 F04

R1
60k

*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM
C5: TAIYO YUDEN JMK325BJ226MM

PGND PGND PGND

D1: MOTOROLA MBR0520L
L1: SUMIDA CDRH6D28-3R0
M1: ZETEX ZXM61P025

Figure 3

1.22V

3421 F03

ERROR

AMP

OUT

APPLICATIO S I FOR ATIO

LTC3421

3421f

PACKAGE DESCRIPTIO

UF Package

24-Lead Plastic QFN (4mm

4mm)

(Reference LTC DWG # 05-08-1697)

4.00

0.10

(4 SIDES)

NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE

PIN 1
TOP MARK
(NOTE 5)

0.38

0.10

0.23 TYP

(4 SIDES)

BOTTOM VIEW--EXPOSED PAD

2.45

0.10

(4-SIDES)

0.75

0.05

R = 0.115

TYP

0.25

0.05

0.50 BSC

0.200 REF

0.00 0.05

(UF24) QFN 0603

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70

0.05

0.25

0.05

0.50 BSC

2.45

0.05

(4 SIDES)

3.10

0.05

4.50

0.05

PACKAGE OUTLINE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3421

3421f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

LINEAR TECHNOLOGY CORPORATION 2003

LT/TP 1103 1K PRINTED IN USA

TYPICAL APPLICATIO

Single Cell to 3.3V at 500mA with Secondary Cell Backup During Shutdown. LOWBAT and V

REF

Output are Enabled

SHDN

ENB

REF

LBI

LBO

SYNC

LIM

OUTS

OUT

BURST

SW SW

4.7

GND

LTC3421

0.1

470pF

C5*
22

C1*
4.7

1V TO 1.5V

1 CELL

PRIMARY CELL

LOW BAT

OUTPUT

R2
28k

R3
40k

R4
100k

R5
340k

3V
SECONDARY CELL

OUT

3.3V
500mA

R6
200k

3421 TA05

R1
60k

604k

301k

0.1

*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM

PGND PGND PGND

C5: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A916CY-4R7M

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OUTPUT CURRENT (mA)

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3421