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112801

FEATURES

§ Real-time clock keeps track of hundredths of

seconds, minutes, hours, days, date of the
month, months, and years

§ 512k x 8 NV SRAM directly replaces

volatile static RAM or EEPROM

§ Embedded lithium energy cell maintains

calendar operation and retains RAM data

§ Watch function is transparent to RAM

operation

§ Month and year determine the number of

days in each month; valid up to 2100

§ Over 10 years of data retention in the

absence of power

§ Full 10% operating range

§ Lithium energy source is electrically

disconnected to retain freshness until power
is applied for the first time

§ DIP Module only

Standard 32-pin JEDEC pinout
Upward comparable with the DS1248

§ PowerCap

Module Board only

Surface mountable package for direct

connection to PowerCap containing
battery and crystal

Replaceable battery (PowerCap)
Pin for pin compatible with other densities

of DS124XP phantom clocks

PIN ASSIGNMENT

DS1251/DS1251P

4096k NV SRAM with Phantom Clock

www.maxim-ic.com

1
2
3
4
5
6
7
8
9
10
11
12

32-Pin Encapsulated Package

740mil Flush

A14

A5
A4
A3
A2
A1
A0

DQ1

DQ0

A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7

DQ5

DQ6

30
29
28
27
26
25
24
23
22
21

A16

A12

A18/RST

DQ2

GND

15
16

18
17

DQ4
DQ3

RST

A15

A16

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

A17

A14

A13

A12

A11

A10

A18

X1 GND V

BAT

34-Pin PowerCap Module Board

(Uses DS9034PCX PowerCap)

PowerCap is a registered trademark of Dallas Semiconductor.

DS1251/DS1251P

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ORDERING INFORMATION

DS1251YPXXXY (5V)

- IND Industrial

- 70 70ns access

blank 32-Pin DIP Module

34-Pin PowerCap Module board*

DS1251WP-XXXY (3.3V)

- IND Industrial
- 120 120ns access

blank 32-Pin DIP Module

34-Pin PowerCap Module board*

*DS9034PCX (PowerCap) Required:
(Must be ordered separately.)

PIN DESCRIPTION

Address

Inputs

- Chip Enable

- Output Enable

- Write Enable

- Power Supply Input

GND -

Ground

- Data In/Data Out

- No Connection

X1, X2

- Crystal Connection

BAT

- Battery Connection

RST

Reset

DESCRIPTION

The DS1251 4096k NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 512k
words by 8 bits) with a built-in real-time clock. The DS1251Y has a self-contained lithium energy source
and control circuitry, which constantly monitors V

for an out-of-tolerance condition. When such a

condition occurs, the lithium energy source is automatically switched on and write protection is
unconditionally enabled to prevent garbled data in both the memory and real-time clock.

The phantom clock provides timekeeping information including hundredths of seconds, seconds, minutes,
hours, days, dates, months, and years. The date at the end of the month is automatically adjusted for
months with fewer than 31 days, including correction for leap years. The phantom clock operates in either
24-hour or 12-hour format with an AM/PM indicator.

PACKAGES

The DS1251 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1251P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery because of the high temperatures required for
solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and
PowerCap are ordered separately and shipped in separate containers.

DS1251/DS1251P

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RAM READ MODE

The DS1251 executes a read cycle whenever

(write enable) is inactive (high) and

(chip enable) is

active (low). The unique address specified by the 19 address inputs (A0A18) defines which of the 512k
bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within t

ACC

(access time) after the last address input signal is stable, providing that

and

(output enable) access

times and states are also satisfied. If

and

access times are not satisfied, then data access must be

measured from the later occurring signal (

) and the limiting parameter is either t

for

, rather than address access.

RAM WRITE MODE

The DS1251 is in the write mode whenever the

and

signals are in the active (low) state after

address inputs are stable. The latter occurring falling edge of

will determine the start of the

write cycle. The write cycle is terminated by the earlier rising edge of

. All address inputs must

be kept valid throughout the write cycle.

must return to the high state for a minimum recovery time

) before another cycle can be initiated. The

control signal should be kept inactive (high) during

write cycles to avoid bus contention. However, if the output bus has been enabled (

and

active)

then

will disable the outputs in t

ODW

from its falling edge.

DATA RETENTION MODE

The 5V device is fully accessible and data can be written or read only when V

is greater than V

However, when V

is below the power-fail point, V

(point at which write protection occurs), the

internal clock registers and SRAM are blocked from any access. When V

falls below the battery switch

point, V

(battery supply level), device power is switched from the V

pin to the backup battery. RTC

operation and SRAM data are maintained from the battery until V

is returned to nominal levels.

The 3.3V device is fully accessible and data can be written or read only when V

is greater than V

PF.

When V

falls below the power-fail point, V

, access to the device is inhibited. If V

is less than V

BAT,

the device power is switched from V

to the backup supply (V

BAT

) when V

drops below V

. If V

greater than V

BAT

, the device power is switched from V

to the backup supply (V

BAT

) when V

drops

below V

BAT

. RTC operation and SRAM data are maintained from the battery until V

is returned to

nominal levels.

All control, data, and address signals must be powered down when V

is powered down.

PHANTOM CLOCK OPERATION

Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the

DS1251/DS1251P

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and

control of the phantom clock starts the pattern recognition sequence by moving a pointer to

the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the

and

control of the SmartWatch. These 64 write cycles are used only to gain access to the

phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write
cycles generated to gain access to the phantom clock are also writing data to a location in the mated
RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a
phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit
comparison register. If a match is found, the pointer increments to the next location of the comparison
register and awaits the next write cycle. If a match is not found, the pointer does not advance and all
subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the
present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for
a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or
from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either
receive or transmit data on DQ0, depending on the level of the

pin or the

pin. Cycles to other

locations outside the memory block can be interleaved with

cycles without interrupting the pattern

recognition sequence or data transfer sequence to the phantom clock.

PHANTOM CLOCK REGISTER INFORMATION

The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.

Data contained in the phantom clock register is in binary-coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.

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