General Description
The MAX19588 is a 3.3V, high-speed, high-perfor-
mance analog-to-digital converter (ADC) featuring a
fully differential wideband track-and-hold (T/H) and a
16-bit converter core. The MAX19588 is optimized for
multichannel, multimode receivers, which require the
ADC to meet very stringent dynamic performance
requirements. With a -82dBFS noise floor, the
MAX19588 allows for the design of receivers with supe-
rior sensitivity requirements.
At 100Msps, the MAX19588 achieves a 79dB signal-to-
noise ratio (SNR) and an 82.1dBc/97.7dBc single-tone
spurious-free dynamic range performance (SFDR1/
SFDR2) at f
IN
= 70MHz. The MAX19588 is not only opti-
mized for excellent dynamic performance in the 2nd
Nyquist region, but also for high-IF input frequencies. For
instance, at 130MHz, the MAX19588 achieves an
82.3dBc SFDR and its SNR performance stays flat (within
2.3dB) up to 175MHz. This level of performance makes
the part ideal for high-performance digital receivers.
The MAX19588 operates from a 3.3V analog supply
voltage and a 1.8V digital voltage, features a 2.56V
P-P
full-scale input range, and allows for a guaranteed sam-
pling speed of up to 100Msps. The input track-and-hold
stage operates with a 600MHz full-scale, full-power
bandwidth.
The MAX19588 features parallel, low-voltage CMOS-
compatible outputs in two's-complement output format.
The MAX19588 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extended
industrial (-40C to +85C) temperature range.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
High-Performance Instrumentation
Antenna Array Processing
Features
100Msps Conversion Rate
-82dBFS Noise Floor
Excellent Low-Noise Characteristics
SNR = 79.4dB at f
IN
= 10MHz
SNR = 79dB at f
IN
= 70MHz
Excellent Dynamic Range (SFDR1/SFDR2)
93.2dBc/102.5dBc at f
IN
= 10MHz
82.1dBc/97.7dBc at f
IN
= 70MHz
Less than 0.1ps Sampling Jitter
1275mW Power Dissipation
2.56V
P-P
Fully Differential Analog Input Voltage
Range
CMOS-Compatible Two's-Complement Data
Output
Separate Data Valid Clock and Over-Range Outputs
Flexible Input Clock Buffer
Small 56-Pin, 8mm x 8mm x 0.8mm Thin QFN
Package
EV Kit Available for MAX19588
(Order MAX19588EVKIT)
MAX19588
High-Dynamic-Range, 16-Bit,
100Msps ADC with -82dBFS Noise Floor
________________________________________________________________
Maxim Integrated Products
1
TOP VIEW
MAX19588
THIN QFN
8mm x 8mm
15
17
16
18
19
20
21
22
23
24
25
26
27
28
N.C.
N.C.
AV
DD
AV
DD
AV
DD
AGND
AGND
AGND
AV
DD
AV
DD
AV
DD
REFOUT
REFIN
AGND
AV
DD
AV
DD
N.C.
DOR
DGND
DV
DD
DAV
D15
D14
D13
D12
D11
D10
D9
48
47
46
45
44
43
54
53
56
55
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11 12 13 14
42 41 40 39 38 37 36 35 34 33 32 31 30 29
AGND
AGND
AGND
INN
INP
AGND
AGND
AGND
AGND
CLKN
CLKP
AGND
AV
DDA
AV
DDA
DGND
DGND
DV
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
DV
DD
DV
DD
EP
Pin Configuration
Ordering Information
19-0513; Rev 0; 5/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
+
Denotes lead-free package.
D = Dry pack.
*
EP = Exposed paddle.
PART
TEMP
RANGE
PIN-PACKAGE
PKG
CODE
MAX19588ETN-D
-40
C to
+85
C
56 Thin QFN-EP*
T5688-2
MAX19588ETN+D
-40
C to
+85
C
56 Thin QFN-EP*
T5688-2
MAX19588
High-Dynamic-Range, 16-Bit,
100Msps ADC with -82dBFS Noise Floor
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AV
DD
= AV
DDA
= 3.3V, DV
DD
= 1.8V, AGND = DGND = 0, internal reference, INP and INN driven differentially, CLKP and CLKN driven
differentially, C
L
= 5pF at digital outputs (D0D15, DOR), C
L
= 15pF for DAV, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are at T
A
= +25C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
DD
, AV
DDA
to AGND ........................................ -0.3V to +3.6V
DV
DD
to DGND..................................................... -0.3V to +2.4V
AGND to DGND.................................................... -0.3V to +0.3V
INP, INN, CLKP, CLKN, REFP, REFN,
REFIN, REFOUT to AGND....................-0.3V to (AV
DD
+ 0.3V)
D0D15, DAV, DOR to GND ....................-0.3V to (DV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70C)
56-Pin Thin QFN-EP
(derate 47.6mW/C above +70C) .........................3809.5mW
Operating Temperature Range ..........................-40C to +85C
Thermal Resistance
JA
..................................................21C/W
Thermal Resistance
JC
.................................................0.6C/W
Junction Temperature ......................................................+150C
Storage Temperature Range .............................-60C to +150C
Lead Temperature (soldering, 10s) .................................+300C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
N
16
Bits
Offset Error
V
OS
0
10
20
mV
Gain Error
GE
-3.5
+3.5
%FS
ANALOG INPUTS (INP, INN)
Input Voltage Range
V
DIFF
Fully differential input, V
IN
= V
INP
- V
INN
2.56
V
P-P
Common-Mode Voltage
V
CM
Internally self-biased
2.4
V
Differential Input Resistance
R
IN
10
20%
k
Differential Input Capacitance
C
IN
7
pF
Full-Power Analog Bandwidth
BW
-3dB
-3dB rolloff for FS Input
600
MHz
REFERENCE INPUT/OUTPUT (REFIN, REFOUT)
Reference Input Voltage Range
REFIN
1.28
10%
V
Reference Output Voltage
REFOUT
1.28
V
DYNAMIC SPECIFICATIONS (f
CLK
= 100Msps)
Thermal Plus Quantization Noise
Floor
NF
A
IN
< -35dBFS
-82
dBFS
f
IN
= 10MHz, A
IN
= -2dBFS
79.4
f
IN
= 70MHz, A
IN
= -2dBFS, T
A
= +25
C
77.5
79
f
IN
= 70MHz, A
IN
= -2dBFS
75.3
79
f
IN
= 105MHz, A
IN
= -2dBFS
78.3
f
IN
= 130MHz, A
IN
= -2dBFS
77.5
Signal-to-Noise Ratio
(First 4 Harmonics Excluded)
(Note 2)
SNR
f
IN
= 168MHz, A
IN
= -2dBFS
76.6
dB
MAX19588
High-Dynamic-Range, 16-Bit,
100Msps ADC with -82dBFS Noise Floor
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= AV
DDA
= 3.3V, DV
DD
= 1.8V, AGND = DGND = 0, internal reference, INP and INN driven differentially, CLKP and CLKN driven
differentially, C
L
= 5pF at digital outputs (D0D15, DOR), C
L
= 15pF for DAV, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are at T
A
= +25C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
IN
= 10MHz, A
IN
= -2dBFS
79
f
IN
= 70MHz, A
IN
= -2dBFS, T
A
= +25
C
75
77.1
f
IN
= 70MHz, A
IN
= -2dBFS
73.5
77.1
f
IN
= 105MHz, A
IN
= -2dBFS
77.1
f
IN
= 130MHz, A
IN
= -2dBFS
75.8
Signal-to-Noise Plus Distortion
(Note 2)
SINAD
f
IN
= 168MHz, A
IN
= -2dBFS
70.8
dB
f
IN
= 10MHz, A
IN
= -2dBFS
93.2
f
IN
= 70MHz, A
IN
= -2dBFS, T
A
= +25
C
79.6
82.1
f
IN
= 70MHz, A
IN
= -2dBFS
79.3
82.1
f
IN
= 105MHz, A
IN
= -2dBFS
86.6
f
IN
= 130MHz, A
IN
= -2dBFS
82.3
Spurious-Free Dynamic Range
(Worst Harmonic, 2nd and 3rd)
SFDR1
f
IN
= 168MHz, A
IN
= -2dBFS
75.4
dBc
f
IN
= 10MHz, A
IN
= -2dBFS
102.5
f
IN
= 70MHz, A
IN
= -2dBFS, T
A
= +25
C
90.4
97.7
f
IN
= 70MHz, A
IN
= -2dBFS
85
97.7
f
IN
= 105MHz, A
IN
= -2dBFS
94.2
f
IN
= 130MHz, A
IN
= -2dBFS
94.1
Spurious-Free Dynamic Range
(Worst Harmonic, 4th and Higher)
(Note 2)
SFDR2
f
IN
= 168MHz, A
IN
= -2dBFS
91.5
dBc
f
IN
= 10MHz, A
IN
= -2dBFS
-94.3
f
IN
= 70MHz, A
IN
= -2dBFS, T
A
= +25
C
-93
-83
f
IN
= 70MHz, A
IN
= -2dBFS
-93
-78.3
f
IN
= 105MHz, A
IN
= -2dBFS
-88
f
IN
= 130MHz, A
IN
= -2dBFS
-82.3
Second-Order Harmonic
Distortion
HD2
f
IN
= 168MHz, A
IN
= -2dBFS
-77.6
dBc
f
IN
= 10MHz, A
IN
= -2dBFS
-94.3
f
IN
= 70MHz, A
IN
= -2dBFS, T
A
= +25
C
-82.1
-79.6
f
IN
= 70MHz, A
IN
= -2dBFS
-82.1
-79.3
f
IN
= 105MHz, A
IN
= -2dBFS
-87.4
f
IN
= 130MHz, A
IN
= -2dBFS
-92.5
Third-Order Harmonic Distortion
HD3
f
IN
= 168MHz, A
IN
= -2dBFS
-75.4
dBc
Third-Order Intermodulation
Distortion
IM3
f
IN1
= 65.1MHz, A
IN1
= -8dBFS
f
IN2
= 70.1MHz, A
IN2
= -8dBFS
-87.7
dBc
Two-Tone SFDR
TTSFDR
f
IN1
= 65.1MHz, f
IN2
= 70.1MHz, -100dBFS
< A
IN
< -10dBFS
98
dBFS
CONVERSION RATE
Maximum Conversion Rate
f
CLKMAX
100
MHz
Minimum Conversion Rate
f
CLKMIN
20
MHz
Aperture Jitter
t
J
85
fs
RMS
MAX19588
High-Dynamic-Range, 16-Bit,
100Msps ADC with -82dBFS Noise Floor
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= AV
DDA
= 3.3V, DV
DD
= 1.8V, AGND = DGND = 0, internal reference, INP and INN driven differentially, CLKP and CLKN driven
differentially, C
L
= 5pF at digital outputs (D0D15, DOR), C
L
= 15pF for DAV, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical values are at T
A
= +25C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUTS (CLKP, CLKN)
Differential Input Swing
V
DIFFCLK
Fully differential inputs
1.0 to
5.0
V
P-P
Common-Mode Voltage
V
CMCLK
Self-biased
1.6
V
Differential Input Resistance
R
INCLK
10
k
Differential Input Capacitance
C
INCLK
3
pF
CMOS-COMPATIBLE DIGITAL OUTPUTS (D0D15, DOR, DAV)
Digital Output High Voltage
V
OH
I
SOURCE
= 200A
DV
DD
-
0.2
V
Digital Output Low Voltage
V
OL
I
SINK
= 200A
0.2
V
TIMING SPECIFICATIONS (Figures 4, 5), C
L
= 7.5pF (D0D15, DOR); C
L
= 35pF (DAV)
CLKP - CLKN High
t
CLKP
(Note 3)
4
ns
CLKP - CLKN Low
t
CLKN
(Note 3)
4
ns
Effective Aperture Delay
t
AD
-300
ps
Output Data Delay
t
DAT
3.4
ns
Data Valid Delay
t
DAV
(Note 3)
2.5
4
5.2
ns
Pipeline Latency
t
LATENCY
7
Clock
Cycles
CLKP Rising Edge to DATA Not
Valid
t
DNV
(Note 3)
1.1
ns
CLKP Rising Edge to DATA
Guaranteed Valid
t
DGV
(Note 3)
7.5
ns
DATA Setup Time Before Rising
DAV
t
S
Clock duty cycle = 50% (Note 3)
2
ns
DATA Hold Time After Rising
DAV
t
H
Clock duty cycle = 50% (Note 3)
2.5
ns
POWER SUPPLIES
Analog Power-Supply Voltage
AV
DD
,
A
VDDA
3.13
3.3
3.46
V
Digital Output Power-Supply
Voltage
DV
DD
1.7
1.8
1.9
V
Analog Power-Supply Current
I
AVDD
+
I
AVDDA
369
450
mA
Digital Output Power-Supply
Current
I
DVDD
31
42
mA
Power Dissipation
P
DISS
1275
1561
mW
Note 1: T
A
+25C guaranteed by production test, T
A
< +25C guaranteed by design and characterization. Typical values are at T
A
=
+25C.
Note 2: AC parameter measured in a 32,768-point FFT record, where the first 2 bins of the FFT and 2 bins on either side of the carrier
are excluded. For SNR and SINAD measurements, bins dominated by production test system noise are excluded.
Note 3: Parameter guaranteed by design and characterization.
MAX19588
High-Dynamic-Range, 16-Bit,
100Msps ADC with -82dBFS Noise Floor
_______________________________________________________________________________________
5
-140
-100
-120
-80
-60
-40
-20
0
0
10
5
15 20 25
35
45
30
40
FFT PLOT
(524,288-POINT DATA RECORD)
MAX19588 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
f
CLK
= 100MHz
f
IN
= 70.164MHz
A
IN
= -1.94dBFS
2
3
-140
-100
-120
-80
-60
-40
-20
0
0
10
5
15 20 25
35
45
FFT PLOT
(524,288-POINT DATA RECORD)
MAX19588 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
30
40
2
3
f
CLK
= 100MHz
f
IN
= 130.001MHz
A
IN
= -1.98dBFS
68
72
70
74
76
78
80
82
0
40
20
60
80 100 120 140 160 180
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(f
CLK
= 100MHz, A
IN
= -2dBFS)
MAX19588 toc03
f
IN
(MHz)
SNR/SINAD (dB)
SINAD
SNR
70
75
95
105
85
80
90
100
110
0
40
60
80
20
100 120 140 160 180
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 100MHz, A
IN
= -2dBFS)
MAX19588toc04
f
IN
(MHz)
SFDR1/SFDR2 (dBc)
SFDR2
SFDR1
-120
-110
-90
-100
-80
-70
0
40
60
80
20
100 120 140 160 180
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 100MHz, A
IN
= -2dBFS)
MAX19588toc05
f
IN
(MHz)
HD2/HD3 (dBc)
HD3
HD2
0
10
30
60
20
40
70
80
50
90
-80
-60
-50
-40
-70
-30
-20
-10
0
SNR vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 100MHz, f
IN
= 10MHz)
MAX19588toc06
ANALOG INPUT AMPLITUDE (dBFS)
SNR (dB, dBFS)
SNR (dBFS)
SNR (dB)
30
50
90
70
40
60
80
100
110
120
-80
-60
-50
-40
-70
-30
-20
-10
0
SFDR1 vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 100MHz, f
IN
= 10MHz)
MAX19588toc07
ANALOG INPUT AMPLITUDE (dBFS)
SFDR1 (dBc, dBFS)
SFDR1 (dBFS)
SFDR1 (dBc)
SFDR = 90dB
REFERENCE LINE
0
40
100
60
20
10
80
50
110
70
30
90
120
-80
-60
-50
-40
-70
-30
-20
-10
0
SFDR2 vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 100MHz, f
IN
= 10MHz)
MAX19588toc08
ANALOG INPUT AMPLITUDE (dBFS)
SFDR2 (dBc, dBFS)
SFDR2 (dBFS)
SFDR2 (dBc)
SFDR = 90dB
REFERENCE LINE
0
30
80
50
10
20
70
40
60
90
-80
-60
-50
-40
-70
-30
-20
-10
0
SNR vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 100MHz, f
IN
= 70MHz)
MAX19588toc09
ANALOG INPUT AMPLITUDE (dBFS)
SNR (dB, dBFS)
SNR (dBFS)
SNR (dB)
Typical Operating Characteristics
(AV
DD
= AV
DDA =
3.3V, DV
DD
= 1.8V, INP and INN driven differentially, internal reference, CLKP and CLKN driven differentially, C
L
=
7.5pF at digital outputs (D0D15, DOR), C
L
= 35pF for DAV, f
CLK
= 100MHz, T
A
= +25C. Unless otherwise noted, all AC data based
on 32k-point FFT records.)
PDF 
ZIP