MAX5875 DS
General Description
The MAX5875 is an advanced 16-bit, 200Msps, dual
digital-to-analog converter (DAC). This DAC meets the
demanding performance requirements of signal synthesis
applications found in wireless base stations and other
communications applications. Operating from +3.3V and
+1.8V supplies, this dual DAC offers exceptional dynamic
performance such as 78dBc spurious-free dynamic range
(SFDR) at f
OUT
= 16MHz and supports update rates of
200Msps, with a power dissipation of only 260mW.
The MAX5875 utilizes a current-steering architecture
that supports a 2mA to 20mA full-scale output current
range, and allows a 0.1V
P-P
to 1V
P-P
differential output
voltage swing. The device features an integrated +1.2V
bandgap reference and control amplifier to ensure
high-accuracy and low-noise performance. A separate
reference input (REFIO) allows for the use of an exter-
nal reference source for optimum flexibility and
improved gain accuracy.
The digital and clock inputs of the MAX5875 accept
3.3V CMOS voltage levels. The device features a flexi-
ble input data bus that allows for dual-port input or a
single-interleaved data port. The MAX5875 is available
in a 68-pin QFN package with an exposed paddle (EP)
and is specified for the extended temperature range
(-40C to +85C).
Refer to the MAX5873 and MAX5874 data sheets for
pin-compatible 12-bit and 14-bit versions of the
MAX5875, respectively. Refer to the MAX5878 data
sheet for an LVDS-compatible version of the MAX5875.
Applications
Base Stations: Single/Multicarrier UMTS, CDMA,
GSM
Communications: Fixed Broadband Wireless
Access, Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Features
200Msps Output Update Rate
Noise Spectral Density = -162dBFS/Hz at f
OUT
=
16MHz
Excellent SFDR and IMD Performance
SFDR = 78dBc at f
OUT
= 16MHz (to Nyquist)
SFDR = 75dBc at f
OUT
= 80MHz (to Nyquist)
IMD = -86dBc at f
OUT
= 10MHz
IMD = -76dBc at f
OUT
= 80MHz
ACLR = 75dB at f
OUT
= 61MHz
2mA to 20mA Full-Scale Output Current
CMOS-Compatible Digital and Clock Inputs
On-Chip +1.20V Bandgap Reference
Low 260mW Power Dissipation
Compact 68-Pin QFN-EP Package (10mm x 10mm)
Evaluation Kit Available (MAX5875EVKIT)
MAX5875
16-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
________________________________________________________________ Maxim Integrated Products
1
58
59
60
61
62
54
55
56
57
63
38
39
40
41
42
43
44
45
46
47
DV
DD3.3
AV
DD1.8
A14
QFN
TOP VIEW
A15
DV
DD1.8
B0
B1
B2
B3
B4
B5
B6
52
53
B7
B8
DACREF
AV
DD3.3
GND
GND
AV
DD3.3
OUTQP
OUTQN
GND
GND
OUTIP
OUTIN
AV
DD3.3
GND
AV
DD3.3
B13
B14
B15
SELIQ
GND
XOR
DORI
PD
TORB
CLKP
35
36
37
CLKN
GND
AV
CLK
GND
A0
A1
A2
A3
REFIO
GND
AV
DD3.3
GND
GND
A4
A5
A6
A7
48
B12
A8
64
A13
65
66
67
A10
A11
A12
68
A9
23
22
21
20
19
27
26
25
24
18
29
28
32
31
30
GND
AV
DD1.8
34
33
49
50
B10
B11
51
B9
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
FSADJ
17
MAX5875
Pin Configuration
Ordering Information
19-3515; Rev 0; 2/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
**EP = Exposed pad.
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-
PACKAGE
PKG CODE
MAX5875EGK
-40C to +85C
68 QFN-EP**
G6800-4
Selector Guide
PART
RESOLUTION
(Bits)
UPDATE
RATE (Msps)
LOGIC
INPUTS
MAX5873
12
200
CMOS
MAX5874
14
200
CMOS
MAX5875
16
200
CMOS
MAX5876*
12
250
LVDS
MAX5877*
14
250
LVDS
MAX5878
16
250
LVDS
*Future product--contact factory for availability.
MAX5875
16-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
DD1.8
, DV
DD1.8
to GND, DACREF ..................-0.3V to +2.16V
AV
DD3.3
, DV
DD3.3
, AV
CLK
to GND, DACREF ........-0.3V to +3.9V
REFIO, FSADJ to GND, DACREF ........-0.3V to (AV
DD3.3
+ 0.3V)
OUTIP, OUTIN, OUTQP, OUTQN to
GND, DACREF....................................-1V to (AV
DD3.3
+ 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AV
CLK
+ 0.3V)
A15/B15A0/B0, XOR, SELIQ to
GND, DACREF .....................................-0.3V to (DV
DD3.3
+ 0.3V)
TORB, DORI, PD to GND, DACREF ....-0.3V to (DV
DD3.3
+ 0.3V)
Continuous Power Dissipation (T
A
= +70C)
68-Pin QFN-EP
(derate 41.7mW/C above +70C) (Note 1) ............3333.3mW
Thermal Resistance
JA
(Note 1)...................................+24C/W
Operating Temperature Range ...........................-40C to +85C
Junction Temperature ......................................................+150C
Storage Temperature Range .............................-60C to +150C
Lead Temperature (soldering, 10s) .................................+300C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
16
Bits
Integral Nonlinearity
INL
Measured differentially
3
LSB
Differential Nonlinearity
DNL
Measured differentially
2
LSB
Offset Error
OS
-0.025
0.001
+0.025
%FS
Offset-Drift Tempco
10
ppm/
C
Full-Scale Gain Error
GE
FS
External reference
1
%FS
Internal reference
100
Gain-Drift Tempco
External reference
50
ppm/
C
Full-Scale Output Current
I
OUTFS
(Note 3)
2
20
mA
Output Compliance
Single-ended
-0.5
+1.1
V
Output Resistance
R
OUT
1
M
Output Capacitance
C
OUT
5
pF
DYNAMIC PERFORMANCE
Clock Frequency
f
CLK
1
200
MHz
f
DAC
= f
CLK
/ 2, single-port mode
1
100
Output Update Rate
f
DAC
f
DAC
= f
CLK
, dual-port mode
1
200
Msps
f
DAC
= 150MHz
f
OUT
= 16MHz, -12dBFS
-162
Noise Spectral Density
f
DAC
= 200MHz
f
OUT
= 80MHz, -12dBFS
-160
dBFS/Hz
ELECTRICAL CHARACTERISTICS
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= +1.25V, output
load 50
double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25C.) (Note 2)
Note 1: Thermal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.
MAX5875
16-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= +1.25V, output
load 50
double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
OUT
= 1MHz, 0dBFS
88
f
OUT
= 1MHz, -6dBFS
84
f
OUT
= 1MHz, -12dBFS
82
f
OUT
= 10MHz, -12dBFS
81
f
DAC
= 100MHz
f
OUT
= 30MHz, -12dBFS
79
f
OUT
= 10MHz, -12dBFS
80
f
OUT
= 16MHz, -12dBFS,
T
A
+25
o
C
71
78
f
OUT
= 16MHz, 0dBFS
87
f
OUT
= 50MHz, -12dBFS
78
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
DAC
= 200MHz
f
OUT
= 80MHz, -12dBFS
75
dBc
Spurious-Free Dynamic Range,
25MHz Bandwidth
SFDR
f
DAC
= 150MHz
f
OUT
= 16MHz, -12dBFS
84
dBc
f
DAC
= 100MHz
f
OUT1
= 9MHz, -7dBFS;
f
OUT2
= 10MHz, -7dBFS
-86
Two-Tone IMD
TTIMD
f
DAC
= 200MHz
f
OUT1
= 79MHz, -7dBFS;
f
OUT2
= 80MHz, -7dBFS
-76
dBc
Four-Tone IMD, 1MHz
Frequency Spacing, GSM Model
FTIMD
f
DAC
= 150MHz
f
OUT
= 16MHz, -12dBFS
-86
dBc
Adjacent Channel Leakage Power
Ratio 3.84MHz Bandwidth,
W-CDMA Model
ACLR
f
DAC
=
184.32MHz
f
OUT
= 61.44MHz
75
dB
Output Bandwidth
BW
-1dB
(Note 4)
240
MHz
INTER-DAC CHARACTERISTICS
Gain Matching
Gain
f
OUT
= DC - 80MHz
0.2
dB
Gain-Matching Tempco
Gain/C
20
ppm/
C
Phase Matching
Phase
f
OUT
= 60MHz
0.25
D egr ees
Phase-Matching Tempco
Phase/C f
OUT
= 60MHz
0.002
D eg r ees/
C
Channel-to-Channel Crosstalk
f
CLK
= 200MHz, f
OUT
= 50MHz
-70
dB
REFERENCE
Internal Reference Voltage Range
V
REFIO
1.14
1.2
1.26
V
Reference Input Compliance
Range
V
REFIOCR
0.125
1.250
V
Reference Input Resistance
R
REFIO
10
k
Reference Voltage Drift
TCO
REF
25
ppm/
C
MAX5875
16-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= +1.25V, output
load 50
double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG OUTPUT TIMING (See Figure 4)
Output Fall Time
t
FALL
90% to 10% (Note 5)
0.7
ns
Output Rise Time
t
RISE
10% to 90% (Note 5)
0.7
ns
Output Propagation Delay
t
PD
Excluding data latency (Note 5)
1.1
ns
Glitch Impulse
Measured differentially
1
pV
s
I
OUTFS
= 2mA
30
Output Noise
n
OUT
I
OUTFS
= 20mA
30
pA/
Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time
t
SETUP
Referenced to rising edge of clock (Note 6)
-0.6
-1.2
ns
Data to Clock Hold Time
t
HOLD
Referenced to rising edge of clock (Note 6)
2.1
1.5
ns
Latency to I output
9
Single-Port (Interleaved Mode)
Data Latency
Latency to Q output
8
Clock
Cycles
Dual-Port (Parallel Mode) Data
Latency
5.5
Clock
Cycles
Minimum Clock Pulse-Width High
t
CH
CLKP, CLKN
2.4
ns
Minimum Clock Pulse-Width Low
t
CL
CLKP, CLKN
2.4
ns
CMOS LOGIC INPUTS (A15/B15A0/B0, XOR, SELIQ, PD, TORB,
DORI)
Input-Logic High
V
IH
0.7 x
DV
DD3.3
V
Input-Logic Low
V
IL
0.3 x
DV
DD3.3
V
Input Leakage Current
I
IN
1
20
A
PD, TORB, DORI Internal
Pulldown Resistance
V
PD
= V
TORB
= V
DORI
= 3.3V
1.5
M
Input Capacitance
C
IN
2.5
pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
>1.5
Differential Input
Voltage Swing
Square wave
>0.5
V
P-P
Differential Input Slew Rate
SR
CLK
(Note 7)
>100
V/s
External Common-Mode Voltage
Range
V
COM
AV
CLK
/ 2
0.3
V
Input Resistance
R
CLK
5
k
Input Capacitance
C
CLK
2.5
pF
POWER SUPPLIES
AV
DD3.3
3.135
3.3
3.465
Analog Supply Voltage Range
AV
DD1.8
1.710
1.8
1.890
V
DV
DD3.3
3.135
3.3
3.465
Digital Supply Voltage Range
DV
DD1.8
1.710
1.8
1.890
V
MAX5875
16-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= +1.25V, output
load 50
double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25C.) (Note 2)
Note 2: Specifications at T
A
+25C are guaranteed by production testing. Specifications at T
A
< +25C are guaranteed by design
and characterization data.
Note 3: Nominal full-scale current I
OUTFS
= 32 x I
REF
.
Note 4: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5875.
Note 5: Parameter measured single-ended into a 50
termination resistor.
Note 6: Not production tested. Guaranteed by design and characterization data.
Note 7: A differential clock input slew rate of >100V/s is required to achieve the specified dynamic performance.
Note 8: Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage.
Typical Operating Characteristics
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference, V
REFIO
= +1.25V, R
L
= 50
double-terminated,
I
OUTFS
= 20mA, T
A
= +25C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 50Msps)
MAX5875 toc01
f
OUT
(MHz)
SFDR (dBc)
20
15
10
5
20
40
60
80
100
0
0
25
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 100Msps)
MAX5875 toc02
f
OUT
(MHz)
SFDR (dBc)
40
30
20
10
20
40
60
80
100
0
0
50
-12dBFS -6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 150Msps)
MAX5875 toc03
f
OUT
(MHz)
SFDR (dBc)
60
45
30
15
20
40
60
80
100
0
0
75
-12dBFS
-6dBFS
0dBFS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
DAC
= 200Msps, f
OUT
= 1MHz
53
56
I
AVDD3.3
Power-down
0.002
f
DAC
= 200Msps, f
OUT
= 1MHz
25
32
Analog Supply Current
I
AVDD1.8
Power-down
0.001
mA
f
DAC
= 200Msps, f
OUT
= 1MHz
0.5
3
I
DVDD3.3
Power-down
0.001
f
DAC
= 200Msps, f
OUT
= 1MHz
22
25
Digital Supply Current
I
DVDD1.8
Power-down
0.001
mA
f
DAC
= 200Msps, f
OUT
= 1MHz
260
300
mW
Power Dissipation
P
DISS
Power-down
14
W
Power-Supply Rejection Ratio
PSRR
AV
DD3.3
= AV
CLK
= DV
DD3.3
= +3.3V
5%
(Notes 7, 8)
-0.1
+0.1
%FS/V
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