General Description
The MAX5877 is an advanced 14-bit, 250Msps, dual
digital-to-analog converter (DAC). This DAC meets the
demanding performance requirements of signal synthesis
applications found in wireless base stations and other
communications applications. Operating from +3.3V and
+1.8V supplies, this dual DAC offers exceptional dynamic
performance such as 75dBc spurious-free dynamic range
(SFDR) at f
OUT
= 16MHz and supports update rates of
250Msps, with a power dissipation of only 287mW.
The MAX5877 utilizes a current-steering architecture
that supports a 2mA to 20mA full-scale output current
range, and allows a 0.1V
P-P
to 1V
P-P
differential output
voltage swing. The device features an integrated +1.2V
bandgap reference and control amplifier to ensure
high-accuracy and low-noise performance. A separate
reference input (REFIO) allows for the use of an exter-
nal reference source for optimum flexibility and
improved gain accuracy.
The clock inputs of the MAX5877 accept both LVDS
and LVPECL-compatible voltage levels. The device fea-
tures an interleaved data input that allows a single
LVDS bus to support both DACs. The MAX5877 is avail-
able in a 68-pin QFN package with an exposed pad
(EP) and is specified for the extended temperature
range (-40C to +85C).
Refer to the MAX5876 and MAX5878 data sheets for
pin-compatible 12-bit and 16-bit versions of the
MAX5877, respectively. Refer to the MAX5874 data
sheet for a CMOS-compatible version of the MAX5877.
Applications
Base Stations: Single/Multicarrier UMTS, CDMA, GSM
Communications: Fixed Broadband Wireless Access,
Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Features
o 250Msps Output Update Rate
o Noise Spectral Density = -160dBFS/Hz
at f
OUT
= 16MHz
o Excellent SFDR and IMD
SFDR = 75dBc at f
OUT
= 16MHz (to Nyquist)
SFDR = 71dBc at f
OUT
= 80MHz (to Nyquist)
IMD = -87dBc at f
OUT
= 10MHz
IMD = -73dBc at f
OUT
= 80MHz
o ACLR = 75dB at f
OUT
= 61MHz
o 2mA to 20mA Full-Scale Output Current
o LVDS-Compatible Digital and Clock Inputs
o On-Chip +1.20V Bandgap Reference
o Low 287mW Power Dissipation
o Compact 68-Pin QFN-EP Package (10mm x 10mm)
o Evaluation Kit Available (MAX5878EVKIT)
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
________________________________________________________________ Maxim Integrated Products
1
58
59
60
61
62
54
55
56
57
63
38
39
40
41
42
43
44
45
46
47
DV
DD3.3
AV
DD1.8
B5N
QFN
TOP VIEW
B5P
DV
DD1.8
B6N
B6P
B7N
B7P
B8N
B8P
B9N
52
53
B9P
B10N
DACREF
AV
DD3.3
GND
GND
AV
DD3.3
OUTQP
OUTQN
GND
GND
OUTIP
OUTIN
AV
DD3.3
GND
AV
DD3.3
B12P
B13N
B13P
SELIQN
SELIQP
XORP
XORN
PD
TORB
CLKP
35
36
37
CLKN
GND
AV
CLK
GND
N.C.
N.C.
N.C.
N.C.
REFIO
GND
AV
DD3.3
GND
GND
B0N
B0P
B1N
B1P
48
B12N
B2N
64
B4P
65
66
67
B3N
B3P
B4N
68
B2P
23
22
21
20
19
27
26
25
24
18
29
28
32
31
30
GND
AV
DD1.8
34
33
49
50
B11N
B11P
51
B10P
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
FSADJ
17
MAX5877
Pin Configuration
Ordering Information
19-3632; Rev 0; 4/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
*EP = Exposed pad.
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-
PACKAGE
PKG CODE
MAX5877EGK
-40C to +85C
68 QFN-EP*
G6800-4
Selector Guide
PART
RESOLUTION
(BITS)
UPDATE
RATE (Msps)
LOGIC
INPUTS
MAX5873
12
200
CMOS
MAX5874
14
200
CMOS
MAX5875
16
200
CMOS
MAX5876
12
250
LVDS
MAX5877
14
250
LVDS
MAX5878
16
250
LVDS
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
DD1.8
, DV
DD1.8
to GND, DACREF...................-0.3V to +2.16V
AV
DD3.3
, DV
DD3.3
, AV
CLK
to GND, DACREF ........-0.3V to +3.9V
REFIO, FSADJ to
GND, DACREF..................................-0.3V to (AV
DD3.3
+ 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF ...................-1V to (AV
DD3.3
+ 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AV
CLK
+ 0.3V)
B13P/B13NB0P/B0N, XORN, XORP, SELIQN,
SELIQP to GND, DACREF ...................-0.3V to (DV
DD1.8
+ 0.3V)
TORB, PD to GND, DACREF ...............-0.3V to (DV
DD3.3
+ 0.3V)
Continuous Power Dissipation (T
A
= +70C)
68-Pin QFN-EP
(derate 41.7mW/C above +70C) (Note 1) ............3333.3mW
Thermal Resistance
JA
(Note 1)...................................+24C/W
Operating Temperature Range ......................... -40C to +85C
Junction Temperature .................................................... +150C
Storage Temperature Range ........................... -60C to +150C
Lead Temperature (soldering, 10s) ............................... +300C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
14
Bits
Integral Nonlinearity
INL
Measured differentially
0.5
LSB
Differential Nonlinearity
DNL
Measured differentially
0.2
LSB
Offset Error
OS
-0.015
0.001 +0.015
%FS
Offset-Drift Tempco
10
ppm/
C
Full-Scale Gain Error
GE
FS
External reference
-4.4
-0.6
+4.4
%FS
Internal reference
100
Gain-Drift Tempco
External reference
50
ppm/
C
Full-Scale Output Current
I
OUTFS
(Note 3)
2
20
mA
Output Compliance
Single-ended
-0.5
+1.1
V
Output Resistance
R
OUT
1
M
Output Capacitance
C
OUT
5
pF
DYNAMIC PERFORMANCE
Clock Frequency
f
CLK
2
500
MHz
Output Update Rate
f
DAC
f
DAC
= f
CLK
/ 2
1
250
Msps
f
DAC
= 150MHz
f
OUT
= 16MHz, -12dBFS
-160
Noise Spectral Density
f
DAC
= 250MHz
f
OUT
= 80MHz, -12dBFS
-157
dBFS/
Hz
ELECTRICAL CHARACTERISTICS
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50
double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25C.) (Note 2)
Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50
double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
OUT
= 1MHz, 0dBFS
98
f
OUT
= 1MHz, -6dBFS
86
f
OUT
= 1MHz, -12dBFS
78
f
OUT
= 10MHz, -12dBFS
77
f
DAC
= 100MHz
f
OUT
= 30MHz, -12dBFS
78
f
OUT
= 10MHz, -12dBFS
75
f
OUT
= 16MHz, -12dBFS,
T
A
+25
o
C
67
75
f
OUT
= 16MHz, -12dBFS
66
75
f
OUT
= 50MHz, -12dBFS
74
f
DAC
= 200MHz
f
OUT
= 80MHz, -12dBFS
71
f
OUT
= 10MHz, -12dBFS
74
f
OUT
= 50MHz, -12dBFS
72
f
OUT
= 80MHz, -12dBFS
71
Spurious-Free Dynamic Range
to Nyquist
SFDR
f
DAC
= 250MHz
f
OUT
= 100MHz, -12dBFS
68
dBc
Spurious-Free Dynamic Range,
25MHz Bandwidth
SFDR
f
DAC
= 150MHz
f
OUT
= 16MHz, -12dBFS
80
dBc
f
DAC
= 100MHz
f
OUT1
= 9MHz, -7dBFS;
f
OUT2
= 10MHz, -7dBFS
-87
Two-Tone IMD
TTIMD
f
DAC
= 200MHz
f
OUT1
= 79MHz, -7dBFS;
f
OUT2
= 80MHz, -7dBFS
-73
dBc
Four-Tone IMD, 1MHz
Frequency Spacing, GSM Model
FTIMD
f
DAC
= 150MHz
f
OUT
= 16MHz, -12dBFS
-94
dBc
Adjacent Channel Leakage Power
Ratio 3.84MHz Bandwidth,
W-CDMA Model
ACLR
f
DAC
=
184.32MHz
f
OUT
= 61.44MHz
75
dB
Output Bandwidth
BW
-1dB
(Note 4)
240
MHz
INTER-DAC CHARACTERISTICS
f
OUT
= DC - 80MHz
0.2
Gain Matching
Gain
f
OUT
= DC
-0.25
+0.01
+0.25
dB
Gain-Matching Tempco
Gain/C
20
ppm/
C
Phase Matching
Phase
f
OUT
= 60MHz
0.25
D egr ees
Phase-Matching Tempco
Phase/C f
OUT
= 60MHz
0.002
D eg r ees/
C
Channel-to-Channel Crosstalk
f
DAC
= 200Msps, f
OUT
= 50MHz, 0dBFS
90
dB
REFERENCE
Internal Reference Voltage Range
V
REFIO
1.14
1.2
1.26
V
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50
double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Input Compliance
Range
V
REFIOCR
0.125
1.260
V
Reference Input Resistance
R
REFIO
10
k
Reference Voltage Drift
TCO
REF
25
ppm/
C
ANALOG OUTPUT TIMING (See Figure 4)
Output Fall Time
t
FALL
90% to 10% (Note 5)
0.7
ns
Output Rise Time
t
RISE
10% to 90% (Note 5)
0.7
ns
Output Propagation Delay
t
PD
Excluding data latency (Note 5)
1.1
ns
Glitch Impulse
Measured differentially
1
pV
s
I
OUTFS
= 2mA
30
Output Noise
n
OUT
I
OUTFS
= 20mA
30
pA/
Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time
t
SETUP
Referenced to rising edge of clock (Note 6)
-1.2
ns
Data to Clock Hold Time
t
HOLD
Referenced to rising edge of clock (Note 6)
2.0
ns
Latency to I output
9
Data Latency
Latency to Q output
8
Clock
Cycles
Minimum Clock Pulse-Width High
t
CH
CLKP, CLKN
0.9
ns
Minimum Clock Pulse-Width Low
t
CL
CLKP, CLKN
0.9
ns
LVDS LOGIC INPUTS (B13P/B13NB0P/B0N, XORN, XORP, SELIQN, SELIQP)
Differential Input-Logic High
V
IH
100
mV
Differential Input-Logic Low
V
IL
-100
mV
Common-Mode Voltage Range
V
CMR
1.125
1.375
V
Differential Input Resistance
R
IN
(Note 7)
110
Input Capacitance
C
IN
2.5
pF
CMOS LOGIC INPUTS (PD, TORB)
Input-Logic High
V
IH
0.7 x
DV
DD3.3
V
Input-Logic Low
V
IL
0.3 x
DV
DD3.3
V
Input Leakage Current
I
IN
-20
1
+20
A
PD, TORB Internal Pulldown
Resistance
V
PD
= V
TORB
= 3.3V
1.5
M
Input Capacitance
C
IN
2.5
pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
>1.5
Differential Input
Voltage Swing
Square wave
>0.5
V
P-P
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50
double-terminated, transformer-coupled output, I
OUTFS
= 20mA, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25C.) (Note 2)
Note 2: Specifications at T
A
+25C are guaranteed by production testing. Specifications at T
A
< +25C are guaranteed by design.
Note 3: Nominal full-scale current I
OUTFS
= 32 x I
REF
.
Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5877.
Note 5: Parameter measured single-ended into a 50
termination resistor.
Note 6: Not production tested. Guaranteed by design.
Note 7: No termination resistance between XORP and XORN.
Note 8: A differential clock input slew rate of >100V/s is required to achieve the specified dynamic performance.
Note 9: Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Input Slew Rate
SR
CLK
(Note 8)
>100
V/s
External Common-Mode Voltage
Range
V
COM
AV
CLK
/ 2
0.3
V
Input Resistance
R
CLK
5
k
Input Capacitance
C
CLK
2.5
pF
POWER SUPPLIES
AV
DD3.3
3.135
3.3
3.465
Analog Supply Voltage Range
AV
DD1.8
1.710
1.8
1.890
V
DV
DD3.3
3.135
3.3
3.465
Digital Supply Voltage Range
DV
DD1.8
1.710
1.8
1.890
V
Clock Supply Voltage Range
AV
CLK
3.135
3.3
3.465
V
f
DAC
= 250Msps, f
OUT
= 16MHz
52
56
mA
I
AVDD3.3
+ I
AVCLK
Power-down
1
A
f
DAC
= 250Msps, f
OUT
= 16MHz
30
36
mA
Analog Supply Current
I
AVDD1.8
Power-down
1
A
f
DAC
= 250Msps, f
OUT
= 16MHz
0.2
1
mA
I
DVDD3.3
Power-down
1
A
f
DAC
= 250Msps, f
OUT
= 16MHz
34
40
mA
Digital Supply Current
I
DVDD1.8
Power-down
4
A
f
DAC
= 250Msps, f
OUT
= 16MHz
287
324
mW
Power Dissipation
P
DISS
Power-down
16
W
Power-Supply Rejection Ratio
PSRR
AV
DD3.3
= AV
CLK
= DV
DD3.3
= +3.3V
5%
(Notes 8, 9)
-0.1
+0.1
%FS/V
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