BLOCK DIAGRAM
IN
V
BB
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
Q
6
Q
6
Q
7
Q
7
Q
8
Q
8
IN
EN
FEATURES
s
Low skew
s
Extended 100E V
EE
range of 4.2V to 5.5V
s
Guaranteed skew limits
s
Differential design
s
V
BB
output
s
Enable input
s
Fully compatible with industry standard 10KH, 100K
I/O levels
s
75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E111
s
Available in 28-pin PLCC package
The SY10/100E111 are low skew 1-to-9 differential
drivers designed for clock distribution in new, high-
performance ECL systems. They accept one differential or
single-ended input, with V
BB
used for single-ended
operation. The signal is fanned out to nine identical
differential outputs. An enable input is also provided such
that a logic HIGH disables the device by forcing all Q
outputs LOW and all Q outputs HIGH.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the E111 shares a common set of "basic"
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50
, even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same V
CCO
as the pair(s) being used on that side) in order
to maintain minimum skew.
The V
BB
output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using V
BB
for this purpose, it is
recommended that V
BB
is decoupled to V
CC
via a 0.01
F
capacitor.
1:9 DIFFERENTIAL CLOCK
DRIVER WITH ENABLE
DESCRIPTION
Rev.: B
Amendment: /2
Issue Date: February, 1998
ClockWorksTM
SY10E111
SY100E111
1
3
ClockWorksTM
SY10E111
SY100E111
Micrel
NOTES:
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential
output signals.
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
3. Enable is defined as the propagation delay from the 50% point of a negative transition on EN to the 50% point of a positive transition on Q (or a negative
transition on Q). Disable is defined as the propagation delay from the 50% point of a positive transition on EN to the 50% point of a negative transition
on Q (or a positive transition on Q).
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. The set-up time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
75mV to
that IN/IN transition (see Figure 1).
6. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output response greater
than
75mV to that IN/IN transition (see Figure 2).
7. The release time is the minimum time that EN must be de-asserted prior to the next IN/IN transition to ensure an output response that meets the specified
IN to Q propagation delay and output transition times (see Figure 3).
8. V
PP
(min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The V
PP
(min.) is AC limited for the
E111, as a differential input as low as 50mV will still produce full ECL levels at the output.
9. V
CMR
is defined as the range within which the V
IH
level may vary, with the device still meeting the propagation delay specification. The V
IL
level must be
such that the peak-to-peak voltage is less than 1.0V and greater than or equal to V
PP
(min.).
AC ELECTRICAL CHARACTERISTICS
V
EE
= V
EE
(Min.) to V
EE
(Max.); V
CC
= V
CCO
= GND
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Typ. Max. Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Condition
(1-9)
t
PLH
Propagation Delay to Output
ps
t
PHL
IN (differential)
430
--
630
430
--
630
430
--
630
1
IN (single-ended)
330
--
730
330
--
730
330
--
730
2
Enable
450
--
850
450
--
850
450
--
850
3
Disable
450
--
850
450
--
850
450
--
850
3
t
SKEW
Within-Device Skew
--
25
50
--
25
50
--
25
50
ps
4
t
S
Set-up Time, EN to IN
200
0
--
200
0
--
200
0
--
ps
5
t
H
Hold Time, IN to EN
0
200
--
0
200
--
0
200
--
ps
6
t
R
Release Time, EN to IN
300
100
--
300
100
--
300
100
--
ps
7
V
PP
Minimum Input Swing
250
--
--
250
--
--
250
--
--
mV
8
V
CMR
Common Mode Range
1.6
--
0.4
1.6
--
0.4
1.6
--
0.4
V
9
t
r
Rise/Fall Times
275
375
600
275
375
600
275
375
600
ps
--
t
f
20% to 80%
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY10E111JC
J28-1
Commercial
SY10E111JCTR
J28-1
Commercial
SY100E111JC
J28-1
Commercial
SY100E111JCTR
J28-1
Commercial
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