1
ClockWorksTM
SY100EL15L
Micrel
The SY100EL15L is a low skew 1:4 clock distribution
IC designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used the V
BB
output should be connected
to the CLK input and bypassed to ground via a 0.01
F
capacitor. The V
BB
output is designed to act as the
switching reference for the input of the EL15 under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
The EL15 features a multiplexed clock input to allow
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
When both differential inputs are left open, CLK input
will pull down to V
EE
and CLK input will bias around
V
CC
/2.
Pin
Function
CLK
Differential Clock Inputs
SCLK
Synchronous Clock Input
EN
Synchronous Enable
SEL
Clock Select Input
V
BB
Reference Output
Q
0-3
Differential Clock Outputs
TRUTH TABLE
PIN NAMES
FEATURES
DESCRIPTION
1999 Micrel
Rev.: A
Amendment: /0
Issue Date: December 1999
PIN CONFIGURATION/BLOCK DIAGRAM
ClockWorksTM
SY100EL15L
CLK
SCLK
SEL
EN
Q
L
X
L
L
L
H
X
L
L
H
X
L
H
L
L
X
H
H
L
H
X
X
X
H
L*
* On next negative transition of CLK or SCLK
V
CC
CLK
Q
0
Q
0
Q
1
Q
2
Q
2
Q
3
Q
3
V
EE
SEL
V
BB
CLK
EN
16
15
14
13
12
11
10
9
Q
1
1
2
3
4
5
6
7
8
D
Q
1 0
SCLK
SOIC
TOP VIEW
s
3.3V power supply
s
50ps output-to-output skew
s
Low power
s
Synchronous enable/disable
s
Multiplexed clock input
s
75K
internal input pull-down resistors
s
ESD protection of 2000V
s
Available in 16-pin SOIC package
3.3V 1:4 CLOCK
DISTRIBUTION
SynergyTM High-Speed Products
2
ClockWorksTM
SY100EL15L
Micrel
Symbol
Rating
Value
Unit
V
EE
Power Supply (V
CC
= 0V)
8.0 to 0
VDC
V
I
Input Voltage (V
CC
= 0V)
0 to 6.0
VDC
I
OUT
Output Current
Continuous
50
mA
Surge
100
T
A
Operating Temperature Range
40 to +85
C
NOTES:
1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2. Parametric values specified at:
3 volt Power Supply Range
100EL15L Series
3.0V to 3.8V.
ABSOLUTE MAXIMUM RATINGS
(1)
T
A
= 40
C
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Typ.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage
(2)
1085
880
1025
880
1025
955
880
1025
880
mV
V
OL
Output LOW Voltage
(2)
1830
1555
1810
1620
1810
1705
1620
1810
1620
mV
V
OHA
Output HIGH Voltage
(3)
1095
--
1035
--
1035
--
--
1035
--
mV
V
OLA
Output LOW Voltage
(3)
--
1555
--
1610
--
--
1610
--
1610
mV
V
IH
Input HIGH Voltage
1165
880
1165
880
1165
--
880
1165
880
mV
V
IL
Input LOW Voltage
1810
1475
1810
1475
1810
--
1475
1810
1475
mV
I
IH
Input High Current
--
150
--
150
--
--
150
--
150
A
I
IL
Input LOW Current
(4)
0.5
--
0.5
--
0.5
--
0.5
--
A
CLK
300
--
300
--
300
--
--
300
--
I
EE
Power Supply Current
--
35
--
35
--
25
35
--
38
mA
V
BB
Output Reference Voltage
1.38
1.26
1.38
1.26
1.38
--
1.26
1.38
1.26
V
DC ELECTRICAL CHARACTERISTICS
V
EE
= 3.3V
10%; V
CC
= GND
(1)
NOTES:
1. This table replaces the three traditionally seen in ECL 100K data books. Outputs are terminated through a 50
resistor to 2.0V.
2. V
IN
= V
IH
(Max) or V
IL
(Min).
3. V
IN
= V
IH
(Min) or V
IL
(Max).
4. V
IN
= V
IL
(Max).
3
ClockWorksTM
SY100EL15L
Micrel
T
A
= 40
C
T
A
= 0
C
T
A
= +25
C
T
A
= +85
C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Typ.
Max.
Min.
Max.
Unit
t
PLH
Propagation Delay
ps
t
PHL
CLK to Q (Diff)
460
660
470
670
470
--
670
500
700
CLK to Q (SE)
410
710
420
720
420
--
720
450
750
SCLK to Q
410
710
420
720
420
--
720
470
750
t
skew
Part-to-Part Skew
(1)
--
200
--
200
--
--
200
--
200
ps
Within-Device Skew
--
50
--
50
--
--
50
--
50
t
S
Setup Time EN
150
--
150
--
150
--
--
150
--
ps
t
H
Hold Time EN
400
--
400
--
400
--
--
400
--
ps
V
PP
Minimum Input Swing
CLK
250
--
250
--
250
--
--
250
--
mV
V
CMR
Common Mode Range
(2)
mV
V
PP
< 500mV
2.0
0.4
2.1
0.4
2.1
--
0.4
2.1
0.4
V
PP
500mV
1.8
0.4
1.9
0.4
1.9
--
0.4
1.9
0.4
t
r
Output Rise/Fall TimesQ
375
625
325
575
325
--
575
325
575
ps
t
f
(20% 80%)
AC ELECTRICAL CHARACTERISTICS
V
EE
= 3.3V
10%; V
CC
= GND
(1)
NOTES:
1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions.
2. V
CMR
is referenced to the most positive side of the differential input signal. Normal operation is obtained when the input signals are within the V
CMR
range
and the input swing is greater than V
PP
(Min.) and <1V. The lower end of the V
CMR
range varies 1:1 with V
EE
. The numbers in the spec table assume a
nominal V
EE
= 3.3V. Note for PECL operation, the V
CMR
(Min) will be fixed at 3.3V |V
CMR
(Min)|.
PRODUCT ORDERING CODE
Ordering
Package
Operating
Code
Type
Range
SY100EL15LZC
Z16-2
Commercial
SY100EL15LZCTR
Z16-2
Commercial
4
ClockWorksTM
SY100EL15L
Micrel
16 LEAD PLASTIC SOIC .150" WIDE (Z16-2)
MICREL-SYNERGY
3250 SCOTT BOULEVARD
SANTA CLARA
CA 95054
USA
TEL
+ 1 (408) 980-9191
FAX
+ 1 (408) 914-7878
WEB
http://www.synergysemi.com http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
1999 Micrel Incorporated
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