Электронный компонент: MCP3008

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2002 Microchip Technology Inc.

DS21295B-page 1

M

MCP3004/3008

Features

� 10-bit resolution
� � 1 LSB max DNL
� � 1 LSB max INL
� 4 (MCP3004) or 8 (MCP3008) input channels
� Analog inputs programmable as single-ended or

pseudo-differential pairs

� On-chip sample and hold
� SPI serial interface (modes 0,0 and 1,1)
� Single supply operation: 2.7V - 5.5V
� 200 ksps max. sampling rate at V

DD

= 5V

� 75 ksps max. sampling rate at V

DD

= 2.7V

� Low power CMOS technology
� 5 nA typical standby current, 2 �A max.
� 500 �A max. active current at 5V
� Industrial temp range: -40�C to +85�C
� Available in PDIP, SOIC and TSSOP packages

Applications

� Sensor Interface
� Process Control
� Data Acquisition
� Battery Operated Systems

Package Types

Description

The Microchip Technology Inc. MCP3004/3008
devices are successive approximation 10-bit Analog-
to-Digital (A/D) converters with on-board sample and
hold circuitry. The MCP3004 is programmable to pro-
vide two pseudo-differential input pairs or four single-
ended inputs. The MCP3008 is programmable to pro-
vide four pseudo-differential input pairs or eight single-
ended inputs. Differential Nonlinearity (DNL) and Inte-
gral Nonlinearity (INL) are specified at �1 LSB. Com-
munication with the devices is accomplished using a
simple serial interface compatible with the SPI protocol.
The devices are capable of conversion rates of up to
200 ksps. The MCP3004/3008 devices operate over a
broad voltage range (2.7V - 5.5V). Low current design
permits operation with typical standby currents of only
5 nA and typical active currents of 320 �A. The
MCP3004 is offered in 14-pin PDIP, 150 mil SOIC and
TSSOP packages, while the MCP3008 is offered in 16-
pin PDIP and SOIC packages.

Functional Block Diagram

V

DD

CLK
D

OUT

M

C

P3
004

1
2
3
4

14
13
12

11

10

9
8

5
6
7

V

REF

D

IN

CH0
CH1
CH2
CH3

CS/SHDN

DGND

AGND

NC

V

DD

CLK
D

OUT

M

C

P3008

1
2
3
4

16
15
14
13
12
11
10

9

5
6
7
8

V

REF

D

IN

CS/SHDN
DGND

CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7

NC

AGND

PDIP, SOIC, TSSOP

PDIP, SOIC

Comparator

Sample

and

Hold

10-Bit SAR

DAC

Control Logic

CS/SHDN

V

REF

V

SS

V

DD

CLK

D

OUT

Shift

Register

CH0

Channel

Max

Input

CH1

CH7*

* Note: Channels 4-7 available on MCP3008 Only

D

IN

2.7V 4-Channel/8-Channel 10-Bit A/D Converters

with SPITM Serial Interface

MCP3004/3008

DS21295B-page 2

2002 Microchip Technology Inc.

1.0

ELECTRICAL
CHARACTERISTICS

Absolute Maximum Ratings*

V

DD

........................................................................7.0V

All inputs and outputs w.r.t. V

SS

.....-0.6V to V

DD

+0.6V

Storage temperature ..........................-65�C to +150�C
Ambient temp. with power applied .....-65�C to +125�C
Soldering temperature of leads (10 seconds) .. +300�C
ESD protection on all pins ..................................> 4 kV

*Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.

PIN FUNCTION TABLE

Name

Function

V

DD

+2.7V to 5.5V Power Supply

DGND

Digital Ground

AGND

Analog Ground

CH0-CH7

Analog Inputs

CLK

Serial Clock

D

IN

Serial Data In

D

OUT

Serial Data Out

CS/SHDN

Chip Select/Shutdown Input

V

REF

Reference Voltage Input

ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise noted, all parameters apply at V

DD

= 5V, V

REF

= 5V,

T

AMB

= -40�C to +85�C, f

SAMPLE

= 200 ksps and f

CLK

= 18*f

SAMPLE

. Unless otherwise noted, typical values apply for

V

DD

= 5V, T

AMB

= 25�C.

Parameter

Sym

Min

Typ

Max

Units

Conditions

Conversion Rate
Conversion Time

t

CONV

--

--

10

clock

cycles

Analog Input Sample Time

t

SAMPLE

1.5

clock

cycles

Throughput Rate

f

SAMPLE

--

--

200

75

ksps
ksps

V

DD

= V

REF

= 5V

V

DD

= V

REF

= 2.7V

DC Accuracy
Resolution

10

bits

Integral Nonlinearity

INL

--

�0.5

�1

LSB

Differential Nonlinearity

DNL

--

�0.25

�1

LSB

No missing codes over

temperature

Offset Error

--

--

�1.5

LSB

Gain Error

--

--

�1.0

LSB

Dynamic Performance
Total Harmonic Distortion

--

-76

dB

V

IN

= 0.1V to 4.9V@1 kHz

Signal to Noise and Distortion

(SINAD)

--

61

dB

V

IN

= 0.1V to 4.9V@1 kHz

Spurious Free Dynamic Range

--

78

dB

V

IN

= 0.1V to 4.9V@1 kHz

Reference Input
Voltage Range

0.25

--

V

DD

V

Note 2

Current Drain

--

100

0.001

150

3

�A
�A

CS = V

DD

= 5V

Note 1: This parameter is established by characterization and not 100% tested.

2: See graphs that relate linearity performance to V

REF

levels.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures. See Section 6.2, "Maintaining Minimum Clock Speed",
for more information.

2002 Microchip Technology Inc.

DS21295B-page 3

MCP3004/3008

Analog Inputs
Input Voltage Range for CH0 or

CH1 in Single-Ended Mode

V

SS

--

V

REF

V

Input Voltage Range for IN+ in

pseudo-differential mode

IN-

--

V

REF

+IN-

Input Voltage Range for IN- in

pseudo-differential mode

V

SS

-100

--

V

SS

+100

mV

Leakage Current

--

0.001

�1

�A

Switch Resistance

--

1000

--

See Figure 4-1

Sample Capacitor

--

20

--

pF

See Figure 4-1

Digital Input/Output
Data Coding Format

Straight Binary

High Level Input Voltage

V

IH

0.7 V

DD

--

--

V

Low Level Input Voltage

V

IL

--

0.3 V

DD

V

High Level Output Voltage

V

OH

4.1

--

--

V

I

OH

= -1 mA, V

DD

= 4.5V

Low Level Output Voltage

V

OL

--

--

0.4

V

I

OL

= 1 mA, V

DD

= 4.5V

Input Leakage Current

I

LI

-10

--

10

�A

V

IN

= V

SS

or V

DD

Output Leakage Current

I

LO

-10

--

10

�A

V

OUT

= V

SS

or V

DD

Pin Capacitance

(All Inputs/Outputs)

C

IN

,

C

OUT

--

--

10

pF

V

DD

= 5.0V (Note 1)

T

AMB

= 25�C, f = 1 MHz

Timing Parameters
Clock Frequency

f

CLK

--

--

3.6

1.35

MHz
MHz

V

DD

= 5V (Note 3)

V

DD

= 2.7V (Note 3)

Clock High Time

t

HI

125

--

--

ns

Clock Low Time

t

LO

125

--

--

ns

CS Fall To First Rising CLK Edge

t

SUCS

100

--

--

ns

CS Fall To Falling CLK Edge

t

CSD

--

--

0

ns

Data Input Setup Time

t

SU

--

--

50

ns

Data Input Hold Time

t

HD

--

--

50

ns

CLK Fall To Output Data Valid

t

DO

--

--

125
200

ns
ns

V

DD

= 5V, See Figure 1-2

V

DD

= 2.7V, See Figure 1-2

CLK Fall To Output Enable

t

EN

--

--

125
200

ns
ns

V

DD

= 5V, See Figure 1-2

V

DD

= 2.7V, See Figure 1-2

CS Rise To Output Disable

t

DIS

--

--

100

ns

See Test Circuits, Figure 1-2

CS Disable Time

t

CSH

270

--

--

ns

D

OUT

Rise Time

t

R

--

--

100

ns

See Test Circuits, Figure 1-2

(Note 1)

D

OUT

Fall Time

t

F

--

--

100

ns

See Test Circuits, Figure 1-2

(Note 1)

ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at V

DD

= 5V, V

REF

= 5V,

T

AMB

= -40�C to +85�C, f

SAMPLE

= 200 ksps and f

CLK

= 18*f

SAMPLE

. Unless otherwise noted, typical values apply for

V

DD

= 5V, T

AMB

= 25�C.

Parameter

Sym

Min

Typ

Max

Units

Conditions

Note 1: This parameter is established by characterization and not 100% tested.

2: See graphs that relate linearity performance to V

REF

levels.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures. See Section 6.2, "Maintaining Minimum Clock Speed",
for more information.

MCP3004/3008

DS21295B-page 4

2002 Microchip Technology Inc.

FIGURE 1-1:

Serial Interface Timing.

Power Requirements
Operating Voltage

V

DD

2.7

--

5.5

V

Operating Current

I

DD

--

425
225

550

�A

V

DD

= V

REF

= 5V,

D

OUT

unloaded

V

DD

= V

REF

= 2.7V,

D

OUT

unloaded

Standby Current

I

DDS

--

0.005

2

�A

CS = V

DD

= 5.0V

Temperature Ranges
Specified Temperature Range

T

A

-40

--

+85

�C

Operating Temperature Range

T

A

-40

--

+85

�C

Storage Temperature Range

T

A

-65

--

+150

�C

Thermal Package Resistance
Thermal Resistance, 14L-PDIP

JA

--

70

--

�C/W

Thermal Resistance, 14L-SOIC

JA

--

108

--

�C/W

Thermal Resistance, 14L-TSSOP

JA

--

100

--

�C/W

Thermal Resistance, 16L-PDIP

JA

--

70

--

�C/W

Thermal Resistance, 16L-SOIC

JA

--

90

--

�C/W

ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at V

DD

= 5V, V

REF

= 5V,

T

AMB

= -40�C to +85�C, f

SAMPLE

= 200 ksps and f

CLK

= 18*f

SAMPLE

. Unless otherwise noted, typical values apply for

V

DD

= 5V, T

AMB

= 25�C.

Parameter

Sym

Min

Typ

Max

Units

Conditions

Note 1: This parameter is established by characterization and not 100% tested.

2: See graphs that relate linearity performance to V

REF

levels.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures. See Section 6.2, "Maintaining Minimum Clock Speed",
for more information.

CS

CLK

D

IN

MSB IN

T

SU

T

HD

T

SUCS

T

CSH

T

HI

T

LO

D

OUT

T

EN

T

DO

T

R

T

F

LSB

MSB OUT

T

DIS

NULL BIT

2002 Microchip Technology Inc.

DS21295B-page 5

MCP3004/3008

FIGURE 1-2:

Load Circuit for t

R

, t

F

, t

DO

.

FIGURE 1-3:

Load circuit for t

DIS

and t

EN

.

Test Point

1.4V

D

OUT

3 k

C

L

= 100 pF

D

OUT

t

R

Voltage Waveforms for t

R

, t

F

CLK

D

OUT

t

DO

Voltage Waveforms for t

DO

t

F

V

OH

V

OL

90%

10%

*

Waveform 1 is for an output with internal
conditions such that the output is high,
unless disabled by the output control.

Waveform 2 is for an output with internal
conditions such that the output is low,
unless disabled by the output control.

Test Point

D

OUT

3 k

100 pF

t

DIS

Waveform 2

t

DIS

Waveform 1

CS

CLK

D

OUT

t

EN

1

2

B9

Voltage Waveforms for t

EN

t

EN

Waveform

V

DD

V

DD

/2

V

SS

3

4

Voltage Waveforms for t

DIS

D

OUT

D

OUT

CS

V

IH

T

DIS

Waveform 1*

Waveform 2

Document Outline

• 1.0 Electrical Characteristics
  • Electrical Specifications
  • Figure 1-1: Serial Interface Timing.
  • Figure 1-2: Load Circuit for tR, tF, tDO.
  • Figure 1-3: Load circuit for tDIS and tEN.
• 2.0 Typical Performance Characteristics
  • Figure 2-1: Integral Nonlinearity (INL) vs. Sample Rate.
  • Figure 2-2: Integral Nonlinearity (INL) vs. VREF.
  • Figure 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).
  • Figure 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V).
  • Figure 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V).
  • Figure 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V).
  • Figure 2-7: Integral Nonlinearity (INL) vs. Temperature.
  • Figure 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.
  • Figure 2-9: Differential Nonlinearity (DNL) vs. VREF.
  • Figure 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V).
  • Figure 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V).
  • Figure 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V).
  • Figure 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).
  • Figure 2-14: Differential Nonlinearity (DNL) vs. Temperature.
  • Figure 2-15: Gain Error vs. VREF.
  • Figure 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V).
  • Figure 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V).
  • Figure 2-18: Offset Error vs. VREF.
  • Figure 2-19: Gain Error vs. Temperature.
  • Figure 2-20: Signal to Noise (SNR) vs. Input Frequency.
  • Figure 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.
  • Figure 2-22: Offset Error vs. Temperature.
  • Figure 2-23: Signal to Noise and Distortion (SINAD) vs. Input Frequency.
  • Figure 2-24: Signal to Noise and Distortion (SINAD) vs. Input Signal Level.
  • Figure 2-25: Effective Number of Bits (ENOB) vs. VREF.
  • Figure 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency.
  • Figure 2-27: Frequency Spectrum of 10kHz Input (Representative Part).
  • Figure 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.
  • Figure 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.
  • Figure 2-30: Frequency Spectrum of 1kHz Input (Representative Part, VDD = 2.7V).
  • Figure 2-31: IDD vs. VDD.
  • Figure 2-32: IDD vs. Clock Frequency.
  • Figure 2-33: IDD vs. Temperature.
  • Figure 2-34: IREF vs. VDD.
  • Figure 2-35: IREF vs. Clock Frequency.
  • Figure 2-36: IREF vs. Temperature.
  • Figure 2-37: IDDS vs. VDD.
  • Figure 2-38: IDDS vs. Temperature.
  • Figure 2-39: Analog Input Leakage Current vs. Temperature.
• 3.0 Pin Descriptions
  • Table 3-1: Pin function Table
  • 3.1 DGND
  • 3.2 AGND
  • 3.3 CH0 - CH7
  • 3.4 Serial Clock (CLK)
  • 3.5 Serial Data Input (DIN)
  • 3.6 Serial Data Output (DOUT)
  • 3.7 Chip Select/Shutdown (CS/SHDN)
• 4.0 Device Operation
  • 4.1 Analog Inputs
  • 4.2 Reference Input
    • Figure 4-1: Analog Input Model.
    • Figure 4-2: Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1LSB dev...
• 5.0 Serial Communication
  • Table 5-1: Configure Bits for the MCP3004
  • Table 5-2: Configure Bits for the MCP3008
  • Figure 5-1: Communication with the MCP3004 or MCP3008.
  • Figure 5-2: Communication with MCP3004 or MCP3008 in LSB First Format.
• 6.0 Applications Information
  • 6.1 Using the MCP3004/3008 with Microcontroller (MCU) SPI Ports
    • Figure 6-1: SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 0,0: SCLK idles low).
    • Figure 6-2: SPI Communication with the MCP3004/3008 using 8-bit segments (Mode 1,1: SCLK idles hi...
  • 6.2 Maintaining Minimum Clock Speed
  • 6.3 Buffering/Filtering the Analog Inputs
    • Figure 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filte...
  • 6.4 Layout Considerations
    • Figure 6-4: VDD traces arranged in a �Star� configuration in order to reduce errors caused by cur...
  • 6.5 Utilizing the Digital and Analog Ground Pins
    • Figure 6-5: Separation of Analog and Digital Ground Pins.
• 7.0 Packaging Information
  • 7.1 Package Marking Information