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DS22004A-page 1

MCP6G01/2/3/4

Features

· 3 Gain Selections:

- +1, +10, +50 V/V

· One Gain Select Input per Amplifier
· Rail-to-Rail Input and Output
· Low Gain Error: ±1% (max.)
· High Bandwidth: 250 kHz to 900 kHz (typ.)
· Low Supply Current: 110 µA (typ.)
· Single Supply: 1.8V to 5.5V
· Extended Temperature Range: -40°C to +125°C

Typical Applications

· A/D Converter Driver
· Industrial Instrumentation
· Bar Code Readers
· Metering
· Digital Cameras

Block Diagram

Description

The Microchip Technology Inc. MCP6G01/2/3/4 are
analog Selectable Gain Amplifiers (SGA). They can be
configured for gains of +1 V/V, +10 V/V, and +50 V/V
through the Gain Select input pin(s). The Chip Select
pin on the MCP6G03 can put it into shutdown to
conserve power. These SGAs are optimized for single
supply applications requiring reasonable quiescent
current and speed.
The single amplifier MCP6G01 and MCP6G03, and the
dual amplifier MCP6G02, are available in 8-pin SOIC
and MSOP packages. The quad amplifier MCP6G04 is
available in 14-pin SOIC and TSSOP packages. All
parts are fully specified from -40°C to +125°C.

Package Types

OUT

GSEL

Gain Select

Logic

Gain

Switches

Resistor Lad

der

LA
D

)

Gain
(V/V)

GSEL Voltage (Typ.)

(V)

/2 (or open)

Note:

is assumed to be 0V

(MCP6G03

only)

5 M

GSEL

OUT

1
2
3
4

7
6
5

GSEL

OUTA

INA

GSEL

INC

1
2
3
4

14
13
12
11 V

OUTC

GSEL

5
6
7

9
8

GSEL

OUTD

OUTB

IND

INB

MCP6G01

SOIC, MSOP

INA

GSEL

OUTB

1
2
3
4

7
6
5

INB

OUTA

MCP6G02

SOIC, MSOP

MCP6G04

SOIC, TSSOP

GSEL

OUT

1
2
3
4

7
6
5

MCP6G03

SOIC, MSOP

110 µA Selectable Gain Amplifier

MCP6G01/2/3/4

DS22004A-page 2

1.0

ELECTRICAL
CHARACTERISTICS

Absolute Maximum Ratings

........................................................................7.0V

Current at Analog Input Pin (V

)

......................................±2 mA

Analog Input (V

) ..................... V

1.0V to V

+ 1.0V

All other Inputs and Outputs........... V

0.3V to V

+ 0.3V

Output Short Circuit Current...................................continuous
Current at Output and Supply Pins

................................ ±30 mA

Storage Temperature.....................................-65°C to +150°C
Junction Temperature..................................................+150°C
ESD protection on all pins (HBM; MM)

................ 4 kV; 200V

Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
See Section 4.1.4 "Input Voltage and Current Limits".

DC ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V,

= (0.3V)/G, R

= 100 k

to V

/2, GSEL = V

/2, and CS is tied low.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Amplifier Inputs (V

)

Input Offset Voltage

4.5

±1.0

+4.5

G = +1

±1.0

G = +10, +50

Input Offset Voltage Drift

±2

µV/°C

G = +1, T

= -40°C to +125°C

Power Supply Rejection Ratio

PSRR

G = +1 (Note 1)

Input Bias Current

Input Bias Current at

= +85°C

Temperature

1000

5000

= +125°C

Input Impedance

||6

||pF

Amplifier Gain
Nominal Gains

1 to 50

V/V

+1, +10 or +50

DC Gain Error G = +1

0.3

+0.3

OUT

0.3V to V

- 0.3V

+10

1.0

+1.0

OUT

0.3V to V

- 0.3V

DC Gain Drift G = +1

G/T

±1

ppm/°C

= -40°C to +125°C

+10

G/T

±4

ppm/°C

= -40°C to +1285°C

Ladder Resistance (Note 1)
Ladder Resistance

LAD

200

350

500

Ladder Resistance

across Temperature

LAD

1800

ppm/°C

= -40°C to +125°C

Amplifier Output
DC Output Non-linearity G = +1

ONL

0.2

+0.2

% of FSR V

OUT

= 0.3V to V

0.3V,

= 1.8V

ONL

0.1

+0.1

% of FSR V

OUT

= 0.3V to V

0.3V,

= 5.5V

DC Output Non-linearity, G = +10, +50

ONL

0.05

+0.05

% of FSR V

OUT

= 0.3V to V

0.3V

Maximum Output Voltage Swing

, V

+10

G = +1; 0.3V output overdrive

, V

+10

+10; 0.5V output overdrive

Short Circuit Current

±7

= 1.8V

±20

= 5.5V

Note 1:

LAD

Figure 4-1

) connects V

, V

OUT

, and the inverting input of the internal amplifier. Thus, V

is coupled

to the internal amplifier and the PSRR spec describes PSRR+ only. It is recommended that the V

pin be tied directly

to ground to avoid noise problems.

includes current in R

LAD

(typically 0.6 µA at V

OUT

= 0.3V), and excludes digital switching currents.

DS22004A-page 3

MCP6G01/2/3/4

Power Supply
Supply Voltage

1.8

5.5

Quiescent Current per Amplifier

110

170

µA

= 0 (Note 2)

DC ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V,

= (0.3V)/G, R

= 100 k

to V

/2, GSEL = V

/2, and CS is tied low.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Note 1:

LAD

Figure 4-1

) connects V

, V

OUT

, and the inverting input of the internal amplifier. Thus, V

is coupled

to the internal amplifier and the PSRR spec describes PSRR+ only. It is recommended that the V

pin be tied directly

to ground to avoid noise problems.

includes current in R

LAD

(typically 0.6 µA at V

OUT

= 0.3V), and excludes digital switching currents.

AC ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V,

= (0.3V)/G, R

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Frequency Response
-3dB Bandwidth

900

kHz

G = +1, V

OUT

< 100 mV

P-P

(Note 1)

350

kHz

G = +10, V

OUT

< 100 mV

P-P

(Note 1)

250

kHz

G = +50, V

OUT

< 100 mV

P-P

(Note 1)

Gain Peaking

GPK

0.3

G = +1; V

OUT

< 100 mV

P-P

GPK

G = +10, V

OUT

< 100 mV

P-P

GPK

0.7

G = +50; V

OUT

< 100 mV

P-P

Total Harmonic Distortion plus Noise
f = 1 kHz, G = +1 V/V

THD+N

0.0029

OUT

= 1.75V ± 1.4V

, V

= 5.0V,

BW = 80 kHz

f = 1 kHz, G = +10 V/V

THD+N

0.18

OUT

= 2.5V ± 1.4V

, V

= 5.0V,

BW = 80 kHz

f = 1 kHz, G = +50 V/V

THD+N

1.3

OUT

= 2.5V ± 1.4V

, V

= 5.0V,

BW = 80 kHz

Step Response
Slew Rate

0.50

V/µs

G = 1

2.3

V/µs

G = 10

4.5

V/µs

G = 50

Noise
Input Noise Voltage

µV

P-P

f = 0.1 Hz to 10 Hz (Note 2)

µV

P-P

f = 0.1 Hz to 30 kHz (Note 2)

Input Noise Voltage Density

nV/

Hz G = +1 V/V, f = 10 kHz (Note 2)

nV/

Hz G = +10 V/V, f = 10 kHz (Note 2)

nV/

Hz G = +50 V/V, f = 10 kHz (Note 2)

Input Noise Current Density

fA/

Hz f = 10 kHz

Note 1:

See

Table 4-1

for a list of typical numbers and

Figure 2-31

for the frequency response versus gain.

and e

include ladder resistance thermal noise.

MCP6G01/2/3/4

DS22004A-page 4

DIGITAL ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T

= 25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

Parameters

Sym

Min

Typ

Max

Units

Conditions

CS Low Specifications

CS Logic Threshold, Low

CSL

0.2V

CS = 0V

CS Input Current, Low

CSL

CS = 0V

CS High Specifications

CS Logic Threshold, High

CSH

0.8V

CS = V

CS Input Current, High

CSH

0.8

µA

CS = V

= 5.5V

Quiescent Current per Amplifier,
Shutdown Mode (I

)

DD_SHDN

120

CS = V

, MCP6G03

Quiescent Current per Amplifier,
Shutdown Mode (I

) (Note 3)

SS_SHDN

2.4

µA

CS = V

= 1.8V, MCP6G03

SS_SHDN

7.2

µA

CS = V

= 5.5V, MCP6G03

CS Dynamic Specifications

Input Capacitance

Input Rise/Fall Times

CSRF

µs

(Note 2)

CS Low to Amplifier Output High
Turn-on Time

CSON

µs

G = +1 V/V, V

= 1.8V, V

= 0.9V

CS = 0.2V

to V

OUT

= 0.8V

CSON

µs

G = +1 V/V, V

= 5.5V, V

= 0.9V

CS = 0.2V

to V

OUT

= 0.8V

CS High to Amplifier Output High-Z
Turn-off Time

CSOFF

µs

G = +1 V/V, V

= V

/2,

CS = 0.8V

to V

OUT

= 0.1V

Hysteresis

CSHY

0.40

= 1.8V

CSHY

0.55

= 5.5V

GSEL Specifications (Note 1)

GSEL Logic Threshold, Low

GSL

0.15V

0.35V

Gain changes between 1 and 10,
I

GSEL

= 0

GSEL Logic Threshold, High

GSH

0.65V

0.85V

Gain changes between 1 and 50,
I

GSEL

= 0

GSEL Input Current, Low

GSL

1.5

µA

GSEL voltage = 0.3V

GSEL Input Current, High

GSH

+1.5

+10

µA

GSEL voltage = 0.7V

GSEL Dynamic Specifications (Note 1)

Input Capacitance

GSEL

Input Rise/Fall Times

GSRF

µs

(Note 2)

Hysteresis

GSHY

= 1.8V

GSHY

= 5.5V

GSEL Low to Valid Output Time,

G = +1 to +10 Select

GSL1

µs

= 150 mV,

GSEL = 0.25V

to V

OUT

= 1.37V

GSEL Middle to Valid Output Time,

G = +10 to +1 Select

GSM10

µs

= 150 mV,

GSEL = 0.25V

to V

OUT

= 0.28V

GSEL High to Valid Output Time,

G = +1 to +50 Select

GSH1

µs

= 30 mV,

GSEL = 0.75V

to V

OUT

= 1.35V

GSEL Middle to Valid Output Time,

G = +50 to +1 Select

GSM50

µs

= 30 mV,

GSEL = 0.75V

to V

OUT

= 0.18V

Note 1:

GSEL is a tri-level input pin. The gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high.

Not tested in production. Set by design and characterization.

SS_SHDN

includes the current through the CS pin, R

and R

LAD

, and excludes digital switching currents. The block dia-

gram on the from page shows these current paths (through V

DS22004A-page 5

MCP6G01/2/3/4

FIGURE 1-1:

Gain Select Timing Diagram.

GSEL High to Valid Output Time,

G = +10 to +50 Select

GSH10

µs

= 30 mV,

GSEL = 0.75V

to V

OUT

= 1.38V

GSEL Low to Valid Output Time,

G = +50 to +10 Select

GSL50

µs

= 30 mV,

GSEL = 0.25V

to V

OUT

= 0.42V

DIGITAL ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, T

= 25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Note 1:

GSEL is a tri-level input pin. The gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high.

Not tested in production. Set by design and characterization.

SS_SHDN

includes the current through the CS pin, R

and R

LAD

, and excludes digital switching currents. The block dia-

gram on the from page shows these current paths (through V

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V

= +1.8V to +5.5V, and V

= GND.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges
Specified Temperature Range

+125

°C

Operating Temperature Range

+125

°C

(Note 1)

Storage Temperature Range

+150

°C

Thermal Package Resistances
Thermal Resistance, 8L-SOIC

163

°C/W

Thermal Resistance, 8L-MSOP

206

°C/W

Thermal Resistance, 14L-SOIC

120

°C/W

Thermal Resistance, 14L-TSSOP

100

°C/W

Note 1:

The MCP6G01/2/3/4 family of SGAs operates over this temperature range, but operation must not cause T

to exceed

Maximum Junction Temperature (+150°C).

GSEL

OUT

GSL1

0.15V

1.50V

0.150V

0.030V

0.15V

GSM10

0.03V

1.50V

GSH1

0.03V

GSM50

0.30V

1.50V

GSH10

0.30V

GSL50

DS22004A-page 7

MCP6G01/2/3/4

1.1

DC Output Voltage Specs / Model

1.1.1

IDEAL MODEL

The ideal SGA output voltage (V

OUT

) is (see

Figure 1-3

EQUATION 1-1:

This equation holds when there are no gain or offset
errors.

1.1.2

LINEAR MODEL

The SGA's linear region of operation is modeled by the
line V

O_LIN

shown in

Figure 1-3

. V

O_LIN

includes offset

and gain errors, but does not include non-linear effects.

EQUATION 1-2:

This line's endpoints are 0.3V from the supply rails
(V

O_ID

= 0.3V and V

0.3V). The gain error and

input offset voltage specifications (in the electrical
specifications) relate to

Figure 1-3

as follows:

EQUATION 1-3:

The input offset specification describes V

G = +1 V/V.

The DC Gain Drift (

G/T

) can be calculated from the

change in g

across temperature. This is shown in the

following equation:

EQUATION 1-4:

FIGURE 1-3:

Output Voltage Model.

1.1.3

OUTPUT NON-LINEARITY

Figure 1-4

shows the Integral Non-Linearity (INL) of the

output voltage. INL is the output non-linearity error not
explained by V

O_LIN

EQUATION 1-5:

The output non-linearity specification (in the Electrical
Specifications, with units of % of FSR) is related to

Figure 1-4

by:

EQUATION 1-6:

Note that the Full Scale Range (FSR) is V

0.6V

(0.3V to V

0.3V).

Where:

G is the nominal gain

O_ID

REF

O_LIN

G 1 g

(

) V

0.3V

------------ V

0.3V

REF

Where:

G is the nominal gain
g

is the gain error

is the input offset voltage

100%

0.6V

-----------------------------

G 1 g

(

)

-------------------------,

Where:

OUT

O_ID

0.3V

OUT

O_ID

0.3V

----------,

in units of V/V/°C

100%

----------,

in units of %/°C

0.3

-0.3

OUT

(V)

0.3

-0.3 V

LIN

INL

OUT

O_LIN

ONL

100%

max V

(

)

0.6V

-------------------------------

max INL

(

)

Where:

max INL

(

)

DS22004A-page 9

MCP6G01/2/3/4

2.0

TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

FIGURE 2-1:

DC Gain Error, G = +1.

FIGURE 2-2:

DC Gain Error, G

+10.

FIGURE 2-3:

Input Offset Voltage.

FIGURE 2-4:

DC Gain Drift, G = +1.

FIGURE 2-5:

DC Gain Drift, G

+10.

FIGURE 2-6:

Input Offset Voltage Drift.

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

10%

15%

20%

25%

30%

-0

0.0

0.1

0.2

DC Gain Error (%)

Per

cen

t
a
g

e
of

Occ

r
r
en

ces

2460 Samples
G = +1

10%

12%

14%

-0

DC Gain Error (%)

Per

cen

t
a
g

e
of

Occ

r
r
en

ces

4916 Samples
G +10

10%

12%

14%

16%

18%

20%

-4

-3

-2

-1

-0

Input Offset Voltage (mV)

e
rce

f
O

ccu

ces

2460 Samples

G = +50
G = +10
G = +1

10%

12%

14%

16%

18%

-5

-4

-3

-2

-1

DC Gain Drift (ppm/°C)

Perce

of Oc

curre

2459 Samples
G = +1
T

= -40 to +125°C

10%

12%

14%

-1

-8

-6

-4

-2

DC Gain Drift (ppm/°C)

Perce

of Oc

curre

4912 Samples
G +10
T

= -40 to +125°C

10%

12%

14%

16%

18%

20%

22%

-1

-8

-6

-4

-2

Input Offset Voltage Drift (µV/°C)

Per

cen

t
a
g

e
of

rren

c
e

1612 Samples
G = +1, +10, +50
T

= -40 to +125°C

MCP6G01/2/3/4

DS22004A-page 10

Note: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

FIGURE 2-7:

The MCP6G01/2/3/4 family

shows no phase reversal under overdrive.

FIGURE 2-8:

PSRR vs. Temperature.

FIGURE 2-9:

Input Noise Voltage Density

vs. Frequency.

FIGURE 2-10:

Crosstalk vs. Frequency,

with G = 50 (circuit in

Figure 4-7

FIGURE 2-11:

PSRR vs. Frequency.

FIGURE 2-12:

Quiescent Current vs.

Supply Voltage.

-1

0.0E+00

1.0E-03

2.0E-03

3.0E-03

4.0E-03

5.0E-03

6.0E-03

7.0E-03

8.0E-03

9.0E-03

1.0E-02

Time (1 ms/div)

Inpu

tput

Volta

e (V)

= 5.0V

G = +1 V/V

OUT

100

110

120

-50

-25

100

125

Ambient Temperature (°C)

PSRR

(

100

1000

10000

0.1

100

1000 10000 10000

Frequency (Hz)

Input Noise Voltage Density

(nV/

Hz)

10k

100k

100

0.1

G = +1

= +10
= +50

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

1.E+03

1.E+04

1.E+05

Frequency (Hz)

r
os

sta

l
k, Inpu

t R

e
ferre

100k

10k

= 5.0V

G = 50 V/V

= 0

= 1 M

= 100 k

= 10 k

100

1000

10000

100000

Frequency (Hz)

e
r Sup

Reje

ion

Rat

i
o

(dB

)

Input Referred

G = 1

G = 10

G = 50

= 1.8V

= 5.5V

100

10k

100k

100

120

140

160

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

scen

t
C

rren

t
(

)

= +25°C

= 40°C

= +125°C

= +85°C

DS22004A-page 11

MCP6G01/2/3/4

Note: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

FIGURE 2-13:

Quiescent Current (I

) in

Shutdown Mode vs. Supply Voltage.

FIGURE 2-14:

Input Bias Current vs.

Temperature.

FIGURE 2-15:

Input Bias Current vs. Input

Voltage.

FIGURE 2-16:

Quiescent Current (I

) in

Shutdown Mode vs. Temperature.

FIGURE 2-17:

Input Bias Current vs. Input

Voltage.

FIGURE 2-18:

Output Short Circuit Current

vs. Supply Voltage.

-8

-7

-6

-5

-4

-3

-2

-1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

i
esc

t
C

r
r
en

t
i

utdo

(µA

)

In Shutdown Mode

= V

CS = V

SS_SHDN

100

1,000

105

115

125

Ambient Temperature (°C)

t
Bi

as Cu

r
r
e

= 5.5V

= V

100

1,000

10,000

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Voltage (V)

Input

i
a
s

e
n

t (pA

)

= +85°C

= 5.5V

= +125°C

-9

-8

-7

-6

-5

-4

-3

-2

-1

-50

-25

100

125

Ambient Temperature (°C)

i
esc

t
C

r
r
en

t
i

utdo

(µA

)

In Shutdown Mode
V

= V

= 5.5V

= 1.8V

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0

Input Voltage (V)

I
n

put

e
n

t
Ma

i
t
u

e
(A

)

+125°C

+85°C
+25°C

-40°C

10m

100µ

10µ

1µ

100n

10n

100p

10p

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Outp

ut S

hort Ci

rcu

i
t Cu

rre

gnitude

(mA)

= 40°C

= +25°C

= +85°C

= +125°C

MCP6G01/2/3/4

DS22004A-page 12

Note: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

FIGURE 2-19:

Output Voltage Error vs.

Ideal Output Voltage, with V

= 1.8V.

FIGURE 2-20:

Output Voltage Headroom

vs. Output plus Ladder Current (circuit in

Figure 4-4

FIGURE 2-21:

Output Impedance vs.

Frequency.

FIGURE 2-22:

Output Voltage Error vs.

Ideal Output Voltage, with V

= 5.5V.

FIGURE 2-23:

Output Voltage Headroom

vs. Temperature.

FIGURE 2-24:

Ladder Resistance Drift.

-3

-2

-1

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

Ideal Output Voltage; GV

(V)

Outpu

t

Error,

put Referr

ed;

(mV

)

= +1.8V

Representative Part

G = +1

G = +10
G = +50

100

1000

0.01

0.1

Output Current Magnitude (mA)

t
p

Vol

t
ag

ead

;

nd V

 V

(mV

)

= +5.5V

 V

= +1.8V

 V

1.E+02

1.E+03

1.E+04

1.E+05

1.E+04

1.E+05

1.E+06

1.E+07

Frequency (Hz)

Output Impedance Magnitude

(

)

G = 50

= 10
= 1

100

100k

10k

100k

10k

10M

-3

-2

-1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Ideal Output Voltage; GV

(V)

Outpu

t

Error,

put Referr

ed;

(mV

)

= +5.5V

Representative Part

G = +1

G = +10
G = +50

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-50

-25

100

125

Ambient Temperature (°C)

t
p

Vol

t
ag

ead

;

nd V

= 5.5V: V

= 1.8V: V

10%

12%

14%

-2

-1

Ladder Resistance Drift (ppm/°C)

rcen

t
a
g

e
of

Occ

r
r
en

1228 Samples
T

= -40 to +125°C

DS22004A-page 13

MCP6G01/2/3/4

Note: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

FIGURE 2-25:

Slew Rate vs. Temperature,

with G = +1.

FIGURE 2-26:

Slew Rate vs. Temperature,

with G = +10.

FIGURE 2-27:

Bandwidth vs. Resistive

Load.

FIGURE 2-28:

Output Voltage Swing vs.

Frequency.

FIGURE 2-29:

Slew Rate vs. Temperature,

with G = +50.

FIGURE 2-30:

Bandwidth vs. Capacitive

Load.

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

-50

-25

100

125

Ambient Temperature (°C)

l
ew

t
e

/µ

G = +1 V/V

Falling Edge

Rising Edge

= 1.8V

= 5.5V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

-50

-25

100

125

Ambient Temperature (°C)

Slew

a
t
e

(V/

G = +10 V/V

Falling Edge

Rising Edge

= 5.5V

1.E+04

1.E+05

1.E+06

1.E+02

1.E+03

1.E+04

1.E+05

Resistive Load ( )

Bandwidth (Hz)

G = +1

G = +10
G = +50

10k

100k

10k

100k

100

0.1

1.E+03

1.E+04

1.E+05

1.E+06

Frequency (Hz)

t
p

t
Vo

e Swi

g (

P-

)

= 1.8V

= 5.5V

G = +1
G = +10
G = +50

100k

10k

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-50

-25

100

125

Ambient Temperature (°C)

Slew

a
t
e

(V/

G = +50 V/V

Falling Edge

Rising Edge

= 5.5V

1.E+05

1.E+06

100

1000

Capacitive Load (pF)

ndwid

th (Hz)

100k

G = +10

G = +50

G = +1

MCP6G01/2/3/4

DS22004A-page 14

Note: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

FIGURE 2-31:

Gain vs. Frequency.

FIGURE 2-32:

Small Signal Pulse

Response.

FIGURE 2-33:

THD plus Noise vs.

Frequency, V

OUT

= 2.8 V

P-P

FIGURE 2-34:

Gain Peaking vs. Capacitive

Load.

FIGURE 2-35:

Large Signal Pulse

Response.

FIGURE 2-36:

THD plus Noise vs.

Frequency, V

OUT

= 4.0 V

P-P

-40

-30

-20

-10

1.E+04

1.E+05

1.E+06

1.E+07

Frequency (Hz)

G = +1

100k

10M

10k

G = +50

G = +10

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

45.00

50.00

Time (5 µs/div)

t
put Volta

0 mV

/di

v
)

rmal

ized

e (1

00 mV/

i
v
)

= +5.0V

OUT

G = +50
G = +10
G = +1

0.001

0.01

0.1

1.E+02

1.E+03

1.E+04

1.E+05

Frequency (Hz)

HD +

i
se (

)

Measurement BW = 80 kHz

100

100k

10k

G = +10

G = +1

G = +50

OUT

= 2.8V

P-P

= 5.0V

100

1000

Capacitive Load (pF)

a
in

Peak

(
d

G = +1

G = +10
G = +50

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

45.00

50.00

Time (5 µs/div)

ali

z
ed

t
Vo

ut V

e (V

)

= +5.0V

OUT

G = +1
G = +10
G = +50

0.001

0.01

0.1

1.E+02

1.E+03

1.E+04

1.E+05

Frequency (Hz)

D +

i
se (

)

OUT

= 4 V

P-P

= 5.0V

100

100k

10k

G = +10

G = +1

G = +50

Measurement BW = 80 kHz

DS22004A-page 15

MCP6G01/2/3/4

Note: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

FIGURE 2-37:

THD plus Noise vs. Supply

Voltage.

FIGURE 2-38:

THD plus Noise vs. Output

Swing.

FIGURE 2-39:

Gain Select Timing, with

Gain = 1 and 10.

FIGURE 2-40:

THD plus Noise vs. Load

Resistance.

FIGURE 2-41:

Gain Select Timing, with

Gain = 1 and 50.

FIGURE 2-42:

Gain Select Timing, with

Gain = 1 and 10.

0.001

0.01

0.1

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Power Supply Voltage (V)

D + Noise

(%)

G = +1

G = +10

G = +50

OUT

= 0.8V

f = 1 kHz
Measurement BW = 80 kHz

0.001

0.01

0.1

Output Swing (V

P-P

)

D + No

i
se (%

)

G = +1

G = +10

G = +50

Measurement BW = 80 kHz

= 5.0V

f = 1 kHz

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

100

Time (10 µs/div)

t
p

t
Vo

e (

)

-40

-35

-30

-25

-20

-15

-10

-5

a
in S

e
le

Volt

(

)

GSEL

(G = +1)

(G = +10)

= 5.0V

= 0.15V

OUT

0.001

0.01

0.1

1.E+03

1.E+04

1.E+05

1.E+06

Load Resistance ()

D + Nois

e (%)

G = +1

G = +10

G = +50

f = 1 kHz
V

= 5.0V

10k

100k

Measurement BW = 80 kHz

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

100

Time (10 µs/div)

t
Vo

(
V

)

-40

-35

-30

-25

-20

-15

-10

-5

a
in S

e
le

Volt

(

)

GSEL

(G = +1)

(G = +50)

(G = +1)

= 5.0V

= 0.030V

OUT

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

100

Time (10 µs/div)

t
p

t
Vo

e (V

)

-40

-35

-30

-25

-20

-15

-10

-5

lec

t
Volt

age (

)

GSEL

(G = +10)

(G = +50)

(G = +10)

= 5.0V

= 0.030V

OUT

MCP6G01/2/3/4

DS22004A-page 16

Note: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

FIGURE 2-43:

Output Voltage vs. Chip

Select, with V

= 1.8V.

FIGURE 2-44:

GSEL Pin Current vs. GSEL

Voltage, with V

= 1.8V.

FIGURE 2-45:

GSEL Current, with GSEL

Voltage of 0.3V

FIGURE 2-46:

Output Voltage vs. Chip

Select, with V

= 5.0V.

FIGURE 2-47:

GSEL Pin Current vs. GSEL

Voltage, with V

= 5.5V.

FIGURE 2-48:

GSEL Current, with GSEL

Voltage of 0.7V

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Time (20 µs/div)

Outp

ut V

age

(mV)

e
le

l
t
a
g

e
(V

)

1.8
0

OUT

is "ON"

= 1.8V

= 0.9V

Shutdown

G = 1
G = 10
G = 50

-10

-8

-6

-4

-2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

GSEL Voltage (V)

rre

t (µA

)

= +25°C

= +85°C
= +125°C

= 1.8V

= +125°C

= +85°C
= +25°C

10%

12%

14%

16%

18%

20%

22%

-7

-6

-5

-4

-3

GSEL Current (µA)

Perc

t
a
g

e
o

f
O

ccu

rre

1228 Samples
GSEL = 0.3V

= 1.8V

= 5.5V

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Time (20 µs/div)

Outp

ut V

age

(mV)

e
le

l
t
a
g

e
(V

)

5
0

OUT

is "ON"

= 5.0V

= 0.9V

Shutdown

G = 1
G = 10
G = 50

-10

-8

-6

-4

-2

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

GSEL Voltage (V)

rre

t (µA

)

= 5.5V

= +25°C
= +85°C
= +125°C

= +125°C

= +85°C
= +25°C

10%

12%

14%

16%

18%

20%

GSEL Current (µA)

rcen

t
a
g

e
of

Occ

r
r
en

1228 Samples
GSEL = 0.7V

= 5.5V

= 1.8V

DS22004A-page 17

MCP6G01/2/3/4

Note: Unless otherwise indicated, T

= +25°C, V

= +1.8V to +5.5V, V

= GND, G = +1 V/V, V

= (0.3V)/G,

= 100 k

to V

/2, C

= 60 pF, GSEL = V

/2, and CS is tied low.

FIGURE 2-49:

GSEL Trip Point between

G = +1 and G = +10.

FIGURE 2-50:

GSEL Trip Point between

G = +1 and G = +50.

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

2
1

2
2

2
3

2
4

2
5

Normalized GSEL Trip Point; V

GSEL

rce

t
a

f
O

ccu

rre

ces

1227 Samples
G = +1 to +10

= 1.8V

= 5.5V

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

7
3

7
4

7
5

7
6

7
7

Normalized GSEL Trip Point; V

GSEL

Perc

t
a
g

e
of

Occ

r
r
en

1228 Samples
G = +1 to +50

= 1.8V

= 5.5V

MCP6G01/2/3/4

DS22004A-page 18

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in

Table 3-1

TABLE 3-1:

PIN FUNCTION TABLE

3.1

Analog Output

The output pin (V

OUT

) is a low impedance voltage

source. The selected gain (G) and input voltage (V

)

determine its value.

3.2

Analog Input

The analog inputs (V

) are high impedance CMOS

inputs with low bias currents. Only three fixed, non-
inverting gains are available through these inputs.

3.3

Power Supply (V

and V

)

The Positive Power Supply Pin (V

) is 1.8V to 5.5V

higher than the Negative Power Supply Pin (V

). For

normal operation, the other pins are at voltages
between V

and V

Typically, these parts are used in a single (positive)
supply configuration. In this case, V

is connected to

ground, and V

is connected to the supply. V

will

need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the V

pin. These parts need

to use a bulk capacitor (typically 1.0 µF to 10 µF) within
100 mm of the V

pin; it can be shared with nearby

analog parts.

3.4

Digital Inputs

The Chip Select (CS) input is a Schmitt-triggered,
CMOS logic input.
The Gain Select (GSEL) inputs are tri-level digital
inputs. They function similar to normal logic inputs at
low (G = +10) and high voltages (G = +50). The pin can
also be set to mid-supply (G = +1) by a low impedance
source, or by leaving this pin open.

MCP6G01

MCP6G02

MCP6G03

MCP6G04

Symbol

Description

OUT

, V

OUTA

Analog Output (SGA A)

GSEL, GSEL

Gain Select Input (SGA A)

, V

INA

Analog Input (SGA A)

Positive Power Supply

INB

Analog Input (SGA B)

GSEL

Gain Select Input (SGA B)

OUTB

Analog Output (SGA B)

OUTC

Analog Output (SGA C)

GSEL

Gain Select Input (SGA C)

INC

Analog Input (SGA C)

Negative Power Supply

IND

Analog Input (SGA D)

GSEL

Gain Select Input (SGA D)

OUTD

Analog Output (SGA D)

Chip Select

1, 5, 8

1, 5

No Internal Connection

DS22004A-page 19

MCP6G01/2/3/4

4.0

APPLICATIONS INFORMATION

The MCP6G01/2/3/4 family of Selectable Gain
Amplifiers (SGA) is based on simple analog building
blocks (see

Figure 4-1

). Each of these blocks will be

explained in more detail in the following subsections.

FIGURE 4-1:

SGA Block Diagram.

4.1

Internal Op Amp

The internal op amp gives the right combination of
bandwidth, accuracy, and flexibility.

4.1.1

COMPENSATION CAPACITORS

The internal op amp has three compensation
capacitors (comp. caps.) connected to a switching
network. They are selected to give good small signal
bandwidth at high gains, and good slew rate (full power
bandwidth) at low gains. The change in bandwidth as
gain changes is between 250 and 900 kHz. Refer to

Table 4-1

for more information.

TABLE 4-1:

GAIN VS. INTERNAL
COMPENSATION
CAPACITOR

4.1.2

RAIL-TO-RAIL INPUTS

The input stage of the internal op amp uses two
differential input stages in parallel; one operates at low
V

(input voltage), while the other operates at high V

With this topology, the internal inputs can operate to
0.3V past either supply rail, although the output will clip
the signal before that happens.
The transition between the two input stage occurs
when V

1.1V (see

Figure 2-19

and

Figure 2-

). For the best distortion and gain linearity, avoid this

region of operation.

4.1.3

PHASE REVERSAL

The MCP6G01/2/3/4 amplifier family is designed with
CMOS input devices. It is designed to not exhibit phase
inversion when the input pins exceed the supply
voltages.

Figure 2-7

shows an input voltage exceeding

both supplies with no resulting phase inversion.

4.1.4

INPUT VOLTAGE AND CURRENT
LIMITS

The ESD protection on the inputs can be depicted as
shown in

Figure 4-2

. This structure was chosen to

protect the input transistors, and to minimize input bias
current (I

). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below
V

. They also clamp any voltages that go too far

above V

; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass ESD
events within the specified limits.

Gain
(V/V)

GSEL Voltage (Typ.)

(V)

/2 (or open)

Note:

is assumed to be 0V

OUT

GSEL

Gain Select

Logic

Gain

Switches

Re
sisto

r
L

adde

LAD

)

(MCP6G03

only)

5 M

Gain
(V/V)

Internal

Comp.

Cap.

G x BW

(MHz)

Typ.

(V/µs)

Typ.

FPBW

(kHz)

Typ.

(kHz)

Typ.

Large

0.90

0.50

900

Medium

3.5

2.3

133

350

Small

12.5

4.5

260

250

Note 1:

Changing the compensation capacitor does not
change the DC performance (e.g., V

G x BW is approximately the Gain Bandwidth
Product of the internal op amp.

FPBW is the Full Power Bandwidth at
V

= 5.5V, which is based on slew rate (SR).

BW is the closed-loop, small signal 3 dB
bandwidth.

MCP6G01/2/3/4

DS22004A-page 20

FIGURE 4-2:

Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the V

pins (see Section

"Absolute Maximum Ratings " at the beginning of
Section 1.0 "Electrical Characteristics").

Figure 4-3

shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(V

) from going too far below ground, and the resistor

limits the possible current drawn out of the input pin.

Diode D

prevents the input pin (V

) from going too far

above V

. When implemented as shown, resistor R

also limits the current through D

FIGURE 4-3:

Protecting the Analog

Inputs.

It is also possible to connect the diode to the left of the
resistor R

. In this case, the current through the diode

needs to be limited by some other mechanism. The

resistor then serves as in-rush current limiter; the DC
current into the input pin (V

) should be very small.

A significant amount of current can flow out of the
inputs when the common mode voltage (V

) is below

ground (V

); see

Figure 2-17

. Applications that are

high impedance may need to limit the useable voltage
range.

4.1.5

RAIL-TO-RAIL OUTPUT

The maximum output voltage swing is the maximum
swing possible under a particular amplifier load current.
The amplifier load current is the sum of the external
load current (I

OUT

) and the current through the ladder

resistance (I

LAD

); see

Figure 4-4

EQUATION 4-1:

FIGURE 4-4:

Amplifier Load Current.

See

Figure 2-20

for the typical output headroom

or V

) as a function of amplifier

load current.The specification table states the output
can reach within 10 mV of either supply rail when
R

= 100 k

4.2

Resistor Ladder

The resistor ladder shown in

Figure 4-1

LAD

= R

+ R

) sets the gain. Placing the gain

switches in series with the inverting input reduces the
parasitic capacitance, distortion, and gain mismatch.
R

LAD

is an additional load on the output of the SGA and

causes additional current draw from the supplies.
When CS is high, the SGA is shut down (low power).
R

LAD

is still attached to the V

OUT

and V

pins. Thus,

these pins and the internal amplifier's inverting input
are all connected through R

LAD

and the output is not

high-Z (unlike the internal op amp).
R

LAD

contributes to the output noise; see

Figure 2-9

LAD

is intended to be driven at the V

pin by a low

impedance voltage source. The power supply driving
the V

pin should have an output impedance less than

0.1

to maintain reasonable gain accuracy.

Bond

Pad

Bond

Pad

Bond

Pad

to the rest of

Input

Stage

the amplifier

MCP6G0X

(minimum expected V

)

2 mA

OUT

Where:

Amplifier Load Current

OUT

LAD

OUT

(

)

LAD

---------------------------------

OUT

LAD

OUT

LAD

MCP6G0X

DS22004A-page 21

MCP6G01/2/3/4

4.3

MCP6G03 Chip Select (CS)

The MCP6G03 is a single amplifier with chip select
(CS). When CS is high, the internal op amp is shut
down and its output placed in a high-Z state. The
resistive ladder is always connected between V

and

OUT

; even in shutdown. This means that the output

resistance will be 350 k

(typ.), with a path for output

signals to appear at the input. The supply current at
V

includes the current through the load resistor and

ladder resistors; it also includes current from the CS pin
to V

. When CS is low, the amplifier is enabled. If CS

is left floating, the amplifier may not operate properly.

Figure 1-2

and

Figure 2-43

show how the output

voltage and supply current response to a CS pulse.

4.4

Gain Select (GSEL)

The amplifier can be set to the gains +1 V/V, +10 V/V,
and +50 V/V using one input pin (GSEL). At the same
time, different compensation capacitors are selected to
optimize the bandwidth vs. slew rate trade-off (see

Table 4-1

Table 4-2

shows how to change the gain

using a GPIO pin on a microcontroller and

Table 4-3

shows how to hard wire the gain (i.e., using PCB
wiring).

TABLE 4-2:

MCU DRIVEN GAIN
SELECTION

TABLE 4-3:

HARD WIRED GAIN
SELECTION

4.5

Capacitive Load and Stability

Large capacitive loads can cause stability problems
and reduced bandwidth for the MCP6G01/2/3/4 family
of SGAs (

Figure 2-30

and

Figure 2-34

). As the load

capacitance increases, there is a corresponding
increase in frequency response peaking and step
response overshoot and ringing. This happens
because a large load capacitance decreases the
internal amplifier's phase margin and bandwidth.
When driving large capacitive loads with these SGAs
(i.e., > 60 pF), a small series resistor at the output
(R

ISO

Figure 4-5

) improves the internal amplifier's

stability by making the load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.

FIGURE 4-5:

SGA Circuit for Large

Capacitive Loads.

Figure 4-6

gives recommended R

ISO

values for

different capacitive loads. After selecting R

ISO

for your

circuit, double check the resulting frequency response
peaking and step response overshoot on the bench.
Modify R

ISO

's value until the response is reasonable at

all gains.

FIGURE 4-6:

Recommended R

ISO

Gain

MCU Pin's State

+1 V/V

Output PIC's V

REF

at V

Digital Output High-Z (Notes 1)
Output V

/2 PWM signal (Notes 2)

+10 V/V

Digital Output driven Low

+50 V/V

Digital Output driven High

Note 1: See Section 4.8.1 "Driving the Gain

Select Pin with a Microcontroller GPIO
Pin".

2: See Section 4.8.2 "Driving the Gain

Select Pin with a PWM Signal"

Selected Gain

Possible GSEL Drivers

+1 V/V

Open Circuit (Note 1)
Low impedance source at V

+10 V/V

Tied to GND (0V)

+50 V/V

Tied to V

Note 1: The GSEL pin floats to mid-supply

/2); a bypass capacitor may be

needed.

OUT

MCP6G0X

ISO

100

1,000

100

1,000

10,000

100,000

Load Capacitance (F)

Recommended R

ISO

(

)

10p

100p

100n

For all gains

10n

MCP6G01/2/3/4

DS22004A-page 22

4.6

Layout Considerations

Good PC board layout techniques will help achieve the
performance shown in Section 1.0 "Electrical
Characteristics" and Section 2.0 "Typical
Performance Curves". It will also help minimize
Electromagnetic Compatibility (EMC) issues.
Because the MCP6G01/2/3/4 SGAs' frequency
response reaches unity gain at 10 MHz when G = 50, it
is important to use good PCB layout techniques. Any
parasitic coupling at high frequency might cause
undesired peaking. Filtering high frequency signals
(i.e., fast edge rates) can help.

4.6.1

COMPONENT PLACEMENT

Separate different circuit functions: digital from analog,
low speed from high speed, and low power from high
power. This will reduce crosstalk.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.

4.6.2

SUPPLY BYPASS

Use a local bypass capacitor (0.01 µF to 0.1 µF) within
2 mm of the V

pin for good, high frequency

performance. It must connect directly to ground.
Use a bulk bypass capacitor (i.e., 1.0 µF to 10 µF)
within 100 mm of the V

pin. It needs to connect to

ground, and provides large, slow currents. This
capacitor may be shared with other nearby analog
parts.
Ground plane is important, and power plane(s) can
also be of great help. High frequency (e.g., multi-layer
ceramic capacitors), surface mount components
improve the supply's performance.

4.6.3

INPUT SOURCE IMPEDANCE

The sources driving the inputs of the SGAs need to
have reasonably low source impedance at higher
frequencies.

Figure 4-7

shows how the external source

resistance (R

), SGA package pin capacitance (C

and SGA package pin-to-pin capacitance (C

) form a

positive feedback voltage divider network. Feedback
may cause frequency response peaking and step
response overshoot and ringing.

FIGURE 4-7:

Positive Feedback Path.

Figure 2-10

shows the crosstalk (referred to input) that

results when a hostile signal is connected to the other
inputs (e.g., V

INB

through V

IND

), and the input of

interest (e.g., V

INA

) has R

connected to GND. A gain

of +50 was chosen for this plot because it
demonstrates the worst-case behavior. Increasing R

increases the crosstalk as expected. At a source
impedance of 10 M

, there is noticeable change in

behavior.
Most designs should use a source resistance (R

) no

larger than 10 M

. Careful attention to layout parasitics

and proper component selection will help minimize this
effect. When a source impedance larger than 10 M

must be used, place a capacitor in parallel to C

reduce the positive feedback. This capacitor needs to
be large enough to overcome gain (or crosstalk)
peaking, yet small enough to allow a reasonable signal
bandwidth.

4.6.4

SIGNAL COUPLING

The input pins of the MCP6G01/2/3/4 family of SGAs
are high impedance. This makes them especially
susceptible to capacitively coupled noise. Using a
ground plane helps reduce this problem.
When noise is capacitively coupled, the ground plane
provides additional shunt capacitance to ground. When
noise is magnetically coupled, the ground plane
reduces the mutual inductance between traces.
Increasing the separation between traces makes a
significant difference.
Changing the direction of one of the traces can also
reduce magnetic coupling. It may help to locate guard
traces next to the victim trace. They should be on both
sides of, and as close as possible to, the victim trace.
Connect the guard traces to the ground plane at both
ends. Also connect long guard traces to the ground
plane in the middle.

MCP6G0X

OUT

DS22004A-page 23

MCP6G01/2/3/4

4.7

Unused Amplifiers

An unused amplifier in a quad package (MCP6G04)
should be configured as shown in

Figure 4-8

. This

circuit prevents the output from toggling and causing
crosstalk. Because the V

pin looks like an open

circuit, the GSEL voltage is automatically set at V

/2,

and the gain is 1 V/V. The output pin provides a
buffered V

/2 voltage and minimizes the supply

current draw of the unused amplifier.

FIGURE 4-8:

Unused Amplifiers.

4.8

Typical Applications

4.8.1

DRIVING THE GAIN SELECT PIN
WITH A MICROCONTROLLER GPIO
PIN

The circuit in

Figure 4-9

uses a microcontroller GPIO

pin to drive the Gain Select input (GSEL). Setting the
GPIO pin to logic low, high-Z or logic high gives a GSEL
voltage of 0V, V

/2 or V

, respectively (G = 10, 1 or

50).

FIGURE 4-9:

Driving the GSEL Pin.

The microcontroller's GPIO pin cannot produce a
leakage current of more than ±1 µA for this circuit to
function properly. In noisy environments, a capacitor
may need to be added to the GPIO pin.

4.8.2

DRIVING THE GAIN SELECT PIN
WITH A PWM SIGNAL

The circuit in

Figure 4-10

uses a PWM output on a PIC

microcontroller (100 kHz clock rate) to drive the Gain
Select input (GSEL). Setting the PWM duty cycle to
0%, 50% or 100% gives a GSEL voltage of 0V, V

or V

, respectively (G = 10, 1 or 50).

FIGURE 4-10:

Driving the GSEL Pin.

The PWM clock rate needs to be fast so it is easily
filtered and does not interfere with the desired signal,
and it needs to be slow enough for good accuracy and
low crosstalk. This filter reduces the ripple at the GSEL
pin to about 7 mV

P-P

at V

= 5.0V. The 10% settling

time is about 200 µs; the filter limits how quickly the
gain can be changed. Scale the resistors and/or
capacitors for other clock rates, or for different ripple.

4.8.3

GAIN RANGING

Figure 4-11

shows a circuit that measures the current

. The circuit's performance benefits from changing

the gain on the SGA. Just as a hand-held multimeter
uses different measurement ranges to obtain the best
results, this circuit makes it easy to set a high gain for
small signals and a low gain for large signals. As a
result, the required dynamic range at the SGA's output
is less than at its input (by up to 34 dB).

FIGURE 4-11:

Wide Dynamic Range

Current Measurement Circuit.

¼ MCP6G04

OUT

MCP6G0X

GSEL

OUT

MCP6G0X

GSEL

MCU

GPIO

OUT

MCP6G0X

GSEL

PIC MCU

PWM

Output

4.7 nF

10 k

4.7 nF

10 k

OUT

MCP6G0X

MCP6G01/2/3/4

DS22004A-page 24

4.8.4

SHIFTED GAIN RANGE SGA

Figure 4-12

shows a circuit using a MCP6271 at a gain

of +10 in front of a MCP6G01. This shifts the overall
gain range to +10 V/V to +500 V/V (from +1 V/V to
+50 V/V).

FIGURE 4-12:

SGA with Higher Gain

Range.

It is also easy to shift the gain range to lower gains (see

Figure 4-13

). The MCP6001 acts as a unity gain buffer,

and the resistive voltage divider shifts the gain range
down to +0.1 V/V to +5.0 V/V (from +1 V/V to +50 V/V).

FIGURE 4-13:

SGA with Lower Gain

Range.

4.8.5

ADC DRIVER

This family of SGAs is well suited for driving Analog-to-
Digital Converters (ADC). The gains (1, 10, and 50)
effectively increase the ADC's input resolution by a
factor of as large as 50 (i.e., by 5.6 bits). This works
well for applications needing relative accuracy more
than absolute accuracy (e.g., power monitoring); see

Figure 4-14

FIGURE 4-14:

SGA as an ADC Driver.

The low-pass filter in the block diagram reduces the
integrated noise at the MCP6G01's output and serves
as an anti-aliasing filter. This filter may be designed
using Microchip's FilterLab

software, available at

www.microchip.com.

OUT

MCP6271

MCP6G01

1.11 k

10.0 k

MCP6001

1.11 k

10.0 k

OUT

MCP6G01

OUT

MCP3001

10-bit

ADC

MCP6G01

Low-pass

Filter

DS22004A-page 25

MCP6G01/2/3/4

5.0

PACKAGING INFORMATION

5.1

Package Marking Information

8-Lead SOIC (150 mil) (MCP6G01, MCP6G02, MCP6G03)

Example:

XXXXXXXX
XXXXYYWW

NNN

8-Lead MSOP (MCP6G01, MCP6G02, MCP6G03)

Example:

XXXXXX
YWWNNN

6G01E

634256

MCP6G01E
SN^^0634

256

Legend: XX...X

Customer-specific information

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week `01')

NNN

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.

Note:

In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

14-Lead SOIC (150 mil) (MCP6S24)

Example:

XXXXXXXXXXX

YYWWNNN

XXXXXXXXXXX

XXXXXXXX

NNN

YYWW

14-Lead TSSOP (4.4mm) (MCP6S24)

Example:

6G04E/ST

256

0609

MCP6G04

0609256

E/SL^^

MCP6G01/2/3/4

DS22004A-page 26

8-Lead Plastic Small Outline (SN) Narrow, 150 mil (SOIC)

Foot Angle

Mold Draft Angle Bottom

Mold Draft Angle Top

0.51

0.42

0.33

.020

.017

.013

Lead Width

0.25

0.23

0.20

.010

.009

.008

Lead Thickness

0.76

0.62

0.48

.030

.025

.019

Foot Length

0.51

0.38

0.25

.020

.015

.010

Chamfer Distance

5.00

4.90

4.80

.197

.193

.189

Overall Length

3.99

3.91

3.71

.157

.154

.146

Molded Package Width

6.20

6.02

5.79

.244

.237

.228

Overall Width

0.25

0.18

0.10

.010

.007

.004

Standoff §

1.55

1.42

1.32

.061

.056

.052

Molded Package Thickness

1.75

1.55

1.35

.069

.061

.053

Overall Height

1.27

.050

Pitch

Number of Pins

MAX

NOM

MIN

MAX

NOM

MIN

Dimension Limits

MILLIMETERS

INCHES*

Units

* Controlling Parameter

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010" (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057

§ Significant Characteristic

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS22004A-page 27

MCP6G01/2/3/4

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037

.035

Footprint (Reference)

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-111

*Controlling Parameter

Mold Draft Angle Top
Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

7
7

.004
.010

.006
.012

(F)

Dimension Limits

Overall Height
Molded Package Thickness

Molded Package Width
Overall Length
Foot Length

Standoff §
Overall Width

Number of Pins
Pitch

.016

.114
.114

.022

.118
.118

.002

.030

.193

.034

MIN

Units

.026

NOM

INCHES

1.00

0.95

0.90

.039

0.15
0.30

.008
.016

0.10
0.25

7
7

0.20
0.40

MILLIMETERS*

0.65

0.86

3.00
3.00
0.55

4.90

.044

.122

.028

.122

.038
.006

0.40

2.90
2.90

0.05

0.76

MIN

MAX

NOM

1.18

0.70

3.10
3.10

0.15

0.97

MAX

§ Significant Characteristic

.184

.200

4.67

.5.08

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

MCP6G01/2/3/4

DS22004A-page 28

14-Lead Plastic Small Outline (SL) Narrow, 150 mil (SOIC)

Foot Angle

Mold Draft Angle Bottom

Mold Draft Angle Top

0.51

0.42

0.36

.020

.017

.014

Lead Width

0.25

0.23

0.20

.010

.009

.008

Lead Thickness

1.27

0.84

0.41

.050

.033

.016

Foot Length

0.51

0.38

0.25

.020

.015

.010

Chamfer Distance

8.81

8.69

8.56

.347

.342

.337

Overall Length

3.99

3.90

3.81

.157

.154

.150

Molded Package Width

6.20

5.99

5.79

.244

.236

.228

Overall Width

0.25

0.18

0.10

.010

.007

.004

Standoff §

1.55

1.42

1.32

.061

.056

.052

Molded Package Thickness

1.75

1.55

1.35

.069

.061

.053

Overall Height

1.27

.050

Pitch

Number of Pins

MAX

NOM

MIN

MAX

NOM

MIN

Dimension Limits

MILLIMETERS

INCHES*

Units

* Controlling Parameter

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010" (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065

§ Significant Characteristic

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS22004A-page 29

MCP6G01/2/3/4

14-Lead Plastic Thin Shrink Small Outline (ST) 4.4 mm (TSSOP)

Foot Angle

Mold Draft Angle Bottom

Mold Draft Angle Top

0.30

0.25

0.19

.012

.010

.007

Lead Width

0.20

0.15

0.09

.008

.006

.004

Lead Thickness

0.70

0.60

0.50

.028

.024

.020

Foot Length

5.10

5.00

4.90

.201

.197

.193

Molded Package Length

4.50

4.40

4.30

.177

.173

.169

Molded Package Width

6.50

6.38

6.25

.256

.251

.246

Overall Width

0.15

0.10

0.05

.006

.004

.002

Standoff §

0.95

0.90

0.85

.037

.035

.033

Molded Package Thickness

1.10

.043

Overall Height

0.65

.026

Pitch

Number of Pins

MAX

NOM

MIN

MAX

NOM

MIN

Dimension Limits

MILLIMETERS*

INCHES

Units

* Controlling Parameter

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005" (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087

§ Significant Characteristic

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS22004A-page 33

MCP6G01/2/3/4

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office

Device:

MCP6G01:

Single SGA

MCP6G01T: Single SGA

(Tape and Reel for MSOP and SOIC)

MCP6G02:

Dual SGA

MCP6G02T: Dual SGA

(Tape and Reel for MSOP and SOIC)

MCP6G03:

Single SGA

MCP6G03T: Single SGA

(Tape and Reel for MSOP and SOIC)

MCP6G04:

Quad SGA

MCP6G04T: Quad SGA

(Tape and Reel for SOIC and TSSOP)

Temperature Range:

= -40°C to +125°C

Package:

MS = Plastic MSOP, 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead (MCP6G04)
ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6G04)

PART NO.

/XX

Package

Temperature

Range

Device

Examples:

MCP6G01-E/MS: Extended Temperature,

8LD MSOP.

MCP6G01T-E/SN: Tape and Reel,

Extended Temperature,
8LD SOIC.

MCP6G02-E/MS: Extended Temperature,

8LD MSOP.

MCP6G02T-E/SN: Tape and Reel,

Extended Temperature,
8LD SOIC.

MCP6G03-E/MS: Extended Temperature,

8LD MSOP.

MCP6G03T-E/SN: Tape and Reel,

Extended Temperature,
8LD SOIC.

MCP6G03-E/SN: Extended Temperature,

8LD SOIC.

MCP6G04T-E/SL: Tape and Reel,

Extended Temperature,
14LD SOIC.

MCP6G04T-E/ST: Tape and Reel,

Extended Temperature,
14LD TSSOP.

MCP6G04-E/ST: Extended Temperature,

14LD TSSOP.

DS22004A-page 35

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer's risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

, microID, MPLAB, PIC, PICmicro,

PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

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dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
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Endurance, UNI/O, WiperLock and ZENA are trademarks of
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countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:
·

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company's quality system processes and procedures are for its

PICmicro

8-bit MCUs, K

code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip's quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS22004A-page 36

AMERICAS

Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Atlanta
Alpharetta, GA
Tel: 770-640-0034
Fax: 770-640-0307
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256

ASIA/PACIFIC

India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350

EUROPE

Austria - Wels
Tel: 43-7242-2244-3910
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820

ORLDWIDE

ALES

AND

ERVICE

08/29/06

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MCP6G0x

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MCP6G0x