Document Outline

• Devices Included in this Data Sheet:
• Pin Diagrams
• Table of Contents
• 1.0 Device Overview
  • TABLE 1-1: PIC16F87XA Device Features
  • FIGURE 1-1: PIC16F873A/876A Block Diagram
  • FIGURE 1-2: PIC16F874A/877A Block Diagram
  • TABLE 1-2: PIC16F873A/876A Pinout Description
  • TABLE 1-3: PIC16F874A/877A Pinout Description
• 2.0 Memory Organization
  • FIGURE 2-1: PIC16F876A/877A Program Memory Map and Stack
  • 2.1 Program Memory Organization
    • FIGURE 2-2: PIC16F873A/874A Program Memory Map and Stack
  • 2.2 Data Memory Organization
    • 2.2.1 General purpose Register File
      • FIGURE 2-3: PIC16F876A/877A Register File Map
      • FIGURE 2-4: PIC16F873A/874A register File Map
    • 2.2.2 Special Function Registers
      • TABLE 2-1: Special Function Register Summary
      • Register 2-1: Status Register (Address 03h, 83h, 103h, 183h)
      • Register 2-2: OPTION_REG Register (Address 81h, 181h)
      • Register 2-3: INTCON Register (Address 0Bh, 8Bh, 10Bh, 18Bh)
      • Register 2-4: PIE1 Register (Address 8Ch)
      • Register 2-5: PIR1 Register (Address 0Ch)
      • Register 2-6: PIE2 Register (Address 8Dh)
      • Register 2-7: PIR2 Register (Address 0Dh)
      • Register 2-8: PCON Register (Address 8Eh)
  • 2.3 PCL and PCLATH
    • FIGURE 2-5: Loading of PC In Different Situations
    • 2.3.1 computed GOTO
    • 2.3.2 Stack
  • 2.4 Program Memory Paging
    • EXAMPLE 2-1: Call of a Subroutine in Page 1 from Page 0
  • 2.5 Indirect Addressing, INDF and FSR Registers
    • EXAMPLE 2-2: Indirect Addressing
    • FIGURE 2-6: Direct/Indirect Addressing
• 3.0 Data EEPROM and Flash Program Memory
  • 3.1 EEADR and EEADRH
  • 3.2 EECON1 and EECON2 Registers
    • Register 3-1: EECON1 Register (Address 18ch)
  • 3.3 Reading Data EEPROM Memory
    • EXAMPLE 3-1: Data EEPROM Read
  • 3.4 Writing to Data EEPROM Memory
    • EXAMPLE 3-2: Data EEPROM Write
  • 3.5 Reading Flash Program Memory
    • EXAMPLE 3-3: Flash PROGRAM Read
  • 3.6 Writing to Flash Program Memory
    • FIGURE 3-1: Block WRITES to Flash Program Memory
    • EXAMPLE 3-4: Writing to Flash Program Memory
  • 3.7 Protection Against Spurious Write
  • 3.8 Operation During Code-Protect
    • TABLE 3-1: Registers/Bits Associated with Data EEPROM and Flash Program Memories
• 4.0 I/O Ports
  • 4.1 PORTA and the TRISA Register
    • EXAMPLE 4-1: Initializing PORTA
    • FIGURE 4-1: Block Diagram of RA3:RA0 Pins
    • FIGURE 4-2: Block Diagram of RA4/T0CKI Pin
    • FIGURE 4-3: Block Diagram of RA5 Pin
    • TABLE 4-1: PORTA Functions
    • TABLE 4-2: Summary of Registers Associated with PORTA
  • 4.2 PORTB and the TRISB Register
    • FIGURE 4-4: Block Diagram of RB3:RB0 Pins
    • FIGURE 4-5: Block Diagram of RB7:RB4 Pins
    • TABLE 4-3: PORTB Functions
    • TABLE 4-4: Summary of Registers Associated with PORTB
  • 4.3 PORTC and the TRISC Register
    • FIGURE 4-6: PORTC Block Diagram (Peripheral Output Override) RC<2:0>, RC<7:5>
    • FIGURE 4-7: PORTC Block Diagram (peripheral output override) RC<4:3>
    • TABLE 4-5: PORTC Functions
    • TABLE 4-6: Summary of Registers Associated with PORTC
  • 4.4 PORTD and TRISD Registers
    • FIGURE 4-8: PORTD Block Diagram (in I/O Port Mode)
    • TABLE 4-7: PORTD Functions
    • TABLE 4-8: Summary of Registers Associated with PORTD
  • 4.5 PORTE and TRISE Register
    • FIGURE 4-9: PORTE Block Diagram (in I/O Port Mode)
    • TABLE 4-9: PORTE Functions
    • TABLE 4-10: Summary of Registers Associated with PORTE
    • Register 4-1: TRISE RegistER (Address 89h)
  • 4.6 Parallel Slave Port
    • FIGURE 4-10: PORTD and PORTE Block Diagram (Parallel Slave Port)
    • FIGURE 4-11: Parallel Slave Port Write Waveforms
    • FIGURE 4-12: Parallel Slave Port Read Waveforms
    • TABLE 4-11: Registers Associated with Parallel Slave Port
• 5.0 Timer0 Module
  • 5.1 Timer0 Interrupt
    • FIGURE 5-1: Block Diagram of the Timer0/WDT Prescaler
  • 5.2 Using Timer0 with an External Clock
  • 5.3 Prescaler
    • Register 5-1: OPTION_REG Register
    • TABLE 5-1: Registers Associated with Timer0
• 6.0 Timer1 Module
  • Register 6-1: T1CON: Timer1 Control Register (Address 10h)
  • 6.1 Timer1 Operation in Timer Mode
  • 6.2 Timer1 Counter Operation
    • FIGURE 6-1: Timer1 Incrementing Edge
  • 6.3 Timer1 Operation in Synchronized Counter Mode
    • FIGURE 6-2: Timer1 Block Diagram
  • 6.4 Timer1 Operation in Asynchronous Counter Mode
    • 6.4.1 Reading and writing Timer1 in asynchronous counter mode
  • 6.5 Timer1 Oscillator
    • TABLE 6-1: Capacitor Selection for the Timer1 Oscillator
  • 6.6 Resetting Timer1 Using a CCP Trigger Output
  • 6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L)
  • 6.8 Timer1 Prescaler
    • TABLE 6-2: Registers Associated with Timer1 as a Timer/Counter
• 7.0 Timer2 Module
  • FIGURE 7-1: Timer2 Block Diagram
  • Register 7-1: T2CON: Timer2 Control Register (Address 12h)
  • 7.1 Timer2 Prescaler and Postscaler
  • 7.2 Output of TMR2
    • TABLE 7-1: Registers Associated with Timer2 as a Timer/Counter
• 8.0 Capture/Compare/PWM Modules
  • TABLE 8-1: CCP Mode � Timer ResourceS REQUIRED
  • TABLE 8-2: Interaction of Two CCP Modules
  • Register 8-1: CCP1CON Register/CCP2CON Register (Address 17h/1DH)
  • 8.1 Capture Mode
    • 8.1.1 CCP pin Configuration
      • FIGURE 8-1: Capture Mode Operation Block Diagram
    • 8.1.2 Timer1 Mode Selection
    • 8.1.3 Software Interrupt
    • 8.1.4 CCP Prescaler
      • EXAMPLE 8-1: Changing between capture prescalers
  • 8.2 Compare Mode
    • FIGURE 8-2: Compare Mode Operation Block Diagram
    • 8.2.1 CCP Pin Configuration
    • 8.2.2 timer1 Mode Selection
    • 8.2.3 Software Interrupt Mode
    • 8.2.4 Special Event Trigger
  • 8.3 PWM Mode (PWM)
    • FIGURE 8-3: Simplified PWM Block Diagram
    • FIGURE 8-4: PWM Output
    • 8.3.1 PWM period
    • 8.3.2 PWM Duty Cycle
      • EQUATION 8-1:
    • 8.3.3 Setup for PWM Operation
      • TABLE 8-3: Example PWM Frequencies and Resolutions at 20 MHz
      • TABLE 8-4: Registers Associated with Capture, compare and Timer1
      • TABLE 8-5: Registers Associated with PWM and Timer2
• 9.0 Master Synchronous Serial Port (MSSP) Module
  • 9.1 Master SSP (MSSP) Module Overview
  • 9.2 Control Registers
  • 9.3 SPI Mode
    • FIGURE 9-1: MSSP Block Diagram (SPIMode)
    • 9.3.1 Registers
      • Register 9-1: SSPSTAT: MSSP Status Register (SPI Mode) (Address 94h)
      • Register 9-2: SSPCON1: MSSP Control Register 1 (SPI Mode) (Address 14h)
    • 9.3.2 Operation
      • EXAMPLE 9-1: Loading the SSPBUF (SSPSR) Register
    • 9.3.3 Enabling SPI I/O
    • 9.3.4 Typical Connection
      • FIGURE 9-2: SPI Master/Slave Connection
    • 9.3.5 Master Mode
      • FIGURE 9-3: SPI Mode Waveform (Master Mode)
    • 9.3.6 Slave Mode
    • 9.3.7 Slave Select Synchronization
      • FIGURE 9-4: Slave Synchronization Waveform
      • FIGURE 9-5: SPI Mode Waveform (Slave Mode with CKE = 0)
      • FIGURE 9-6: SPI Mode Waveform (Slave Mode with CKE = 1)
    • 9.3.8 Sleep Operation
    • 9.3.9 Effects of a Reset
    • 9.3.10 Bus Mode Compatibility
      • TABLE 9-1: SPI Bus Modes
      • TABLE 9-2: Registers Associated with SPI Operation
  • 9.4 I2C Mode
    • FIGURE 9-7: MSSP Block Diagram (I2C Mode)
    • 9.4.1 Registers
      • Register 9-3: SSPSTAT: MSSP Status Register (I2C Mode) (Address 94h)
      • Register 9-4: SSPCON1: MSSP Control Register 1 (I2C Mode) (Address 14h)
      • Register 9-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C Mode) (Address 91h)
    • 9.4.2 Operation
    • 9.4.3 SLAVE Mode
      • FIGURE 9-8: I2C Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)
      • FIGURE 9-9: I2C Slave Mode Timing (Transmission, 7-bit Address)
      • FIGURE 9-10: I2C Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)
      • FIGURE 9-11: I2C Slave Mode Timing (Transmission, 10-bit Address)
    • 9.4.4 Clock Stretching
      • FIGURE 9-12: Clock synchronization Timing
      • FIGURE 9-13: I2C Slave Mode Timing With SEN = 1 (Reception, 7-bit Address)
      • FIGURE 9-14: I2C Slave Mode Timing SEN = 1 (Reception, 10-bit Address)
    • 9.4.5 General Call Address Support
      • FIGURE 9-15: Slave Mode General Call Address Sequence (7 or 10-bit Address Mode)
    • 9.4.6 Master Mode
      • FIGURE 9-16: MSSP Block Diagram (I2C Master Mode)
    • 9.4.7 Baud Rate Generator
      • FIGURE 9-17: Baud Rate Generator Block Diagram
      • TABLE 9-3: I2C Clock Rate w/BRG
      • FIGURE 9-18: Baud Rate Generator Timing With Clock Arbitration
    • 9.4.8 I2C Master Mode Start Condition Timing
      • FIGURE 9-19: First Start Bit Timing
    • 9.4.9 I2C Master Mode Repeated Start Condition Timing
      • FIGURE 9-20: Repeat Start Condition Waveform
    • 9.4.10 I2C Master Mode Transmission
    • 9.4.11 I2C Master Mode Reception
      • FIGURE 9-21: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address)
      • FIGURE 9-22: I2C Master Mode Waveform (Reception, 7-Bit Address)
    • 9.4.12 Acknowledge Sequence Timing
    • 9.4.13 Stop Condition Timing
      • FIGURE 9-23: Acknowledge Sequence Waveform
      • FIGURE 9-24: Stop Condition Receive or Transmit Mode
    • 9.4.14 Sleep Operation
    • 9.4.15 Effect of a Reset
    • 9.4.16 Multi-Master Mode
    • 9.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
      • FIGURE 9-25: Bus Collision Timing for Transmit and Acknowledge
      • FIGURE 9-26: Bus Collision During Start Condition (SDA only)
      • FIGURE 9-27: Bus Collision During Start Condition (SCL = 0)
      • FIGURE 9-28: BRG Reset Due to SDA Arbitration During Start Condition
      • FIGURE 9-29: Bus Collision During a Repeated Start Condition (Case 1)
      • FIGURE 9-30: Bus Collision During Repeated Start Condition (Case 2)
      • FIGURE 9-31: Bus Collision During a Stop Condition (Case 1)
      • FIGURE 9-32: Bus Collision During a Stop Condition (Case 2)
• 10.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)
  • Register 10-1: TXSTA: Transmit Status and Control Register (Address 98h)
  • Register 10-2: RCSTA: Receive Status and Control Register (Address 18h)
  • 10.1 USART Baud Rate Generator (BRG)
    • 10.1.1 SAMPLING
      • TABLE 10-1: Baud Rate Formula
      • TABLE 10-2: Registers Associated with Baud Rate Generator
      • TABLE 10-3: Baud Rates for Asynchronous Mode (BRGH = 0)
      • TABLE 10-4: Baud Rates for Asynchronous Mode (BRGH = 1)
  • 10.2 USART Asynchronous Mode
    • 10.2.1 USART Asynchronous Transmitter
      • FIGURE 10-1: USART Transmit Block Diagram
      • FIGURE 10-2: Asynchronous Master Transmission
      • FIGURE 10-3: Asynchronous Master Transmission (Back to Back)
      • TABLE 10-5: Registers Associated with Asynchronous Transmission
    • 10.2.2 USART Asynchronous Receiver
      • FIGURE 10-4: USART Receive Block Diagram
      • FIGURE 10-5: Asynchronous Reception
      • TABLE 10-6: Registers Associated with Asynchronous Reception
    • 10.2.3 Setting up 9-bit mode with Address Detect
      • FIGURE 10-6: USART Receive Block Diagram
      • FIGURE 10-7: Asynchronous Reception with Address Detect
      • FIGURE 10-8: Asynchronous Reception with Address Byte First
      • TABLE 10-7: Registers Associated with Asynchronous Reception
  • 10.3 USART Synchronous Master Mode
    • 10.3.1 USART Synchronous Master Transmission
      • TABLE 10-8: Registers Associated with Synchronous Master Transmission
      • FIGURE 10-9: Synchronous Transmission
      • FIGURE 10-10: Synchronous Transmission (Through TXEN)
    • 10.3.2 USART Synchronous Master Reception
      • TABLE 10-9: Registers Associated with Synchronous Master Reception
      • FIGURE 10-11: Synchronous Reception (Master Mode, SREN)
  • 10.4 USART Synchronous Slave Mode
    • 10.4.1 USART Synchronous Slave Transmit
      • TABLE 10-10: Registers Associated with Synchronous Slave Transmission
    • 10.4.2 USART Synchronous Slave Reception
      • TABLE 10-11: Registers Associated with Synchronous Slave Reception
• 11.0 Analog-to-Digital Converter (A/D) Module
  • Register 11-1: ADCON0 Register (Address 1Fh)
  • Register 11-2: ADCON1 Register (Address 9fh)
  • FIGURE 11-1: A/D Block Diagram
  • 11.1 A/D Acquisition Requirements
    • EQUATION 11-1: Acquisition Time
    • FIGURE 11-2: Analog Input Model
  • 11.2 Selecting the A/D Conversion Clock
  • 11.3 Configuring Analog Port Pins
    • TABLE 11-1: Tad vs. Maximum Device Operating Frequencies (Standard devices (F))
  • 11.4 A/D Conversions
    • FIGURE 11-3: A/D Conversion Tad Cycles
    • 11.4.1 A/D Result Registers
      • FIGURE 11-4: A/D Result Justification
  • 11.5 A/D Operation During Sleep
  • 11.6 Effects of a Reset
    • TABLE 11-2: Registers/bits Associated with A/D
• 12.0 Comparator Module
  • Register 12-1: CMCON Register
  • 12.1 Comparator Configuration
    • FIGURE 12-1: Comparator I/O Operating Modes
  • 12.2 Comparator Operation
  • 12.3 Comparator Reference
    • FIGURE 12-2: Single Comparator
    • 12.3.1 EXTERNAL REFERENCE SIGNAL
    • 12.3.2 INTERNAL REFERENCE SIGNAL
  • 12.4 Comparator Response Time
  • 12.5 Comparator Outputs
    • FIGURE 12-3: Comparator Output Block Diagram
  • 12.6 Comparator Interrupts
  • 12.7 Comparator Operation During Sleep
  • 12.8 Effects of a Reset
  • 12.9 Analog Input Connection Considerations
    • FIGURE 12-4: Analog Input Model
    • TABLE 12-1: Registers Associated with Comparator Module
• 13.0 Comparator Voltage Reference Module
  • Register 13-1: CVRCON Control Register (Address 9Dh)
  • FIGURE 13-1: Comparator Voltage Reference Block Diagram
  • TABLE 13-1: Registers Associated with Comparator Voltage Reference
• 14.0 Special Features of the CPU
  • 14.1 Configuration Bits
    • Register 14-1: Configuration Word (ADDRESS 2007H)(1)
  • 14.2 Oscillator Configurations
    • 14.2.1 Oscillator Types
    • 14.2.2 Crystal Oscillator/CERAmic Resonators
      • FIGURE 14-1: Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration)
      • FIGURE 14-2: External Clock Input Operation (HS, XT or LP OSC Configuration)
      • TABLE 14-1: Ceramic Resonators
      • TABLE 14-2: Capacitor Selection for Crystal Oscillator
    • 14.2.3 RC Oscillator
      • FIGURE 14-3: RC Oscillator Mode
  • 14.3 Reset
    • FIGURE 14-4: Simplified Block Diagram of On-chip Reset Circuit
  • 14.4 MCLR
    • FIGURE 14-5: Recommended MCLR Circuit
  • 14.5 Power-on Reset (POR)
  • 14.6 Power-up Timer (PWRT)
  • 14.7 Oscillator Start-up Timer (OST)
  • 14.8 Brown-out Reset (BOR)
  • 14.9 Time-out Sequence
  • 14.10 Power Control/Status Register (PCON)
    • TABLE 14-3: Time-out in Various Situations
    • TABLE 14-4: Status Bits and Their Significance
    • TABLE 14-5: Reset ConditionS for Special Registers
    • TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
    • FIGURE 14-6: Time-out Sequence on Power-up (MCLR Tied to Vdd VIA RC NETWORK)
    • FIGURE 14-7: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1
    • FIGURE 14-8: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2
    • FIGURE 14-9: Slow Rise Time (MCLR Tied to Vdd VIA RC NETWORK)
  • 14.11 Interrupts
    • FIGURE 14-10: Interrupt Logic
    • 14.11.1 INT Interrupt
    • 14.11.2 TMR0 Interrupt
    • 14.11.3 PortB INTCON CHANGE
  • 14.12 Context Saving During Interrupts
    • EXAMPLE 14-1: Saving Status, W and PCLATH Registers in RAM
  • 14.13 Watchdog Timer (WDT)
    • FIGURE 14-11: Watchdog Timer Block Diagram
    • TABLE 14-7: Summary of Watchdog Timer Registers
  • 14.14 Power-down Mode (Sleep)
    • 14.14.1 Wake-up from Sleep
    • 14.14.2 Wake-Up Using Interrupts
      • FIGURE 14-12: Wake-up from Sleep Through Interrupt
  • 14.15 In-Circuit Debugger
    • TABLE 14-8: Debugger Resources
  • 14.16 Program Verification/Code Protection
  • 14.17 ID Locations
  • 14.18 In-Circuit Serial Programming
  • 14.19 Low-Voltage (Single-Supply) ICSP Programming
• 15.0 Instruction Set Summary
  • 15.1 READMODIFY-WRITE OPERATIONS
    • TABLE 15-1: Opcode Field Descriptions
    • FIGURE 15-1: General Format for Instructions
    • TABLE 15-2: PIC16F87XA Instruction Set
  • 15.2 Instruction Descriptions
• 16.0 Development Support
  • 16.1 MPLAB Integrated Development Environment Software
  • 16.2 MPASM Assembler
  • 16.3 MPLAB C17 and MPLAB C18 C Compilers
  • 16.4 MPLINK Object Linker/ MPLIB Object Librarian
  • 16.5 MPLAB C30 C Compiler
  • 16.6 MPLAB ASM30 Assembler, Linker, and Librarian
  • 16.7 MPLAB SIM Software Simulator
  • 16.8 MPLAB SIM30 Software Simulator
  • 16.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator
  • 16.10 MPLAB ICE 4000 High Performance Universal In-Circuit Emulator
  • 16.11 MPLAB ICD 2 In-Circuit Debugger
  • 16.12 PRO MATE II Universal Device Programmer
  • 16.13 PICSTART Plus Development Programmer
  • 16.14 PICDEM 1 PICmicro Demonstration Board
  • 16.15 PICDEM.net Internet/Ethernet Demonstration Board
  • 16.16 PICDEM 2 Plus Demonstration Board
  • 16.17 PICDEM 3 PIC16C92X Demonstration Board
  • 16.18 PICDEM 4 8/14/18-Pin Demonstration Board
  • 16.19 PICDEM 17 Demonstration Board
  • 16.20 PICDEM 18R PIC18C601/801 Demonstration Board
  • 16.21 PICDEM LIN PIC16C43X Demonstration Board
  • 16.22 PICkitTM 1 Flash Starter Kit
  • 16.23 PICDEM USB PIC16C7X5 Demonstration Board
  • 16.24 Evaluation and Programming Tools
• 17.0 Electrical Characteristics
  • Absolute Maximum Ratings �
    • FIGURE 17-1: PIC16F87Xa Voltage-Frequency Graph (Industrial, Extended)
    • FIGURE 17-2: PIC16LF87XA Voltage-Frequency Graph (Industrial)
  • 17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/8...
  • 17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/8...
    • TABLE 17-1: Comparator Specifications
    • TABLE 17-2: Voltage Reference Specifications
  • 17.3 Timing Parameter Symbology
    • FIGURE 17-3: Load Conditions
    • FIGURE 17-4: External Clock Timing
    • TABLE 17-3: External Clock Timing Requirements 
    • FIGURE 17-5: CLKO and I/O Timing
    • TABLE 17-4: CLKO and I/O Timing Requirements
    • FIGURE 17-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
    • FIGURE 17-7: Brown-out Reset Timing
    • TABLE 17-5: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and brown-out reset ...
    • FIGURE 17-8: Timer0 and Timer1 External Clock Timings
    • TABLE 17-6: Timer0 and Timer1 External Clock Requirements
    • FIGURE 17-9: Capture/Compare/PWM Timings (CCP1 and CCP2)
    • TABLE 17-7: Capture/Compare/PWM Requirements (CCP1 and CCP2)
    • FIGURE 17-10: Parallel Slave Port Timing (PIC16F874A/877A only)
    • TABLE 17-8: Parallel Slave Port Requirements (PIC16F874A/877A only)
    • FIGURE 17-11: SPI Master Mode Timing (CKE=0, smp = 0)
    • FIGURE 17-12: SPI Master Mode Timing (CKE=1, SMP = 1)
    • FIGURE 17-13: SPI Slave Mode Timing (CKE=0)
    • FIGURE 17-14: SPI Slave Mode Timing (CKE=1)
    • TABLE 17-9: SPI Mode requirements
    • FIGURE 17-15: I2C Bus Start/Stop Bits Timing
    • TABLE 17-10: I2C Bus Start/Stop Bits Requirements
    • FIGURE 17-16: I2C Bus Data Timing
    • TABLE 17-11: I2C Bus Data Requirements
    • FIGURE 17-17: USART Synchronous Transmission (Master/Slave) Timing
    • TABLE 17-12: USART Synchronous Transmission Requirements
    • FIGURE 17-18: USART Synchronous Receive (Master/Slave) Timing
    • TABLE 17-13: USART Synchronous Receive Requirements
    • TABLE 17-14: A/D Converter Characteristics: PIC16F873A/874A/876A/877A (Industrial) PIC16LF873A/87...
    • FIGURE 17-19: A/D Conversion Timing
    • TABLE 17-15: A/D Conversion Requirements
• 18.0 DC and AC Characteristics Graphs and Tables
  • FIGURE 18-1: Typical Idd vs. Fosc over Vdd (HS Mode)
  • FIGURE 18-2: Maximum Idd vs. Fosc over Vdd (HS Mode)
  • FIGURE 18-3: Typical Idd vs. Fosc over Vdd (XT Mode)
  • FIGURE 18-4: Maximum Idd vs. Fosc over Vdd (XT Mode)
  • FIGURE 18-5: Typical Idd vs. Fosc over Vdd (LP Mode)
  • FIGURE 18-6: Maximum Idd vs. Fosc over Vdd (LP Mode)
  • FIGURE 18-7: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 20 pF, +25�C)
  • FIGURE 18-8: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 100 pF, +25�C)
  • FIGURE 18-9: Average Fosc vs. Vdd for Various Values of R (RC Mode, C = 300pF, +25�C)
  • FIGURE 18-10: Ipd vs. Vdd, -40�C to +125�C (Sleep Mode, all peripherals disabled)
  • FIGURE 18-11: Typical and Maximum DItmr1 vs. Vdd over Temperature (-10�C TO +70�C, Timer1 with Os...
  • FIGURE 18-12: Typical and Maximum DIwdt vs. Vdd over Temperature (WDT enabled)
  • FIGURE 18-13: DIbor vs. Vdd over Temperature
  • FIGURE 18-14: Typical, Minimum and Maximum WDT Period vs. Vdd (-40�C to +125�C)
  • FIGURE 18-15: Average WDT Period vs. Vdd over Temperature (-40�C to +125�C)
  • FIGURE 18-16: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 5V, -40�C to +125�C)
  • FIGURE 18-17: Typical, Minimum and Maximum Voh vs. Ioh (Vdd = 3V, -40�C to +125�C)
  • FIGURE 18-18: Typical, Minimum and Maximum Vol vs. Iol (Vdd = 5V, -40�C to +125�C)
  • FIGURE 18-19: Typical, Minimum and Maximum Vol vs. Iol (Vdd = 3V, -40�C to +125�C)
  • FIGURE 18-20: Minimum and Maximum Vin vs. Vdd (TTL Input, -40�C to +125�C)
  • FIGURE 18-21: Minimum and Maximum Vin vs. Vdd (ST Input, -40�C to +125�C)
  • FIGURE 18-22: Minimum and Maximum Vin vs. Vdd (I2C Input, -40�C to +125�C)
  • FIGURE 18-23: A/D Nonlinearity vs. Vrefh (Vdd = Vrefh, -40�C to +125�C)
  • FIGURE 18-24: A/D Nonlinearity vs. Vrefh (Vdd = 5V, -40�C to +125�C)
• 19.0 Packaging Information
  • 19.1 Package Marking Information
  • Package Marking Information (Cont�d)
  • 40-Lead Plastic Dual In-line (P) � 600 mil (PDIP)
  • 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
  • 44-Lead Plastic Leaded Chip Carrier (L) � Square (PLCC)
  • 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
  • 28-Lead Skinny Plastic Dual In-line (SP) � 300 mil (PDIP)
  • 28-Lead Plastic Small Outline (SO) �Wide, 300 mil (SOIC)
  • 28-Lead Plastic Shrink Small Outline (SS) � 209 mil, 5.30 mm (SSOP)
  • 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Punch Singulated (QFN)
• Appendix A: Revision History
  • Revision A (November 2001)
  • Revision B (October 2003)
• Appendix B: Device Differences
  • TABLE B-1: Differences Between Devices in the PIC16F87XA Family
• Appendix C: Conversion Considerations
  • TABLE C-1: Conversion Considerations
• INDEX
• On-Line Support
  • Connecting to the Microchip Internet Web Site
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