Document Outline

• 14-bit Power Control PWM Module:
• Motion Feedback Module:
• High-Speed, 200 Ksps 10-bit A/D Converter:
• Flexible Oscillator Structure:
• Power-Managed Modes:
• Peripheral Highlights:
• Special Microcontroller Features:
• Pin Diagrams
• Table of Contents
• 1.0 Device Overview
  • 1.1 New Core Features
    • 1.1.1 nanoWATT TECHNOLOGY
    • 1.1.2 Multiple Oscillator Options and Features
  • 1.2 Other Special Features
  • 1.3 Details on Individual Family Members
    • TABLE 1-1: Device Features
    • FIGURE 1-1: PIC18F2331/2431 Block Diagram
    • FIGURE 1-2: PIC18F4331/4431 Block Diagram
    • TABLE 1-2: PIC18F2331/2431 Pinout I/O Descriptions
    • TABLE 1-3: PIC18F4331/4431 Pinout I/O Descriptions 
• 2.0 Oscillator Configurations
  • 2.1 Oscillator Types
  • 2.2 Crystal Oscillator/Ceramic Resonators
    • FIGURE 2-1: Crystal/Ceramic Resonator Operation (XT, LP, HS or HSPLL Configuration)
    • TABLE 2-1: Capacitor Selection for Ceramic Resonators
    • TABLE 2-2: Capacitor Selection for Crystal Oscillator
    • FIGURE 2-2: External Clock Input Operation (HS OSC Configuration)
  • 2.3 HSPLL
    • FIGURE 2-3: PLL Block Diagram
  • 2.4 External Clock Input
    • FIGURE 2-4: External Clock Input Operation (EC Configuration)
    • FIGURE 2-5: External Clock Input Operation (ECIO Configuration)
  • 2.5 RC Oscillator
    • FIGURE 2-6: RC Oscillator Mode
    • FIGURE 2-7: RCIO Oscillator Mode
  • 2.6 Internal Oscillator Block
    • 2.6.1 INTIO Modes
    • 2.6.2 INTRC Output Frequency
    • 2.6.3 OSCTUNE Register
      • Register 2-1: OSCTUNE: Oscillator Tuning Register
  • 2.7 Clock Sources and Oscillator Switching
    • 2.7.1 Oscillator Control Register
      • FIGURE 2-8: PIC18F2331/2431/4331/4431 Clock Diagram
      • Register 2-2: OSCCON Register
    • 2.7.2 Oscillator Transitions
  • 2.8 Effects of Power-Managed Modes on the Various Clock Sources
  • 2.9 Power-up Delays
    • TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
• 3.0 Power-Managed Modes
  • 3.1 Selecting Power-Managed Modes
    • 3.1.1 Clock Sources
      • TABLE 3-1: Power-Managed Modes
    • 3.1.2 Entering Power-Managed Modes
    • 3.1.3 Multiple Sleep Commands
    • 3.1.4 Comparisons Between Run and Idle Modes
      • TABLE 3-2: Comparison Between Power-Managed Modes
  • 3.2 Sleep Mode
  • 3.3 Idle Modes
    • FIGURE 3-1: Timing Transition for Entry to Sleep Mode
    • FIGURE 3-2: Transition Timing For Wake From Sleep (HSPLL)
    • 3.3.1 PRI_IDLE Mode
      • FIGURE 3-3: Transition Timing to PRI_Idle Mode
      • FIGURE 3-4: Transition Timing For Wake From PRI_Idle Mode
    • 3.3.2 SEC_IDLE Mode
      • FIGURE 3-5: Timing Transition for Entry to SEC_IDLE Mode
      • FIGURE 3-6: Timing Transition for Wake from SEC_RUN MODE (HSPLL)
    • 3.3.3 RC_IDLE Mode
      • FIGURE 3-7: Timing Transition to RC_IDLE Mode
      • FIGURE 3-8: Timing Transition for Wake from RC_RUN MODE (RC_RUN to PRI_RUN)
  • 3.4 Run Modes
    • 3.4.1 PRI_RUN mode
    • 3.4.2 SEC_RUN Mode
      • FIGURE 3-9: Timing Transition for Entry to SEC_RUN Mode
    • 3.4.3 RC_RUN Mode
      • FIGURE 3-10: Timing Transition to RC_RUN Mode
    • 3.4.4 Exit to Idle Mode
    • 3.4.5 Exit to Sleep Mode
  • 3.5 Wake From Power-Managed Modes
    • 3.5.1 Exit by Interrupt
      • TABLE 3-3: Activity and Exit Delay on Wake from Sleep Mode OR ANY Idle MODE (By Clock Sources)
    • 3.5.2 Exit by Reset
    • 3.5.3 Exit by WDT Time-out
    • 3.5.4 Exit Without an Oscillator Start-up Delay
  • 3.6 INTOSC Frequency Drift
    • 3.6.1 Example � USART
    • 3.6.2 Example � Timers
    • 3.6.3 Example � CCP in Capture Mode
• 4.0 Reset
  • FIGURE 4-1: Simplified Block Diagram of On-chip Reset Circuit
  • 4.1 Power-on Reset (POR)
    • FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
  • 4.2 Power-up Timer (PWRT)
  • 4.3 Oscillator Start-up Timer (OST)
  • 4.4 PLL Lock Time-out
  • 4.5 Brown-out Reset (BOR)
  • 4.6 Time-out Sequence
    • TABLE 4-1: Time-out in Various Situations
    • Register 4-1: RCON Register Bits and Positions
    • TABLE 4-2: Status Bits, Their Significance and the Initialization Condition for RCON Register
    • TABLE 4-3: Initialization Conditions for All Registers
    • FIGURE 4-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd RISE < Tpwrt)
    • FIGURE 4-4: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 1
    • FIGURE 4-5: Time-out Sequence on Power-up (MCLR not Tied to Vdd): Case 2
    • FIGURE 4-6: Slow Rise Time (MCLR Tied to Vdd, Vdd RISE > Tpwrt)
    • FIGURE 4-7: Time-out Sequence on POR w/ PLL Enabled (MCLR tied to Vdd)
• 5.0 Memory Organization
  • FIGURE 5-1: Program Memory Map and Stack for PIC18F2331/4331
  • 5.1 Program Memory Organization
    • FIGURE 5-2: Program Memory Map and Stack for PIC18F2431/4431
  • 5.2 Return Address Stack
    • 5.2.1 Top-of-Stack Access
    • 5.2.2 Return Stack Pointer (STKPTR)
      • FIGURE 5-3: Return Address Stack and Associated Registers
      • Register 5-1: STKPTR Register
    • 5.2.3 PUSH and POP instructions
    • 5.2.4 Stack Full/Underflow Resets
  • 5.3 Fast Register Stack
    • EXAMPLE 5-1: Fast Register Stack Code Example
  • 5.4 PCL, PCLATH and PCLATU
  • 5.5 Clocking Scheme/Instruction Cycle
  • 5.6 Instruction Flow/Pipelining
    • FIGURE 5-4: Clock/Instruction Cycle
    • EXAMPLE 5-2: Instruction Pipeline Flow
  • 5.7 Instructions in Program Memory
    • FIGURE 5-5: Instructions in Program memory
    • 5.7.1 Two-Word Instructions
      • EXAMPLE 5-3: Two-Word Instructions
  • 5.8 Look-up Tables
    • 5.8.1 Computed GOTO
      • EXAMPLE 5-4: Computed GOTO Using an offset value
    • 5.8.2 Table reads/Table writes
  • 5.9 Data Memory Organization
    • 5.9.1 General Purpose Register File
      • FIGURE 5-6: Data Memory Map for PIC18F2331/2431/4331/4431 Devices
    • 5.9.2 Special Function Registers
      • TABLE 5-1: Special Function Register Map for PIC18F2331/2431/4331/4431 Devices
      • TABLE 5-2: Register File Summary (PIC18F2331/2431/4331/4431) 
  • 5.10 Access Bank
  • 5.11 Bank Select Register (BSR)
    • FIGURE 5-7: Direct Addressing
  • 5.12 Indirect Addressing, INDF and FSR Registers
    • EXAMPLE 5-5: How to Clear RAM (Bank 1) Using Indirect Addressing
    • 5.12.1 Indirect Addressing Operation
      • FIGURE 5-8: Indirect Addressing Operation
      • FIGURE 5-9: Indirect Addressing
  • 5.13 Status Register
    • Register 5-2: Status Register
  • 5.14 RCON Register
    • Register 5-3: RCON Register
• 6.0 Flash Program Memory
  • 6.1 Table Reads and Table Writes
    • FIGURE 6-1: Table Read Operation
    • FIGURE 6-2: Table Write Operation
  • 6.2 Control Registers
    • 6.2.1 EECON1 AND EECON2 REGISTERS
      • Register 6-1: EECON1 Register
    • 6.2.2 TABLAT � Table Latch Register
    • 6.2.3 TBLPTR � Table Pointer Register
    • 6.2.4 TABLE POINTER BOUNDARIES
      • TABLE 6-1: Table Pointer Operations with TBLRD and TBLWT Instructions
      • FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
  • 6.3 Reading the Flash Program Memory
    • FIGURE 6-4: Reads from Flash Program Memory
    • EXAMPLE 6-1: READING A Flash PROGRAM MEMORY WORD
  • 6.4 Erasing Flash Program Memory
    • 6.4.1 Flash Program Memory Erase Sequence
      • EXAMPLE 6-2: ERasing a Flash PROGRAM MEMORY row
  • 6.5 Writing to Flash Program Memory
    • FIGURE 6-5: TABLE WRITES to Flash PROGRAM MEMORY
    • 6.5.1 Flash Program memory write sequence
      • EXAMPLE 6-3: writing to Flash PROGRAM MEMORY
      • EXAMPLE 6-3: writing to Flash PROGRAM MEMORY (CONTINUED)
    • 6.5.2 Write verify
    • 6.5.3 unexpected termination of write operation
  • 6.6 Flash Program Operation During Code Protection
    • TABLE 6-2: Registers Associated with program Flash Memory
• 7.0 Data EEPROM Memory
  • 7.1 EEADR
  • 7.2 EECON1 and EECON2 Registers
    • Register 7-1: EECON1 Register
  • 7.3 Reading the Data EEPROM Memory
  • 7.4 Writing to the Data EEPROM Memory
  • 7.5 Write Verify
  • 7.6 Protection Against Spurious Write
    • EXAMPLE 7-1: Data EEPROM Read
    • EXAMPLE 7-2: Data EEPROM Write
  • 7.7 Operation During Code-Protect
  • 7.8 Using the Data EEPROM
    • EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE
    • TABLE 7-1: Registers Associated with Data EEPROM Memory
• 8.0 8 X 8 Hardware Multiplier
  • 8.1 Introduction
    • TABLE 8-1: Performance Comparison
  • 8.2 Operation
    • EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine
    • EXAMPLE 8-2: 8 x 8 Signed Multiply Routine
    • EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm
    • EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine
    • EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm
    • EXAMPLE 8-4: 16 x 16 Signed Multiply Routine
• 9.0 Interrupts
  • FIGURE 9-1: Interrupt Logic
  • 9.1 INTCON Registers
    • Register 9-1: INTCON Register
    • Register 9-2: INTCON2 Register
    • Register 9-3: INTCON3 Register
  • 9.2 PIR Registers
    • Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1
    • Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2
    • Register 9-6: PIR3: Peripheral Interrupt Flag Register 3
  • 9.3 PIE Registers
    • Register 9-7: PIE1: Peripheral Interrupt Enable Register 1
    • Register 9-8: PIE2: Peripheral Interrupt Enable Register 2
    • Register 9-9: PIE3: Peripheral Interrupt Enable Register 3
  • 9.4 IPR Registers
    • Register 9-10: IPR1: Peripheral Interrupt Priority Register 1
    • Register 9-11: IPR2: Peripheral Interrupt Priority Register 2
    • Register 9-12: IPR3: Peripheral Interrupt Priority Register 3
  • 9.5 RCON Register
    • Register 9-13: RCON Register
  • 9.6 INTn Pin Interrupts
  • 9.7 TMR0 Interrupt
  • 9.8 PORTB Interrupt-on-Change
  • 9.9 Context Saving During Interrupts
    • EXAMPLE 9-1: Saving Status, WREG and BSR Registers in RAM
• 10.0 I/O Ports
  • FIGURE 10-1: Generic I/O Port Operation
  • 10.1 PORTA, TRISA and LATA Registers
    • EXAMPLE 10-1: Initializing PORTA
    • FIGURE 10-2: Block Diagram of RA0
    • FIGURE 10-3: Block Diagram of RA1
    • FIGURE 10-4: Block Diagram of RA3:RA2 Pins
    • FIGURE 10-5: Block Diagram of RA4
    • FIGURE 10-6: Block Diagram of RA5
    • FIGURE 10-7: Block Diagram of RA6
    • FIGURE 10-8: Block Diagram of RA7
    • TABLE 10-1: PORTA Functions
    • TABLE 10-2: Summary of Registers Associated with PORTA
  • 10.2 PORTB, TRISB and LATB Registers
    • EXAMPLE 10-2: Initializing PORTB
    • FIGURE 10-9: Block Diagram of RB3:RB0 Pins
    • FIGURE 10-10: Block Diagram of RB4
    • FIGURE 10-11: Block Diagram of RB5
    • FIGURE 10-12: Block Diagram of RB7:RB6 Pins
    • TABLE 10-3: PORTB Functions
    • TABLE 10-4: Summary of Registers Associated with PORTB
  • 10.3 PORTC, TRISC and LATC Registers
    • EXAMPLE 10-3: Initializing PORTC
    • FIGURE 10-13: Block Diagram of RC0
    • FIGURE 10-14: Block Diagram of RC1
    • FIGURE 10-15: Block Diagram of RC2
    • FIGURE 10-16: Block Diagram of RC3
    • FIGURE 10-17: Block Diagram of RC4
    • FIGURE 10-18: Block Diagram of RC5
    • FIGURE 10-19: Block Diagram of RC6
    • FIGURE 10-20: Block Diagram of RC6
    • TABLE 10-5: PORTC Functions
    • TABLE 10-6: Summary of Registers Associated with PORTC
  • 10.4 PORTD, TRISD and LATD Registers
    • EXAMPLE 10-4: Initializing PORTD
    • FIGURE 10-21: Block Diagram of RD7:RD6 Pins
    • FIGURE 10-22: Block Diagram of RD5
    • FIGURE 10-23: Block Diagram of RD4
    • FIGURE 10-24: Block Diagram of RD3
    • FIGURE 10-25: Block Diagram of RD2
    • FIGURE 10-26: Block Diagram of RD1
    • FIGURE 10-27: Block Diagram of RD0
    • TABLE 10-7: PORTD Functions
    • TABLE 10-8: Summary of Registers Associated with PORTD
  • 10.5 PORTE, TRISE and LATE Registers
    • EXAMPLE 10-5: Initializing PORTE
    • 10.5.1 PORTE in 28-pin Devices
      • FIGURE 10-28: RE2:RE0 Block Diagram
      • FIGURE 10-29: RE3 Block Diagram
      • Register 10-1: TRISE Register
      • TABLE 10-9: PORTE Functions
      • TABLE 10-10: Summary of Registers Associated with PORTE
• 11.0 Timer0 Module
  • Register 11-1: T0CON: Timer0 Control Register
  • FIGURE 11-1: Timer0 Block Diagram in 8-bit Mode
  • FIGURE 11-2: Timer0 Block Diagram in 16-bit Mode
  • 11.1 Timer0 Operation
  • 11.2 Prescaler
    • 11.2.1 Switching Prescaler Assignment
  • 11.3 Timer0 Interrupt
  • 11.4 16-Bit Mode Timer Reads and Writes
    • TABLE 11-1: Registers Associated with Timer0
• 12.0 Timer1 Module
  • Register 12-1: T1CON: Timer1 Control Register
  • 12.1 Timer1 Operation
    • FIGURE 12-1: Timer1 Block Diagram
    • FIGURE 12-2: Timer1 Block Diagram: 16-bit Read/Write Mode
  • 12.2 Timer1 Oscillator
    • FIGURE 12-3: External Components for the TIMER1 LP Oscillator
    • TABLE 12-1: Capacitor Selection for the TIMER Oscillator
  • 12.3 Timer1 Oscillator Layout Considerations
    • FIGURE 12-4: Oscillator Circuit with Grounded Guard ring
  • 12.4 Timer1 Interrupt
  • 12.5 Resetting Timer1 Using a CCP Trigger Output
  • 12.6 Timer1 16-Bit Read/Write Mode
  • 12.7 Using Timer1 as a Real-Time Clock
    • EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt service
    • TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
• 13.0 Timer2 Module
  • 13.1 Timer2 Operation
    • Register 13-1: T2CON: Timer2 Control Register
  • 13.2 Timer2 Interrupt
  • 13.3 Output of TMR2
    • FIGURE 13-1: Timer2 Block Diagram
    • TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
• 14.0 Timer5 Module
  • Register 14-1: T5CON: Timer5 Control Register
  • FIGURE 14-1: Timer5 Block Diagram (16-bit Read/Write Mode Shown)
  • 14.1 Timer5 Operation
    • 14.1.1 Continuous and Single-Shot Operation
  • 14.2 16-bit Read/Write and Write Modes
    • 14.2.1 16-bit Read-Modify-Write
  • 14.3 Timer5 Prescaler
  • 14.4 Noise Filter
  • 14.5 Timer5 Interrupt
  • 14.6 Timer5 Special Event Trigger Output
  • 14.7 Timer5 Special Event Reset Input
    • 14.7.1 Wake-up on IC1 Edge
    • 14.7.2 Delayed-action Event Trigger
    • 14.7.3 Special Event Reset While Timer5 Is Incrementing
  • 14.8 Operation in Sleep Mode
    • 14.8.1 INTERRUPT DETECT IN Sleep MODE
      • TABLE 14-1: Registers associated with Timer5
• 15.0 Capture/Compare/PWM (CCP) Modules
  • Register 15-1: CCPxCON: CCP Module Control Register
  • 15.1 CCP1 Module
    • TABLE 15-1: CCP Mode � Timer Resource
  • 15.2 CCP2 Module
  • 15.3 Capture Mode
    • 15.3.1 CCP pin Configuration
    • 15.3.2 Timer1 Mode Selection
    • 15.3.3 Software Interrupt
    • 15.3.4 CCP Prescaler
      • EXAMPLE 15-1: Changing Between Capture Prescalers
      • FIGURE 15-1: Capture Mode Operation Block Diagram
  • 15.4 Compare Mode
    • 15.4.1 CCP Pin Configuration
    • 15.4.2 Timer1 Mode Selection
    • 15.4.3 Software Interrupt Mode
    • 15.4.4 Special Event Trigger
      • FIGURE 15-2: Compare Mode Operation Block Diagram
      • TABLE 15-2: Registers Associated with Capture, compare and Timer1
  • 15.5 PWM Mode
    • FIGURE 15-3: Simplified PWM Block Diagram
    • FIGURE 15-4: PWM Output
    • 15.5.1 PWM period
      • EQUATION 15-1:
    • 15.5.2 PWM Duty Cycle
      • EQUATION 15-2:
      • EQUATION 15-3:
    • 15.5.3 Setup for PWM Operation
      • TABLE 15-3: Example PWM Frequencies and Resolutions at 40 MHz
      • TABLE 15-4: Registers Associated with PWM and Timer2
• 16.0 Motion Feedback Module
  • TABLE 16-1: Summary of Motion Feedback Module Features
  • FIGURE 16-1: Motion Feedback Module Block diagram
  • 16.1 Input Capture
    • FIGURE 16-2: Input Capture Block diagram for IC1
    • FIGURE 16-3: Input Capture Block diagram for IC2 and IC3
    • Register 16-1: CAPxCON: Input Capture Control Register
    • 16.1.1 EDGE CAPTURE MODE
      • FIGURE 16-4: Edge Capture mode timing
    • 16.1.2 PERIOD MEASUREMENT MODE
    • 16.1.3 PULSE WIDTH MEASUREMENT MODE
      • FIGURE 16-5: Pulse Width measurement mode timing
    • 16.1.4 INPUT CAPTURE ON STATE CHANGE
      • FIGURE 16-6: Input CApture on state change (Hall-effect sensor mode)
    • 16.1.5 ENTERING INPUT CAPTURE MODE AND CAPTURE TIMING
    • 16.1.6 Timer5 Reset
    • 16.1.7 IC Interrupts
      • FIGURE 16-7: CAPxIF interrupts and IC1 Special Event Trigger
    • 16.1.8 Special Event Trigger (CAP1 Only)
      • TABLE 16-2: Special Event trigger
    • 16.1.9 OPERATING MODES SUMMARY
    • 16.1.10 Other Operating Modes
      • TABLE 16-3: Input capture Time Base Reset summary
  • 16.2 Quadrature Encoder Interface
    • FIGURE 16-8: QEI Block Diagram
    • 16.2.1 QEI CONFIGURATION
      • Register 16-2: QEICON: Quadrature Encoder Interface Control Register
    • 16.2.2 QEI MODES
      • TABLE 16-4: QEI Modes
    • 16.2.3 QEI OPERATION
      • TABLE 16-5: direction of Rotation
    • 16.2.4 QEI INTERRUPTS
    • 16.2.5 QEI SAMPLE TIMING
      • FIGURE 16-9: QEI inputs when sampled by the filter (Divide Ratio = 1:1)
      • FIGURE 16-10: QEI module Reset Timing on Period Match
      • FIGURE 16-11: QEI module Reset timing with the INDEX input
    • 16.2.6 Velocity Measurement
      • TABLE 16-6: Velocity Pulses
      • FIGURE 16-12: Velocity Measurement Block diagram
      • FIGURE 16-13: Velocity measurement Timing(1)
  • 16.3 Noise Filters
    • Register 16-3: DFLTCON: Digital Filter Control Register
    • FIGURE 16-14: Filter timing diagram (clock divider = 1:1)
  • 16.4 IC and QEI Shared Interrupts
    • TABLE 16-7: Meaning of IC and QEI Interrupt Flags
  • 16.5 Operation in Sleep Mode
    • 16.5.1 3X INPUT CAPTURE IN Sleep MODE
    • 16.5.2 QEI IN Sleep MODE
      • TABLE 16-8: Registers associated with the Motion Feedback module
• 17.0 Power Control PWM Module
  • FIGURE 17-1: Power Control PWM Module Block Diagram
  • FIGURE 17-2: PWM Module Block Diagram, One Output Pair, Complementary Mode
  • FIGURE 17-3: PWM MOdule Block Diagram, One Output Pair, Independent Mode
  • 17.1 Control Registers
  • 17.2 Module Functionality
  • 17.3 PWM Time Base
    • FIGURE 17-4: PWM Time Base Block Diagram
    • Register 17-1: PTCON0: PWM Timer Control Register 0
    • Register 17-2: PTCON1: PWM Timer Control Register 1
    • Register 17-3: PWMCON0: PWM Control Register 0
    • Register 17-4: PWMCON1: PWM Control Register 1
    • 17.3.1 Free Running Mode
    • 17.3.2 Single-shot Mode
    • 17.3.3 Continuous Up/Down Counting Modes
    • 17.3.4 PWM Time Base Prescaler
      • TABLE 17-1: Minimum PWM frequency
    • 17.3.5 PWM Time Base Postscaler
  • 17.4 PWM Time Base Interrupts
    • 17.4.1 Interrupts in Free running mode
      • FIGURE 17-5: PWM Time Base Interrupt Timing, Free running Mode
    • 17.4.2 Interrupts in Single-shot mode
    • 17.4.3 Interrupts in Continuous up/down counting mode
      • FIGURE 17-6: PWM Time Base Interrupt Timing, Single Shot Mode
      • FIGURE 17-7: PWM Time Base Interrupts, Up/Down Counting Mode
    • 17.4.4 Interrupts in Double update mode
      • FIGURE 17-8: PWM Time Base Interrupts, Up/Down Counting Mode with Double Updates
  • 17.5 PWM Period
    • EQUATION 17-1: PWM Period for free running mode
    • EQUATION 17-2: PWM Period for Up/Down Counting Mode
    • EQUATION 17-3: PWM Resolution
    • TABLE 17-2: Example Pwm frequencies and resolutions
    • FIGURE 17-9: PWM Period Buffer Updates in Free Running Count Mode
    • FIGURE 17-10: PWM Period Buffer Updates In Up/Down Counting Modes
  • 17.6 PWM Duty Cycle
    • 17.6.1 PWM Duty Cycle registers
      • FIGURE 17-11: Duty Cycle Comparison
    • 17.6.2 DUTY CYCLE REGISTER BUFFERS
    • 17.6.3 Edge-Aligned PWM
      • FIGURE 17-12: Edge-Aligned PWM
      • FIGURE 17-13: Duty Cycle Update Times in Up/down Counting Mode
      • FIGURE 17-14: Duty Cycle Update Times in Up/down Counting Mode With Double Updates
    • 17.6.4 CENTER-ALIGNED PWM
      • FIGURE 17-15: Start of Center-Aligned PWM
    • 17.6.5 COMPLEMENTARY PWM OPERATION
      • FIGURE 17-16: Typical Load for Complementary PWM Outputs
  • 17.7 Dead Time Generators
    • 17.7.1 DEAD TIME Insertion
      • FIGURE 17-17: Dead Time Control Unit Block Diagram for One PWM Output Pair
      • FIGURE 17-18: Dead Time Insertion for Complementary PWM
      • Register 17-5: DTCON � Dead Time control Register
    • 17.7.2 DEAD TIME RANGES
    • 17.7.3 DECREMENTING THE DEAD TIME COUNTER
      • TABLE 17-3: EXample Dead Time Ranges
    • 17.7.4 DEAD TIME DISTORTION
  • 17.8 Independent PWM Output
    • 17.8.1 DUTY CYCLE ASSIGNMENT IN THE INDEPENDENT MODE
    • 17.8.2 PWM CHANNEL OVERRIDE
      • FIGURE 17-19: CENTER-CONNECTED LOAD
  • 17.9 Single-Pulse PWM Operation
  • 17.10 PWM Output Override
    • 17.10.1 COMPLEMENTARY OUTPUT MODE
    • 17.10.2 OVERRIDE SYNCHRONIZATION
      • FIGURE 17-20: Override Bits in Complementary Mode
    • 17.10.3 OUTPUT OVERRIDE EXAMPLES
      • Register 17-6: OVDCOND: Output Override control Register
      • Register 17-7: OVDCONS: Output state Register
      • FIGURE 17-21: PWM OUtput Override example #1
      • TABLE 17-4: PWM OUTput override example #1
      • TABLE 17-5: PWM OUTPUT OVERRIDE EXAMPLE #2
      • FIGURE 17-22: PWM OUTPUT OVERRIDE EXAMPLE #2
  • 17.11 PWM Output and Polarity Control
    • 17.11.1 OUTPUT PIN CONTROL
      • FIGURE 17-23: PWM I/O Pin Block Diagram
    • 17.11.2 OUTPUT POLARITY CONTROL
    • 17.11.3 PWM OUTPUT PIN Reset STATES
  • 17.12 PWM Fault Inputs
    • 17.12.1 FAULT PIN ENABLE BITS
    • 17.12.2 MFAULT INPUT MODES
    • 17.12.3 PWM OUTPUTS WHILE IN FAULT CONDITION
    • 17.12.4 PWM OUTPUTS IN debug mode
      • Register 17-8: FLTCONFIG: Fault Configuration Register
  • 17.13 PWM Update Lockout
  • 17.14 PWM Special Event Trigger
    • 17.14.1 SPECIAL EVENT TRIGGER ENABLE
    • 17.14.2 SPECIAL EVENT TRIGGER POSTSCALER
      • TABLE 17-6: Registers Associated with the Power Control PWM Module
• 18.0 Synchronous Serial Port (SSP) Module
  • 18.1 SSP Module Overview
  • 18.2 SPI Mode
    • Register 18-1: SSPSTAT: Sync Serial Port Status Register (ADDRESS 94h)
    • Register 18-2: SSPCON: Sync Serial Port Control Register (Address 14h)
    • FIGURE 18-1: SSP Block Diagram (SPIMode)
    • FIGURE 18-2: SPI Mode Timing, Master Mode
    • FIGURE 18-3: SPI Mode Timing (Slave Mode With CKE=0)
    • FIGURE 18-4: SPI Mode Timing (Slave Mode With CKE=1)
    • TABLE 18-1: Registers Associated with SPI Operation
  • 18.3 SSP I2C Operation
    • FIGURE 18-5: SSP Block Diagram (I2C Mode)
    • 18.3.1 SLAVE Mode
      • TABLE 18-2: Data Transfer Received Byte Actions
      • FIGURE 18-6: I2C Waveforms for Reception (7-bit Address)
      • FIGURE 18-7: I2C Waveforms for Transmission (7-bit Address)
    • 18.3.2 Master Mode
    • 18.3.3 Multi-master Mode
      • TABLE 18-3: Registers Associated with I2C Operation
• 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
  • 19.1 Asynchronous Operation in Power-Managed Modes
    • Register 19-1: TXSTA: Transmit Status and Control Register
    • Register 19-2: RCSTA: Receive Status and Control Register
    • Register 19-3: BAUDCTL: Baud Rate Control Register
  • 19.2 USART Baud Rate Generator (BRG)
    • 19.2.1 POWER-MANAGED Mode Operation
    • 19.2.2 SAMPLING
      • TABLE 19-1: Baud rate Formulas
      • EXAMPLE 19-1: Calculating Baud Rate Error
      • TABLE 19-2: Registers Associated with Baud Rate Generator
      • TABLE 19-3: BAUD Rates for Asynchronous Modes
    • 19.2.3 Auto-Baud Rate Detect
      • TABLE 19-4: BRG Counter Clock Rates
      • FIGURE 19-1: Automatic Baud Rate Calculation
  • 19.3 USART Asynchronous Mode
    • 19.3.1 USART Asynchronous Transmitter
      • FIGURE 19-2: USART Transmit Block Diagram
      • FIGURE 19-3: Asynchronous Transmission
      • FIGURE 19-4: Asynchronous Transmission (Back to Back)
      • TABLE 19-5: Registers Associated with Asynchronous Transmission
    • 19.3.2 USART Asynchronous Receiver
    • 19.3.3 Setting up 9-bit mode with address detect
      • FIGURE 19-5: USART Receive Block Diagram
      • FIGURE 19-6: Asynchronous Reception
      • TABLE 19-6: Registers Associated with Asynchronous Reception
    • 19.3.4 Auto-Wake-up on SYNC BREAK Character
      • FIGURE 19-7: Auto-Wake-Up bit (WUE) timings during normal operation
      • FIGURE 19-8: Auto-Wake-Up bit (WUE) timings during Sleep
    • 19.3.5 BREAK Character Sequence
    • 19.3.6 Receiving a BREAK Character
      • FIGURE 19-9: Send BREAK Character Sequence
  • 19.4 USART Synchronous Master Mode
    • 19.4.1 USART Synchronous Master Transmission
      • FIGURE 19-10: Synchronous Transmission
      • FIGURE 19-11: Synchronous Transmission (Through TXEN)
      • TABLE 19-7: Registers Associated with Synchronous Master Transmission
    • 19.4.2 USART Synchronous Master Reception
      • FIGURE 19-12: Synchronous Reception (Master Mode, SREN)
      • TABLE 19-8: Registers Associated with Synchronous Master Reception
  • 19.5 USART Synchronous Slave Mode
    • 19.5.1 USART Synchronous Slave Transmit
      • TABLE 19-9: Registers Associated with Synchronous Slave Transmission
    • 19.5.2 USART Synchronous Slave Reception
      • TABLE 19-10: Registers Associated with Synchronous Slave Reception
• 20.0 10-bit High-Speed Analog-to-Digital Converter (A/D) Module
  • Register 20-1: ADCON0: A/D Control Register 0
  • Register 20-2: ADCON1: A/D Control Register 1
  • Register 20-3: ADCON2 � A/D Control Register 2
  • Register 20-4: ADCON3: A/D Control Register 3
  • Register 20-5: ADCHS: A/D Channel Select Register
  • Register 20-6: ANSEL0: Analog Select Register 0(1)
  • Register 20-7: ANSEL1: Analog Select Register 1(1)
  • FIGURE 20-1: A/D Block Diagram
  • 20.1 Configuring the A/D Converter
    • TABLE 20-1: auto-conversion Sequence configurations
    • 20.1.1 Conversion Type
    • 20.1.2 Conversion Mode
    • 20.1.3 Conversion Sequencing
    • 20.1.4 Triggering A/D Conversions
    • 20.1.5 A/D Module Initialization Steps
  • 20.2 A/D Result Buffer
  • 20.3 A/D Acquisition Requirements
    • EQUATION 20-1: Acquisition Time
    • EQUATION 20-2: Minimum A/D Holding Capacitor Charging Time
    • EXAMPLE 20-1: Calculating the Minimum Required Acquisition Time
    • FIGURE 20-2: Analog Input Model
  • 20.4 A/D Voltage References
  • 20.5 Selecting and Configuring Automatic Acquisition Time
  • 20.6 Selecting the A/D Conversion Clock
    • TABLE 20-2: Tad vs. Device Operating Frequencies
  • 20.7 Operation in Power-Managed Modes
  • 20.8 Configuring Analog Port Pins
  • 20.9 A/D Conversions
    • FIGURE 20-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, TACQ = 0)
    • FIGURE 20-4: A/D Conversion Tad Cycles (ACQT<3:0> = 0010, TACQ = 4 TAD)
    • 20.9.1 A/D Result Register
      • FIGURE 20-5: A/D Result Justification
      • EQUATION 20-3: Conversion Time for Multichannel Modes
      • TABLE 20-3: Summary of A/D Registers
• 21.0 Low-Voltage Detect
  • FIGURE 21-1: Typical Low-Voltage Detect Application
  • FIGURE 21-2: Low-Voltage Detect (LVD) Block Diagram
  • FIGURE 21-3: LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
  • 21.1 Control Register
    • Register 21-1: LVDCON Register
  • 21.2 Operation
    • FIGURE 21-4: Low-Voltage Detect waveforms
    • 21.2.1 Reference Voltage Set Point
    • 21.2.2 Current Consumption
  • 21.3 Operation During Sleep
  • 21.4 Effects of a Reset
• 22.0 Special Features of the CPU
  • 22.1 Configuration Bits
    • TABLE 22-1: Configuration bits and Device IDs
    • Register 22-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
    • Register 22-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
    • Register 22-3: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
    • Register 22-4: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)
    • Register 22-5: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
    • Register 22-6: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)
    • Register 22-7: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)
    • Register 22-8: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)
    • Register 22-9: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)
    • Register 22-10: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)
    • Register 22-11: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)
    • Register 22-12: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)
    • Register 22-13: DEVICE ID REGISTER 1 FOR PIC18F2331/2431/4331/4431 DEVICEs
    • Register 22-14: DEVICE ID REGISTER 2 FOR PIC18F2331/2431/4331/4431 DEVICEs
  • 22.2 Watchdog Timer (WDT)
    • 22.2.1 Control Register
      • FIGURE 22-1: WDT Block Diagram
      • Register 22-15: WDTCON Register
      • TABLE 22-2: Summary of Watchdog Timer Registers
  • 22.3 Two-Speed Start-up
    • 22.3.1 Special Considerations for Using Two-Speed Start-up
      • FIGURE 22-2: Timing Transition for Two-speed Start-up (INTOSC to HSPLL)
  • 22.4 Fail-Safe Clock Monitor
    • FIGURE 22-3: FSCM Block Diagram
    • 22.4.1 FSCM and the Watchdog Timer
    • 22.4.2 Exiting Fail-Safe Operation
      • FIGURE 22-4: FSCM Timing Diagram
    • 22.4.3 FSCM Interrupts in Power- Managed Modes
    • 22.4.4 POR or Wake From Sleep
  • 22.5 Program Verification and Code Protection
    • FIGURE 22-5: Code-Protected program memory FOR PIC18F2331/2431/4331/4431
    • TABLE 22-3: Summary of Code Protection Registers
    • 22.5.1 Program Memory code Protection
      • FIGURE 22-6: Table Write (WRTn) Disallowed
      • FIGURE 22-7: External Block Table Read (EBTRn) Disallowed
      • FIGURE 22-8: External Block Table Read (EBTRn) Allowed
    • 22.5.2 Data EEPROM Code Protection
    • 22.5.3 Configuration Register Protection
  • 22.6 ID Locations
  • 22.7 In-Circuit Serial Programming
  • 22.8 In-Circuit Debugger
    • TABLE 22-4: Debugger Resources
  • 22.9 Low-Voltage ICSP Programming
• 23.0 Instruction Set Summary
  • 23.1 READMODIFY-WRITE OPERATIONS
    • TABLE 23-1: Opcode Field Descriptions
    • FIGURE 23-1: General Format for Instructions
    • TABLE 23-2: PIC18FXXX Instruction Set 
  • 23.2 Instruction Set
• 24.0 Development Support
  • 24.1 MPLAB Integrated Development Environment Software
  • 24.2 MPASM Assembler
  • 24.3 MPLAB C17 and MPLAB C18 C Compilers
  • 24.4 MPLINK Object Linker/ MPLIB Object Librarian
  • 24.5 MPLAB C30 C Compiler
  • 24.6 MPLAB ASM30 Assembler, Linker, and Librarian
  • 24.7 MPLAB SIM Software Simulator
  • 24.8 MPLAB SIM30 Software Simulator
  • 24.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator
  • 24.10 MPLAB ICE 4000 High Performance Universal In-Circuit Emulator
  • 24.11 MPLAB ICD 2 In-Circuit Debugger
  • 24.12 PRO MATE II Universal Device Programmer
  • 24.13 PICSTART Plus Development Programmer
  • 24.14 PICDEM 1 PICmicro Demonstration Board
  • 24.15 PICDEM.net Internet/Ethernet Demonstration Board
  • 24.16 PICDEM 2 Plus Demonstration Board
  • 24.17 PICDEM 3 PIC16C92X Demonstration Board
  • 24.18 PICDEM 4 8/14/18-Pin Demonstration Board
  • 24.19 PICDEM 17 Demonstration Board
  • 24.20 PICDEM 18R PIC18C601/801 Demonstration Board
  • 24.21 PICDEM LIN PIC16C43X Demonstration Board
  • 24.22 PICkitTM 1 Flash Starter Kit
  • 24.23 PICDEM USB PIC16C7X5 Demonstration Board
  • 24.24 Evaluation and Programming Tools
• 25.0 Electrical Characteristics
  • Absolute Maximum Ratings (�)
    • FIGURE 25-1: PIC18F2331/2431/4331/4431 Voltage-Frequency Graph (Industrial)
    • FIGURE 25-2: PIC18LF2331/2431/4331/4431 Voltage-Frequency Graph (Industrial)
  • 25.1 DC Characteristics: Supply Voltage PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2...
  • 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Ext...
  • 25.3 DC Characteristics: PIC18F2331/2431/4331/4431 (Industrial) PIC18LF2331/2431/4331/4431 (Indus...
    • TABLE 25-1: Memory Programming Requirements
    • FIGURE 25-3: Low-Voltage Detect Characteristics
    • TABLE 25-2: Low-Voltage Detect Characteristics
  • 25.4 AC (Timing) Characteristics
    • 25.4.1 Timing Parameter Symbology
    • 25.4.2 Timing Conditions
      • TABLE 25-3: Temperature and Voltage Specifications - AC
      • FIGURE 25-4: Load Conditions for Device Timing Specifications
    • 25.4.3 Timing Diagrams and Specifications
      • FIGURE 25-5: External Clock Timing (All Modes Except PLL)
      • TABLE 25-4: External Clock Timing Requirements
      • TABLE 25-5: PLL Clock Timing Specifications (Vdd = 4.2V to 5.5V)
      • TABLE 25-6: Internal RC accuracy PIC18F2331/2431/4331/4431 (Industrial) PIC18LF2331/2431/4331/443...
      • FIGURE 25-6: CLKO and I/O Timing
      • TABLE 25-7: CLKO and I/O Timing Requirements
      • FIGURE 25-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
      • FIGURE 25-8: Brown-out Reset Timing
      • TABLE 25-8: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset ...
      • FIGURE 25-9: Timer0 and Timer1 External Clock Timings
      • TABLE 25-9: Timer0 and Timer1 External Clock Requirements
      • FIGURE 25-10: Capture/Compare/PWM Timings (aLL ccp mODULES)
      • TABLE 25-10: Capture/Compare/PWM Requirements (aLL ccp mODULES)
      • FIGURE 25-11: Example SPI Master Mode Timing (CKE=0)
      • TABLE 25-11: Example SPI Mode Requirements (Master Mode, CKE=0)
      • FIGURE 25-12: Example SPI Master Mode Timing (CKE=1)
      • TABLE 25-12: Example SPI Mode Requirements (Master Mode, CKE=1)
      • FIGURE 25-13: Example SPI Slave Mode Timing (CKE=0)
      • TABLE 25-13: Example SPI Mode Requirements (Slave Mode Timing (CKE=0))
      • FIGURE 25-14: Example SPI Slave Mode Timing (CKE=1)
      • TABLE 25-14: Example SPI Slave Mode Requirements (CKE=1)
      • FIGURE 25-15: I2C Bus Start/Stop Bits Timing
      • TABLE 25-15: I2C Bus Start/Stop Bits Requirements (Slave Mode)
      • FIGURE 25-16: I2C Bus Data Timing
      • TABLE 25-16: I2C Bus Data Requirements (Slave Mode)
      • FIGURE 25-17: SSP I2C Bus Start/Stop Bits Timing Waveforms
      • TABLE 25-17: SSP I2C Bus Start/Stop Bits Requirements
      • FIGURE 25-18: SSP I2C Bus Data Timing
      • TABLE 25-18: SSP I2C Bus Data Requirements
      • FIGURE 25-19: USART Synchronous Transmission (Master/Slave) Timing
      • TABLE 25-19: USART Synchronous Transmission Requirements
      • FIGURE 25-20: USART Synchronous Receive (Master/Slave) Timing
      • TABLE 25-20: USART Synchronous Receive Requirements
      • TABLE 25-21: A/D Converter Characteristics: PIC18F2331/2431/4331/4431 (Industrial) PIC18LF2331/24...
• 26.0 Preliminary DC and AC Characteristics Graphs and Tables
• 27.0 Packaging Information
  • 27.1 Package Marking Information
  • 27.2 Package Details
  • 28-Lead Skinny Plastic Dual In-line (SP) � 300 mil (PDIP)
  • 28-Lead Plastic Small Outline (SO) �Wide, 300 mil (SOIC)
  • 40-Lead Plastic Dual In-line (P) � 600 mil (PDIP)
  • 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
  • 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
• Appendix A: Revision History
  • Revision A (June 2003)
  • Revision B (December 2003)
• Appendix B: Device Differences
  • TABLE B-1: Device Differences
• Appendix C: Conversion Considerations
• Appendix D: Migration from Baseline to Enhanced Devices
• Appendix E: Migration from Mid-range to Enhanced Devices
• Appendix F: Migration from High-end to Enhanced Devices
• INDEX
• On-Line Support
  • Connecting to the Microchip Internet Web Site
• Systems Information and Upgrade Hot Line
• Reader Response
• Product Identification System
  • Sales and Support
• Worldwide Sales and Service