Document Outline

• Broadband Access Multiplexer (BAM)
• Contents
• Figures
• Tables
• 1.0 Product Description
  • 1.1 Overview
  • 1.2 Line Side Interfaces
    • 1.2.1 Line Side Serial Interface
    • 1.2.2 SONET Interleave Bus (SI-Bus) Interface
  • 1.3 System Side Interfaces�Time Slot Bus (TSB)
  • 1.4 Supported Multiplexing
  • 1.5 Supported Mapping
  • 1.6 Embedded Framers
    • Table 1-1. Number of Framer Blocks
  • 1.7 Supported Through-Paths
    • Figure 1-1. Supported SDH Mappings
    • Figure 1-2. Supported SONET Mappings
    • Figure 1-3. Device Partitioning of SONET/SDH Path Overhead Bytes
    • 1.7.1 Commonly Used Through-Paths
      • Table 1-2. SI-Bus Line Interface Supported Through-Paths
      • Table 1-3. Serial Line Interface Supported Through-Paths (1 of 2)
    • 1.7.2 Other Supported Through-Paths
      • Table 1-4. SI-Bus Line Interface Supported Through-Paths
      • Table 1-5. Serial Line Interface Supported Through-Paths
  • 1.8 Applications
    • 1.8.1 OC-12/STM-4 Path Termination for HDLC Application
      • Figure 1-4. OC-12/STM-4 Application
    • 1.8.2 OC-3/STM-1 Path Termination for HDLC Application
      • Figure 1-5. OC-3/STM-1 Application
    • 1.8.3 DS3/E3 Path Termination for HDLC Application
      • Figure 1-6. DS3/E3 Application
  • 1.9 Pin Assignments
    • Figure 1-7. CX29503 324-pin TBGA Pinout Diagram
    • Table 1-6. Pin Assignments (1 of 4)
    • Table 1-7. Pin Type Definitions
    • Table 18. Pin Definitions(1 of 6)
• 2.0 Functional Description
  • 2.1 CX29503 Block Diagram
    • Figure 2-1. CX29503 Top-Level Block Diagram
  • 2.2 CX29503 Detailed Block Diagram
    • Figure 2-2. Mapper/Multiplexer (MUX) Block Diagram
  • 2.3 Top-Level MUX
  • 2.4 Global Control and Status Block
  • 2.5 SONET Interleave Bus (SI-Bus)
    • Figure 2-3. SI-Bus Reference Model
    • 2.5.1 SI-Bus Operation
      • Figure 2-4. SI-Bus Unit of Transfer (3 Interleaved STS-1 Frames)
      • 2.5.1.1 Transmit Interface
        • Figure 2-5. SI-Bus Transmit Signal Relationship
      • 2.5.1.2 Receive Interface
        • Figure 2-6. SI-Bus Receive Signal Relationship
    • 2.5.2 CX29503 Connection to CX29610
      • Figure 2-7. Interconnection Between CX29503 and CX29610
  • 2.6 SONET/SDH Mapper/Multiplexer (MUX) Block
    • Figure 2-8. SONET/SDH Mapper/MUX Functional Block Diagram
    • 2.6.1 SONET/SDH Mapper/MUX Receiver
      • 2.6.1.1 SI-Bus Receiver Interface
      • 2.6.1.2 STS-1/TUG-3 SPE Extraction Control
      • 2.6.1.3 DS3/E3 Demapping Function
      • 2.6.1.4 DS3/E3 Smoothing Function
      • 2.6.1.5 VT Extraction Control
      • 2.6.1.6 VT Performance Monitoring
        • Table 2-1. VT Overhead Bytes and Associated Registers
        • Table 2-2. VT Start/End Events and Associated Registers
        • Table 2-3. VT One �Shot Events� and Associated Registers
      • 2.6.1.7 VT Path Conditioning
      • 2.6.1.8 DS1/E1 Demapping Function
      • 2.6.1.9 Receive Time Slot Bus Interface
    • 2.6.2 SONET/SDH Mapper/MUX Transmitter
      • 2.6.2.1 SI-Bus Transmitter Interface
      • 2.6.2.2 STS-1/TUG-3 Overhead Insertion
      • 2.6.2.3 VT Build and VT Overhead Insertion
      • 2.6.2.4 DS3/E3 Mapping Function
      • 2.6.2.5 DS1/E1 Mapping Function
      • 2.6.2.6 Transmit Time Slot Bus (TSB) Interface
    • 2.6.3 SONET/SDH Transmitter to Receiver Loopback Control
  • 2.7 DS3/E3 Framer Block
    • Figure 2-9. DS3/E3 Framer Block Diagram
  • 2.8 DS1/E1 Framer Block
    • Figure 2-10. DS1/E1 Framer Core Block Diagram
    • 2.8.1 Module Functions
      • Table 2-4. DS1 Mode In-Frame and Out-of-Frame Criteria
      • Table 2-5. E1 Mode In-Frame and Out-of-Frame Criteria
  • 2.9 M13/E13 Multiplexer (MUX) Block
    • Figure 2-11. M13/E13 Functional Block Diagram
    • 2.9.1 Operational Features Specification
  • 2.10 Time Slot Bus (TSB) Interface
    • Figure 2-12. CX29503 Time Slot Bus Interface
    • Figure 2-13. TSB Interface Block Diagram
    • Table 2-6. TSB Bandwidths
    • 2.10.1 Summary of Payload TSB
      • Figure 2-14. TSB Payload Time Slot Diagram
    • 2.10.2 Summary of Overhead TSB
      • Figure 2-15. TSB Overhead Time Slot Diagram
    • 2.10.3 TSB Signals
      • Figure 2-16. TSB Interface Pins
    • 2.10.4 Details of Payload TSB
      • 2.10.4.1 Data Path Signals
      • 2.10.4.2 Stuff Byte Compensation
        • Table 2-7. TSB Data Paths and Bus Rates
      • 2.10.4.3 Mapping of Payload to TSB Payload Time Slots
        • Table 2-8. Mapping of CX29503 Data Paths To and From TSB Time Slots
        • Table 2-9. Mapping of Unchannelized STS-1 To and From TSB Time Slots
        • Table 2-10. Mapping of Unchannelized DS3 To and From TSB Time Slots in SI-Bus Mode
        • Table 2-11. Mapping of Unchannelized E3 To and From TSB Time Slots in SI-Bus Mode
    • 2.10.5 Details of Overhead TSB
      • 2.10.5.1 Overhead Data Path
      • 2.10.5.2 Overhead TSB Frame Stuff Byte Compensation
      • 2.10.5.3 Mapping of Overhead Data to Overhead TSB Time Slots
        • Table 2-12. Mapping of Data To and From Overhead TSB Time Slots (1 of 2)
      • 2.10.5.4 SONET Overhead Communication Channels
      • 2.10.5.5 SDH Overhead Communication Channels
      • 2.10.5.6 Electrical DS3 Serial Port Overhead Communication Channels
      • 2.10.5.7 Electrical E3 Serial Port Overhead Communication Channels
    • 2.10.6 Timing Details
      • 2.10.6.1 Payload Bus, AC Characteristics
        • Figure 2-17. Framing Strobe TSB_STB Relation to Time Slot N
        • Figure 2-18. Payload TSB Transmit Data (TSB_TDAT)
        • Figure 2-19. Payload TSB Transmit Stuff Indicator (TSB_TSTUFF)
        • Figure 2-20. TS Bus Interface to HDLC Controller Transmit Sync Timing
        • Figure 2-21. Payload TSB Receive Data (TSB_RDAT)
        • Figure 2-22. Payload TSB Receive Stuff Indicator (TSB_RSTUFF)
        • Figure 2-23. TS Bus Interface to HDLC Controller Receive Sync Timing
      • 2.10.6.2 Overhead Bus, AC Characteristics
• 3.0 Parallel Microprocessor Interface
  • 3.1 Address/Data Bus
  • 3.2 Bus Control Signals
  • 3.3 Interrupt and Control Signals
    • Figure 3-1. Top-Level Interrupt Structure
  • 3.4 Command and Status Processor (CSP)
    • Figure 3-2. Command and Status Processor (CSP) Block Diagram
• 4.0 Clock Sources and Clock Configurations
  • 4.1 DS3/E3 Framer Clock and Data Options on the Line Side
    • Figure 4-1. DS3/E3 Framer Clock and Data Paths on Line Side
  • 4.2 DS1/E1 Clock and Data Options
    • Figure 4-2. DS1/E1 Framer Clock and Data Paths
  • 4.3 SI-Bus Interface Mode
    • Table 4-1. SI-Bus Clock Sources in SI-Bus Interface Mode
    • 4.3.1 DS3/E3 Clock and Data Configurations (SI-Bus Interface Mode)
      • Table 4-2. DS3 Clock Sources and Configuration Bits in SI-Bus Interface Mode
      • Table 4-3. E3 Clock Sources and Configuration Bits in SI-Bus Interface Mode
    • 4.3.2 DS1/E1 Clock and Data Configurations (SI-Bus Interface Mode)
      • Table 4-4. DS1 Clock Sources and Configuration Bits in SI-Bus Interface Mode
      • Table 4-5. E1 Clock Sources and Configuration Bits in SI-Bus Interface Mode
  • 4.4 Serial DS3 Interface Mode
    • Table 4-6. DS3 Clock Sources and Configuration Bits in Serial DS3 Interface Mode
    • Table 4-7. DS1 Clock Sources and Configuration Bits in Serial DS3 Interface Mode
  • 4.5 Serial E3 Interface Mode
    • Table 4-8. E3 Clock Sources and Configuration Bits in Serial E3 Interface Mode
    • Table 4-9. E1 Clock Sources and Configuration Bits in Serial E3 Interface Mode
  • 4.6 Payload TSB and Overhead TSB Clocks
    • Figure 4-3. TSB Payload Clock and TSB Overhead Clock Sources
    • Table 4-10. Payload TSB Clock Configurations
    • Table 4-11. Overhead TSB Clock Configurations
  • 4.7 Command and Status Processor (CSP) and Microprocessor Clocks
    • Figure 4-4. CSP and Microprocessor Clock Sources
    • Table 4-12. CSP and Microprocessor Clock Configurations
  • 4.8 DS1/E1 System and Microprocessor Clocks
    • Figure 4-5. DS1/E1 System Clock and Microprocessor Clock Sources
    • Table 4-13. DS1/E1 System and DS1/E1 Microprocessor Clock Configurations
  • 4.9 One Hertz Clock
    • Table 4-14. Selections for the One Hertz Clock Source and CLK_1HZ Pin
• 5.0 Loopbacks
  • 5.1 DS3/E3 Framer and M13 MUX Loopbacks
    • Figure 5-1. DS3/E3 Loopback Definitions
  • 5.2 DS1/E1 Framer Loopbacks
    • Figure 5-2. DS1/E1 Framer Loopbacks
    • Table 5-1. Clock Sources for DS1/E1 Loopback Modes
  • 5.3 SI-Bus System Side Loopback
    • Figure 5-3. SI-Bus System Side Loopback
• 6.0 Path Conditioning
  • 6.1 STS-1 Path Conditioning
    • Table 6-1. STS-1 Path Conditioning
  • 6.2 DS3 Path Conditioning
    • Table 6-2. DS3 Path Conditioning
  • 6.3 E3 Path Conditioning
    • Table 6-3. E3 Path Conditioning
  • 6.4 DS2 Path Conditioning
    • Table 6-4. DS2 Path Conditioning
  • 6.5 E2 Path Conditioning
    • Table 6-5. E2 Path Conditioning
  • 6.6 VT Path Conditioning
    • Table 6-6. VT Path Conditioning
  • 6.7 DS1/E1 Path Conditioning
    • Table 6-7. DS1/E1 Path Conditioning
• 7.0 Register Map
  • 7.1 Top Level�CX29503 Register Map
    • Table 7-1. Top Level�CX29503 Register Map
  • 7.2 Single Mapper/MUX Block Register Map
    • Table 7-2. Single Mapper/MUX Register Map (1 of 3)
• 8.0 Register Description
  • 8.1 Global Control and Status
    • Table 8-1. Global Control and Status Block Register Map
    • 0x0000�Device Identification Register (DEV_ID)
    • 0x0001�Top Level Control Register (TOP_CTL_REG)
    • 0x0002�Top Level Interrupt Status Register (TOP_IRQ_STAT)
    • 0x0003�Top Level Interrupt Enable Register (TOP_IRQ_ENB)
    • 0x0004�DS1/E1 Framer Interrupt Request Register 1 (FR_IRR1)
    • 0x0005�DS1/E1 Framer Interrupt Status Register 2 (FR_IRR2)
    • 0x0006�DS1/E1 Framer Interrupt Request Register 3 (FR_IRR3)
    • 0x0007�DS1/E1 Framer Interrupt Request Register 4 (FR_IRR4)
    • 0x0008�DS1/E1 Framer Interrupt Enable Register 1 (FR_IE1)
    • 0x0009�DS1/E1 Framer Interrupt Enable Register 2 (FR_IE2)
    • 0x000A�DS1/E1 Framer Interrupt Enable Register 3 (FR_IE3)
    • 0x000B�DS1/E1 Framer Interrupt Enable Register 4 (FR_IE4)
    • 0x000C�Watchdog Interrupt Status Register 4 (WD_INT_STAT)
    • 0x000D�Watchdog Interrupt Enable Register (WD_INT_ENB)
    • 0x000E�Watchdog Control Register (WD_CTL)
  • 8.2 Time Slot Bus (TSB) Interface
    • Table 8-2. Top Level�TSB Module Register Map
    • 0x0100 to 0x01EC�Test Registers
    • 0x01ED � Unframed Link Control Register 1
    • 0x01EE � Unframed Link Control Register 2
    • 0x01EF � Unframed Link Control Register 3
    • 0x01F0 � Unframed Link Control Register 4
    • 0x01F1�Flush FIFO Register
    • 0x01F2�TSB FIFO Interrupt Status Register (Used for Diagnostics)
    • 0x01F3�TSB FIFO Interrupt Enable Register (Used for DS1 Diagnostics)
    • 0x01F4�Overflow Tx Payload FIFO Number Status Register (Used for Diagnostics)
    • 0x01F5�Underflow Tx Payload FIFO Number Status Register (Used for Diagnostics)
    • 0x01F6�Overflow Rx Payload FIFO Number Status Register (Used for Diagnostics)
    • 0x01F7�Underflow Rx Payload FIFO Number Status Register (Used for Diagnostics)
    • 0x01F8�Overflow Tx Overhead FIFO Number Status Register (Used for Diagnostics)
    • 0x01F9�Underflow Tx Overhead FIFO Number Status Register (Used for Diagnostics)
    • 0x01FA�Overflow Rx Overhead FIFO Number Status Register (Used for Diagnostics)
    • 0x01FB�Underflow Rx Overhead FIFO Number Status Register (Used for Diagnostics)
    • 0x01FC�TSB Module Operation
    • 0x01FE�Framer Set (FS) Configuration Register 1
    • 0x01FF�Framer Set (FS) Configuration Register 2
  • 8.3 DS1/E1 Framers
    • 8.3.1 DS1/E1 Framer Set Global Control and Status Register
      • Table 8-3. Summary of Global Control and Status Registers
      • 0x00�Framer Control Register 1 (FCR0)
      • 0x01�Framer Control Register 2 (FCR1)
    • 8.3.2 DS1/E1 Framer Control and Status Registers
      • Table 8-4. DS1/E1 Framer Block Register Map (1 of 4)
      • 8.3.2.1 Primary Control Registers
      • 0x01�Primary Control Register (CR0)
        • Table 8-5. Receiver Framer Modes
        • Table 8-6. Criteria for Loss/Recovery of Receive Framer Alignment (1 of 2)
      • 0x03�Interrupt Request Register (IRR)
        • Figure 8-1. DS1/E1 Framer Interrupt Structure
        • 8.3.2.2 Interrupt Status Registers
          • Table 8-7. Interrupt Status Register (ISR) Summary
      • 0x04�Alarm 1 Interrupt Status (ISR7)
      • 0x05�Alarm 2 Interrupt Status (ISR6)
      • 0x06�Error Interrupt Status (ISR5)
      • 0x07�Counter Overflow Interrupt Status (ISR4)
      • 0x08�Timer Interrupt Status (ISR3)
      • 0x09�Data Link 1 Interrupt Status (ISR2)
      • 0x0A�Data Link 2 Interrupt Status (ISR1)
      • 0x0B�Pattern Interrupt Status (ISR0)
        • 8.3.2.3 Interrupt Enable Registers (IER)
      • 0x0C�Alarm 1 Interrupt Enable Register (IER7)
      • 0x0D�Alarm 2 Interrupt Enable Register (IER6)
      • 0x0E�Error Interrupt Enable Register (IER5)
      • 0x0F�Count Overflow Interrupt Enable Register (IER4)
        • Table 8-8. Counter Overflow Behavior
      • 0x10�Timer Interrupt Enable Register (IER3)
      • 0x11�Data Link 1 Interrupt Enable Register (IER2)
      • 0x13�Pattern Interrupt Enable Register (IER0)
        • 8.3.2.4 Configuration Registers
      • 0x14�Loopback Configuration Register (LOOP)
      • 0x15�External Data Link Time Slot (DL3_TS)
        • Table 8-9. Odd/Even Frame Selection
        • Table 8-10. External Data Link Time Slot Selection
      • 0x16�External Data Link Bit (DL3_BIT)
        • Table 8-11. External Data Link Sa Byte Selection
      • 0x17�Offline Framer Status (FSTAT)
        • Table 8-12. Maximum Average Reframe Time (MART) and Framer Time-Out
      • 0x18�Programmable Input/Output (PIO)
      • 0x19�Programmable Output Enable (POE)
        • 8.3.2.5 Digital Receiver Registers
      • 0x40�Receiver Configuration (RCR0)
        • Table 8-13. Reframe Criteria
      • 0x41�Receive Test Pattern Configuration (RPATT)
        • Table 8-14. Receive PRBS Test Pattern Measurements
      • 0x42�Receive Loopback Code Detector Configuration (RLB)
      • 0x43�Loopback Activate Code Pattern (LBA)
      • 0x44�Loopback Deactivate Code Pattern (LBD)
      • 0x45�Receive Alarm Signal Configuration (RALM)
        • Table 8-15. Receive Yellow Alarm Set and Clear Criteria (1 of 2)
      • 0x46�Alarm/Error/Counter Latch Configuration (LATCH)
        • Table 8-16. Latch Counter intervals
        • Table 8-17. Error Latching Options
        • Table 8-18. Alarm Latching Options
      • 0x47�Alarm 1 Status (ALM1)
        • Table 8-19. Receive Yellow Alarm
        • Table 8-20. Receive Alarm Indication Signal (RAIS)
      • 0x48�Alarm 2 Status (ALM2)
      • 0x49�Alarm 3 Status (ALM3)
        • Table 8-21. SEF Criteria
        • Table 8-22. Loss Of Frame Alignment Criteria
        • 8.3.2.6 Performance Monitoring Registers
      • 0x50�Framing Bit Error Counter LSB (FERR)
      • 0x51�Framing Bit Error Counter MSB (FERR)
      • 0x52�CRC Error Counter LSB (CERR)
      • 0x53�vCRC Error Counter MSB (CERR)
      • 0x56�Far End Block Error Counter LSB (FEBE)
      • 0x57�Far End Block Error Counter MSB (FEBE)
      • 0x58�PRBS Bit Error Counter LSB (BERR)
      • 0x59�PRBS Bit Error Counter MSB (BERR)
      • 0x5A�SEF/FRED/COFA Alarm Counter (AERR)
        • 8.3.2.7 Receive Sa-Byte Buffers
      • 0x5B�Receive Sa4 Byte Buffer (RSA4)
      • 0x5C�Receive Sa5 Byte Buffer (RSA5)
      • 0x5D�Receive Sa6 Byte Buffer (RSA6)
      • 0x5E�Receive Sa7 Byte Buffer (RSA7)
      • 0x5F�Receive Sa8 Byte Buffer (RSA8)
        • 8.3.2.8 Digital Transmitter Registers
      • 0x70�Transmit Framer Configuration (TCR0)
        • Table 8-23. E1 Transmit Framer Modes (T1/E1N = 0)
        • Table 8-24. T1 Transmit Framer Modes (T1/E1N = 1)
      • 0x71�Transmitter Configuration (TCR1)
      • 0x72�Transmit Frame Format (TFRM)
      • 0x73�Transmit Error Insert (TERROR)
        • Table 8-25. Transmit COFA Injection Options
      • 0x74�Transmit Manual Sa-Byte/FEBE Configuration (TMAN)
        • Table 8-26. Manual Transmit FEBE Options
      • 0x75�Transmit Alarm Signal Configuration (TALM)
        • Table 8-27. Transmit Multiframe Yellow Alarm Options
        • Table 8-28. Transmit Upstream Alarm Indication Signal
      • 0x76�Transmit Test Pattern Configuration (TPATT)
        • Table 8-29. Transmit PRBS Test Pattern Measurements
      • 0x77�Transmit Inband Loopback Code Configuration (TLB)
      • 0x78�Transmit Inband Loopback Code Pattern (LBP)
        • 8.3.2.9 Transmit Sa-Byte Buffers
      • 0x7B�Transmit Sa4 Byte Buffer (TSA4)
      • 0x7C�Transmit Sa5 Byte Buffer (TSA5)
      • 0x7D�Transmit Sa6 Byte Buffer (TSA6)
      • 0x7E�Transmit Sa7 Byte Buffer (TSA7)
      • 0x7F�Transmit Sa8 Byte Buffer (TSA8)
        • 8.3.2.10 Bit-Oriented Protocol (BOP) Registers
      • 0xA0�Bit-Oriented Protocol (BOP) Transceiver
        • Table 8-30. RBOP Message Length
        • Table 8-31. TBOP Message Length
        • Table 8-32. TBOP Mode Description
      • 0xA1�Transmit BOP Code Word (TBOP)
      • 0xA2�Receive BOP code word (RBOP)
      • 0xA3�BOP Status (BOP_STAT)
        • 8.3.2.11 Data Link Registers
      • 0xA4�DL1 Time Slot Enable (DL1_TS)
        • Table 8-33. Data Link 1 Time Slot Selection
      • 0xA5�DL1 Bit Enable (DL1_BIT)
      • 0xA6�DL1 Control (DL1_CTL)
      • 0xA7�RDL 1 FIFO Fill Control (RDL1_FFC)
        • Table 8-34. Message Fill Limits
        • Table 8-35. Receive FIFO Threshold Selections
      • 0xA8�Receive Data Link FIFO 1 (RDL1)
      • 0xA9�RDL 1 Status (RDL1_STAT)
      • 0xAA�Performance Report Message (PRM)
        • Table 8-36. Performance Report Message (PRM) Structure
      • 0xAB�TDL 1 FIFO Empty Control (TDL1_FEC)
        • Table 8-37. TNEAR Interrupt Threshold
      • 0xAC�TDL 1 End Of Message Control (TDL1_EOM)
      • 0AD�Transmit Data Link FIFO 1 (TDL1)
      • 0xAE�TDL 1 Status (TDL1_STAT)
        • 8.3.2.12 Data Link Test Registers
      • 0xBA�DLINK Test Configuration (DL_TEST1)
      • 0xBB�DLINK Test Status (DL_TEST2)
      • 0xBC�DLINK Test Status (DL_TEST3)
      • 0xBD�DLINK Test Control 1 or Configuration 1 (DL_TEST4)
        • 8.3.2.13 Payload Loopback Status Register
      • 0xD9�Payload Loopback Status Register (PLB_STAT)
  • 8.4 M13/E13 Multiplexer/Demultiplexer (MUX/DEMUX)
    • Table 8-38. M13/E13 MUX/DEMUX Block Register Map (1 of 3)
    • Table 8-39. DS3/E3 Framer Register Map (1 of 3)
    • Table 8-40. DS2/E2 Framer/MUX Registers Map (1 of 4)
    • Table 8-41. M13/E13 Control Registers Map (1 of 5)
    • 8.4.1 M13/E13 Global Status and Control Registers
      • 0x5000�M13/E13 System Control Register
      • 0x5006�DS3/E3 Framer Control Register
      • 0x5007�M13 Interrupt Source Status Register
        • Figure 8-2. M13 MUX/DEMUX Interrupt Structure
        • Figure 8-3. M29503 Level 3 to Level 1 Multiplexing
        • Table 8-42. Cross-Reference: M13 Channel Number to DS1/E1 Framer Number
      • 0x500A�DS2/E2 Channel 2 Framer Control Register
      • 0x500B�DS2/E2 Channel 3 Framer Control Register
      • 0x500C�DS2/E2 Channel 4 Framer Control Register
      • 0x500D�DS2/E2 Channel 5 Framer Control Register
      • 0x500E�DS2/E2 Channel 6 Framer Control Register
      • 0x500F�DS2/E2 Channel 7 Framer Control Register
      • 0x5010�DS2/E2 Channel 1 Loopback Control Register
      • 0x5011�DS2/E2 Channel 2 Loopback Control Register
      • 0x5012�DS2/E2 Channel 3 Loopback Control Register
      • 0x5013�DS2/E2 Channel 4 Loopback Control Register
      • 0x5014�DS2/E2 Channel 5 Loopback Control Register
      • 0x5015�DS2/E2 Channel 6 Loopback Control Register
      • 0x5016 �DS2/E2 Channel 7 Loopback Control Register (Loopback Type 2 Control Registers)
      • 0x5017�M13/E13 Group 1 Interrupt Enable
      • 0x5018�M13/E13 Group 2 Interrupt Enable
      • 0x5019�M13/E13 Group 3 Interrupt Enable
      • 0x501A�M13/E13 Group 4 Interrupt Enable
      • 0x501B to 0x5036�M13/E13 Channel 1�28 Control Registers
      • 0x5037 to 0x5052�M13/E13 Channel 1�28 Line Loopback Control Registers (Loopback Type 4 Control Re...
    • 8.4.2 DS3/E3 Framer Registers
      • 0x5220�Mode Control Register
        • Table 8-43. Transmit Alarm Controls
        • Table 8-44. DS3/E3 Framing Mode Selection
      • 0x5221�Counter Interrupt Enable Register
      • 0x5222�Alarm Start Interrupt Enable Register
      • 0x5223�Alarm End Interrupt Enable Register
      • 0x5224�Feature1 Control Register
        • Table 8-45. DS3/E3 Framer Line Side Configurations
      • 0x5225�Feature2 Control Register
      • 0x5226�Feature3 Control Register
      • 0x5227�Feature4 Control Register
      • 0x5228�Feature5 Control Register
      • 0x5229�Transmit Overhead Insertion1 Control Register
        • Table 8-46. DS3-C Bit Parity/E3-G.751 Mode Field Interpretation
      • 0x522A�Transmit Overhead Insertion2 Control Register
        • Figure 8-4. TSB Module to DS3/E3 Module Interface
      • 0x522B�REXTCK Control Register
      • 0x522C�Receive Overhead Control Register
        • Table 8-47. Summary of RXGAPCK Options
      • 0x522D�Transmit Data Link Control Register
      • 0x522E�Transmit Data Link Threshold Control Register
      • 0x522F and 0x5230�Transmit Data Link Message Byte (Lower Address and Higher Address)
      • 0x5231�Receive Data Link Control Register
      • 0x5232�Receive Data Link Threshold Control Register
      • 0x5233�Transmit FEAC Channel Byte
      • 0x5240�DS3/E3 Maintenance Status Register
      • 0x5241�Interrupt Request Register (IRR)
        • Figure 8-5. DS3/E3 Framer Interrupt Structure
      • 0x5242�Counter Interrupt Status Register
      • 0x5243�Alarm Start Interrupt Status Register
      • 0x5244�Alarm End Interrupt Status Register
      • 0x5246�E3-G.832 MA Fields Status Register
      • 0x5247�E3-G.832 SSM Field Status Register
      • 0x5248�Transmit Data Link FEAC Interrupt Status Register (ISR)
      • 0x524B�Receive Data Link Interrupt Status Register (ISR)
      • 0x524C�Receive Data Link Message Byte
        • Table 8-48. Register Definitions (RxGoodBlk Set)
        • Table 8-49. Register Definition (RxGoodBlk Cleared)
      • 0x524F�Receive FEAC Byte
      • 0x5250�Receive FEAC Stack Byte
      • 0x5251�Receive FEAC Interrupt Status Register (SR17i)
      • 0x5252�Receive AIC Byte
      • 0x5260 and 0x5261�DS3/E3 Parity (P bits) Error Counter
      • 0x5262 and 0x5263�DS3 Parity Disagreement Counter
      • 0x5264 and 0x5265�DS3 X-Bit Disagreement Counter
      • 0x5266 and 0x5267�DS3/E3 Frame Error Counter
      • 0x5268 and 0x5269�DS3 Path Parity (CP bits) Error Counter
      • 0x526A and 0x526B�DS3/E3 FEBE Event Counter
      • 0x526C and 0x526D�DS3/E3 Excessive Zeros Counter (Ctr06i)
      • 0x526E, 0x526F, and 0x5270�DS3/E3 LCV Counter
    • 8.4.3 DS2/E2 Framer/MUX Registers
      • 0x5400�DS2/E2 Receiver Interrupt Enable
      • 0x5401�DS2/E2 Interrupt Status
      • 0x5402�DS2/E2 Framer Status
      • 0x5403�DS2/E2 Framer 1 Transmit Control Register
      • 0x5423�DS2/E2 Framer 2 Transmit Control Register
      • 0x5443�DS2/E2 Framer 3 Transmit Control Register
      • 0x5463�DS2/E2 Framer 4 Transmit Control Register
      • 0x5483�DS2/E2 Framer 5 Transmit Control Register
      • 0x54A3�DS2/E2 Framer 6 Transmit Control Register
      • 0x54C3�DS2/E2 Framer 7 Transmit Control Register
      • 0x5404�DS2/E2 Framer 1 Receive Control Register
      • 0x5424�DS2/E2 Framer 2 Receive Control Register
      • 0x5444�DS2/E2 Framer 3 Receive Control Register
      • 0x5464�DS2/E2 Framer 4 Receive Control Register
      • 0x5484�DS2/E2 Framer 5 Receive Control Register
      • 0x54A4�DS2/E2 Framer 6 Receive Control Register
      • 0x54C4�DS2/E2 Framer 7 Receive Control Register
      • 0x5405�DS2/E2 Framer 1 Counter/Loopback Interrupt Enable
      • 0x5425�DS2/E2 Framer 2 Counter/Loopback Interrupt Enable
      • 0x5445�DS2/E2 Framer 3 Counter/Loopback Interrupt Enable
      • 0x5465�DS2/E2 Framer 4 Counter/Loopback Interrupt Enable
      • 0x5485�DS2/E2 Framer 5 Counter/Loopback Interrupt Enable
      • 0x54A5�DS2/E2 Framer 6 Counter/Loopback Interrupt Enable
      • 0x54C5�DS2/E2 Framer 7 Counter/Loopback Interrupt Enable
      • 0x5406�DS2/E2 Framer 1 Alarm Start Interrupt Enable
      • 0x5426�DS2/E2 Framer 2 Alarm Start Interrupt Enable
      • 0x5446�DS2/E2 Framer 3 Alarm Start Interrupt Enable
      • 0x5466�DS2/E2 Framer 4 Alarm Start Interrupt Enable
      • 0x5486�DS2/E2 Framer 5 Alarm Start Interrupt Enable
      • 0x54A6�DS2/E2 Framer 6 Alarm Start Interrupt Enable
      • 0x54C6�DS2/E2 Framer 7 Alarm Start Interrupt Enable
      • 0x5407�DS2/E2 Framer 1 Alarm End Interrupt Enable
      • 0x5427�DS2/E2 Framer 2 Alarm End Interrupt Enable
      • 0x5447�DS2/E2 Framer 3 Alarm End Interrupt Enable
      • 0x5467�DS2/E2 Framer 4 Alarm End Interrupt Enable
      • 0x5487�DS2/E2 Framer 5 Alarm End Interrupt Enable
      • 0x54A7�DS2/E2 Framer 6 Alarm End Interrupt Enable
      • 0x54C7�DS2/E2 Framer 7 Alarm End Interrupt Enable
      • 0x5408�DS2/E2 Framer 1 Transmit FIFO Status
      • 0x5428�DS2/E2 Framer 2 Transmit FIFO Status
      • 0x5448�DS2/E2 Framer 3 Transmit FIFO Status
      • 0x5468�DS2/E2 Framer 4 Transmit FIFO Status
      • 0x5488�DS2/E2 Framer 5 Transmit FIFO Status
      • 0x54A8�DS2/E2 Framer 6 Transmit FIFO Status
      • 0x54C8�DS2/E2 Framer 7 Transmit FIFO Status
      • 0x5409�DS2/E2 Framer 1 Counter/Loopback Interrupt Status
      • 0x5429�DS2/E2 Framer 2 Counter/Loopback Interrupt Status
      • 0x5449�DS2/E2 Framer 3 Counter/Loopback Interrupt Status
      • 0x5469�DS2/E2 Framer 4 Counter/Loopback Interrupt Status
      • 0x5489�DS2/E2 Framer 5 Counter/Loopback Interrupt Status
      • 0x54A9�DS2/E2 Framer 6 Counter/Loopback Interrupt Status
      • 0x54C9�DS2/E2 Framer 7 Counter/Loopback Interrupt Status
      • 0x540A�DS2/E2 Framer 1 Alarm Start Interrupt Status
      • 0x542A�DS2/E2 Framer 2 Alarm Start Interrupt Status
      • 0x544A�DS2/E2 Framer 3 Alarm Start Interrupt Status
      • 0x546A�DS2/E2 Framer 4 Alarm Start Interrupt Status
      • 0x548A�DS2/E2 Framer 5 Alarm Start Interrupt Status
      • 0x54AA�DS2/E2 Framer 6 Alarm Start Interrupt Status
      • 0x54CA�DS2/E2 Framer 7 Alarm Start Interrupt Status
      • 0x540B�DS2/E2 Framer 1 Alarm End Interrupt Status
      • 0x542B�DS2/E2 Framer 2 Alarm End Interrupt Status
      • 0x544B�DS2/E2 Framer 3 Alarm End Interrupt Status
      • 0x546B�DS2/E2 Framer 4 Alarm End Interrupt Status
      • 0x548B�DS2/E2 Framer 5 Alarm End Interrupt Status
      • 0x54AB�DS2/E2 Framer 6 Alarm End Interrupt Status
      • 0x54CB�DS2/E2 Framer 7 Alarm End Interrupt Status
      • 0x540C�DS2/E2 Framer 1 Receive Frame Error Counter
      • 0x542C�DS2/E2 Framer 2 Receive Frame Error Counter
      • 0x544C�DS2/E2 Framer 3 Receive Frame Error Counter
      • 0x546C�DS2/E2 Framer 4 Receive Frame Error Counter
      • 0x548C�DS2/E2 Framer 5 Receive Frame Error Counter
      • 0x54AC�DS2/E2 Framer 6 Receive Frame Error Counter
      • 0x54CC�DS2/E2 Framer 7 Receive Frame Error Counter
      • 0x540D�DS2/E2 Framer 1 Receive M-Bit Error Counter
      • 0x542D�DS2/E2 Framer 2 Receive M-Bit Error Counter
      • 0x544D�DS2/E2 Framer 3 Receive M-Bit Error Counter
      • 0x546D�DS2/E2 Framer 4 Receive M-Bit Error Counter
      • 0x548D�DS2/E2 Framer 5 Receive M-Bit Error Counter
      • 0x54AD�DS2/E2 Framer 6 Receive M-Bit Error Counter
      • 0x54CD�DS2/E2 Framer 7 Receive M-Bit Error Counter
      • 0x540E�DS2/E2 Framer 1�7 Receive LOS Counter
      • 0x542E�DS2/E2 Framer 1�7 Receive LOS Counter
      • 0x544E�DS2/E2 Framer 1�7 Receive LOS Counter
      • 0x546E�DS2/E2 Framer 1�7 Receive LOS Counter
      • 0x548E�DS2/E2 Framer 1�7 Receive LOS Counter
      • 0x54AE�DS2/E2 Framer 1�7 Receive LOS Counter
      • 0x54CE�DS2/E2 Framer 1�7 Receive LOS Counter
      • 0x540F�DS2/E2 Framer 1 Receive Parity Error Counter (Lower Byte)
      • 0x542F�DS2/E2 Framer 2 Receive Parity Error Counter (Lower Byte)
      • 0x544F�DS2/E2 Framer 3 Receive Parity Error Counter (Lower Byte)
      • 0x546F�DS2/E2 Framer 4 Receive Parity Error Counter (Lower Byte)
      • 0x548F�DS2/E2 Framer 5 Receive Parity Error Counter (Lower Byte)
      • 0x54AF�DS2/E2 Framer 6 Receive Parity Error Counter (Lower Byte)
      • 0x54CF�DS2/E2 Framer 7 Receive Parity Error Counter (Lower Byte)
      • 0x5410�DS2/E2 Framer 1 Receive Parity Error Counter (Upper Byte)
      • 0x5430�DS2/E2 Framer 2 Receive Parity Error Counter (Upper Byte)
      • 0x5450�DS2/E2 Framer 3 Receive Parity Error Counter (Upper Byte)
      • 0x5470�DS2/E2 Framer 4 Receive Parity Error Counter (Upper Byte)
      • 0x5490�DS2/E2 Framer 5 Receive Parity Error Counter (Upper Byte)
      • 0x54B0�DS2/E2 Framer 6 Receive Parity Error Counter (Upper Byte)
      • 0x54D0�DS2/E2 Framer 7 Receive Parity Error Counter (Upper Byte)
      • 0x5411�DS2/E2 Framer 1 National Use Bit Status
      • 0x5431�DS2/E2 Framer 2 National Use Bit Status
      • 0x5451�DS2/E2 Framer 3 National Use Bit Status
      • 0x5471�DS2/E2 Framer 4 National Use Bit Status
    • 8.4.4 M13/E13 Control Registers
      • 0x5500� M13/E13 Interrupt Status Register 1
      • 0x5501�DS1/E1 MUX Interrupt Status Register 2
      • 0x5502�DS1/E1 MUX Interrupt Status Register 3
      • 0x5503�DS1/E1 MUX Interrupt Status Register 4
        • 8.4.4.1 DS1/E1 MUX Channel 1�28 Receive Interrupt Enable
          • Table 8-50. Register Offsets�DS1/E1 MUX Channel 1�28 Receive Interrupt Enable 
        • 8.4.4.2 DS1/E1 MUX Channel 1�28 Transmit FIFO Status
          • Table 8-51. Register Offsets�DS1/E1 MUX Channel 1�28 Transmit FIFO Status
        • 8.4.4.3 DS1/E1 MUX Channel 1�28 Receive Interrupt Status
          • Table 8-52. Register Offsets�DS1/E1 MUX Channel 1�28 Receive Interrupt Status
  • 8.5 SONET/SDH Block
    • Table 8-53. SONET/SDH Block Memory Map
    • 8.5.1 Initialization
    • 8.5.2 Software Configuration/Setup
      • 8.5.2.1 DS3 and E3 Modes
      • 8.5.2.2 Unchannelized STS-1/AU-3 or TUG-3 Mode
      • 8.5.2.3 DS1 or E1 Mode
    • 8.5.3 Interrupt Structures
      • Figure 8-6. SONET/SDH Interrupt Structure�Transmit Path
      • Figure 8-7. SONET/SDH Interrupt Structure�Receive Path
    • 8.5.4 General Control and Status Registers
      • Table 8-54. SONET/SDH General Control and Status Register (1 of 2)
      • 8.5.4.1 SONET/SDH Top Level Transmitter Control
      • 0x6000�Transmit SI-Bus Interrupt Enable
      • 0x6001�Transmit SI-Bus Status
      • 0x6004�BIP2 Error Pattern (Used for Diagnostics)
      • 0x6005�Transmit Microprocessor Interface Fast Access Control
      • 0x6007�SI-Bus Transmit to Receive Loopback Control
        • 8.5.4.2 SONET/SDH Level 3 Transmitter Interrupts
      • 0x6008�Transmit Channel Interrupt Enable (Channels 1�8)
      • 0x6009�Transmit Channel Interrupt Enable (Channels 9�16)
      • 0x600A�Transmit Channel Interrupt Enable (Channels 17�24)
      • 0x600B�Transmit Channel Interrupt Enable (Channels 17�24, STS, General)
      • 0x600C�Transmit Channel Status (Channels 1�8)
      • 0x600D�Transmit Channel Status (Channels 9�16)
      • 0x600E�Transmit Channel Status (Channels 17�24)
      • 0x600F�Transmit Channel Status (Channels 17�24, STS, General)
        • 8.5.4.3 SONET/SDH Top Level Receiver Control
      • 0x6080�Receive SI-Bus Interrupt Enable
      • 0x6081�Receive SI-Bus Status
      • 0x6082�SI-Bus Phase Identifier
      • 0x6084�Receive Status/Counter Latching Control
      • 0x6085�Receive Microprocessor Interface Fast Access Control
        • 8.5.4.4 SONET/SDH Level 3 Receiver Interrupts
      • 0x6088�Receive Channel Interrupt Enable (Channels 1�8)
      • 0x6089�Receive Channel Interrupt Enable (Channels 9�16)
      • 0x608A�Receive Channel Interrupt Enable (Channels 17�24)
      • 0x608B�Receive Channel Interrupt Enable (Channels 25�28, STS, General)
      • 0x608C�Receive Channel Status (Channels 1�8)
      • 0x608D�Receive Channel Status (Channels 9�16)
      • 0x608E�Receive Channel Status (Channels 17�24)
      • 0x608F�Receive Channel Status (Channels 25�28, STS, General)
    • 8.5.5 STS-1 Framer Section/Line Control/Status
      • Table 8-55. STS-1 Framer Section/Line Control/Status Registers
      • 0x6100�Transmit Transport Overhead Byte Insertion Control (TXTOHINS)
      • 0x6180�Receive Transport Overhead Byte Drop Control (RXTOHDROP)
    • 8.5.6 STS-1/AU�4/AU-3 and TU-3 Path Control/Status Registers
      • Table 8-56. STS-1/AU-4/AU-3 and TU-3 Path Control/Status Registers (1 of 4)
      • 8.5.6.1 Transmit STS-1/AU�4/AU-3 Overhead
      • 0x6200�Transmit Path Overhead Control
      • 0x6202�Transmit Path Overhead Byte Insertion Control (TXPOHINS)
      • 0x6207�Transmit Path F2 Overhead Byte (TXF2)
      • 0x6209�Transmit Path Z3/F3 Overhead Byte (TXF3)
      • 0x620A�Transmit Path Z4/K3 Overhead Byte (TXK3)
      • 0x620B�Transmit Path Z5/N1 Overhead Byte (TXN1)
        • 8.5.6.2 Transmit DS3/E3 Mapping FIFO
      • 0x620E�Transmit DS3/E3 Mapping FIFO Minimum Level (TXL3MAPMIN)
      • 0x620F�Transmit DS3/E3 Mapping FIFO Reset (TXL3MAPRST)
      • 0x6237�Transmit DS3/E3 Mapping FIFO Interrupt Enable
      • 0x623F�Transmit DS3/E3 Mapping FIFO Status, Diagnostic Only
        • 8.5.6.3 Transmit TU-3 Overhead
      • 0x6240�Transmit TU-3 Overhead Control
      • 0x6242�Transmit TU-3 Overhead Byte Insertion Control (TXTU3INS)
      • 0x6247�Transmit TU-3 F2 Overhead Byte (TXTRF2)
      • 0x6249�Transmit TU-3 Z3/F3 Overhead Byte (TXTRF3)
      • 0x624A�Transmit TU-3 Z4/K3 Overhead Byte (TXTRK3)
      • 0x624B�Transmit TU-3 Z5/N1 Overhead Byte (TXTRN1)
        • 8.5.6.4 Receive STS-1/AU-4/AU-3 Overhead
      • 0x6282�Receive Path Overhead Byte Drop Control
        • 8.5.6.5 Receive DS3/E3 Demapping FIFO
      • 0x628E�Receive DS3/E3 Demapping FIFO Minimum Level (RXL3DEMMIN)
      • 0x628F�Receive DS3/E3 Demap FIFO Reset (RXL3DEMRST)
        • 8.5.6.6 STS-1/AU-4/AU-3 Pointer Processing
      • 0x6294�Receive STS-1/AU-4/AU-3 Pointer Value (8 LSBits)
      • 0x6295�Receive STS-1/AU-4/AU-3 Pointer Status
      • 0x6296�Receive STS-1/AU-4/AU-3 Pointer Increment Counter LSB
      • 0x6297�Receive STS-1/AU-4/AU-3 Pointer Increment Counter MSB
      • 0x6298�Receive STS-1/AU-4/AU-3 Pointer Decrement Counter LSB
      • 0x6299�Receive STS-1/AU-4/AU-3 Pointer Decrement Counter MSB
        • 8.5.6.7 STS Path Level 2 Interrupts
      • 0x62B0�Receive STS Path Interrupt Source
        • 8.5.6.8 STS Path Level 1 Interrupts�STS-1/AU�4/AU-3
      • 0x62B3�Receive Path Start of Status Interrupt Enable 1
      • 0x62B4�Receive Path Start of Status Interrupt Enable 2
      • 0x62B5�Receive Path End of Status Interrupt Enable 1
      • 0x62B6�Receive Path End of Status Interrupt Enable 2
      • 0x62B7�Receive Path Event Status Interrupt Enable
      • 0x62B9�Receive Path Current Status 1
      • 0x62BA�Receive Path Current Status 2
      • 0x62BB�Receive Path Start of Status 1 (RXPSSTAT1)
      • 0x62BC�Receive Path Start of Status 2 (RXPSSTAT2)
      • 0x62BD�Receive Path End of Status 1 (RXPESTAT1)
      • 0x62BE�Receive Path End of Status 2 (RXPESTAT2)
      • 0x62BF�Receive Path Event Status (RXPEVSTAT)
        • 8.5.6.9 Receive TU-3 Overhead
      • 0x62C2�Receive TU-3 Overhead Byte Drop Control
        • 8.5.6.10 Receive TU-3 Pointer Processing
      • 0x62D4�Receive TU-3 Pointer Value (8 LSBits)
      • 0x62D5�Receive TU-3 Pointer Status
      • 0x62D6�Receive TU-3 Pointer Increment Counter LSB
      • 0x62D7�Receive TU-3 Pointer Increment Counter MSB
      • 0x62D8�Receive TU-3 Pointer Decrement Counter LSB
      • 0x62D9�Receive TU-3 Pointer Decrement Counter MSB
        • 8.5.6.11 STS Path Level 1 Interrupts�TU-3
      • 0x62F3�Receive TU-3 Start of Status Interrupt Enable
      • 0x62F5�Receive TU-3 End of Status Interrupt Enable
      • 0x62F7�Receive TU-3 Event Status Interrupt Enable
      • 0x62F9�Receive TU-3 Current Status
      • 0x62FB�Receive TU-3 Start of Status (RXTSSTAT)
      • 0x62FD�Receive TU-3 End of Status (RXTESTAT)
      • 0x62FF�Receive TU-3 Event Status (RXTEVSTAT)
    • 8.5.7 Mapping Control/Status Registers
      • Table 8-57. Mapping Control/Status Registers
      • 0x6380�Level 3 Mapping Control
        • Figure 8-8. SONET Data Path Control
      • 0x6388, 0x6389, 0x638A, 0x638B, 0x638C, 0x638D, and 0x638E�Group n Mapping Control
        • Table 8-58. Register Offsets�Group n Mapping Control
  • 8.6 VT/VC Mapper Control and Status
    • Table 8-59. Tributary Control/Status Registers (1 of 2)
    • 8.6.1 Transmit Tributary Processing
      • 0x00�VT#n Transmit Overhead Control 1 (TXVTCTL1)
        • Table 8-60. Effect of TrigRDI-V and RDIVMode on Trigger-Initiated Actions
      • 0x01�VT#n Transmit Overhead Control 2 (TXVTCTL2)
      • 0x02�VT#n Transmit Signal Label Control (TXVTLAB)
      • 0x03�VT#n Transmit J2 Trace Circular Buffer Address (TXJ2ADD)
      • 0x04�VT#n Transmit J2 Trace Circular Buffer Data (TXJ2DAT)
      • 0x05�VT#n Transmit Z6/N2 Overhead Byte (TXN2)
      • 0x06�VT#n Transmit Z7/K4 Overhead Byte (TXK4)
      • 0x0E�VT#n Transmit Mapping FIFO Minimum Level (TXL1MAPMIN)
      • 0x0F�VT#n Transmit Mapping FIFO Reset (TXL1MAPRST)
      • 0x37�VT#n Transmit Mapping FIFO Interrupt Enable (TXL1MAPINTEN)
      • 0x3F�VT#n Transmit Mapping FIFO Status (TXL1MAPINTEN), Diagnostic Only
    • 8.6.2 Receive Tributary Processing
      • 0x80�VT#n Receive Control (RXVTCTL)
      • 0x82�VT#n Receive Signal Label Status (RXVTLAB)
      • 0x83�VT#n Receive J2 Trace Circular Buffer Address (RXJ2ADD
      • 0x84�VT#n Receive J2 Trace Circular Buffer Data (RXJ2DAT)
      • 0x85�VT#n Receive Z6/N2 Overhead Status (RXN2)
      • 0x86�VT#n Receive Z7/K4 Overhead Status (RXK4)
      • 0x90�VT#n BIP2 Error Counter LSB (BIP2CNTL)
      • 0x91�VT#n BIP2 Error Counter MSB (BIP2CNTH)
      • 0x92�VT#n REI Error Counter LSB (REIVL)
      • 0x93�VT#n REI Error Counter MSB (REIVH)
      • 0x94�VT#n Receive Pointer Value, 8 LSBits (VTPTRL)
      • 0x95�VT#n Receive Pointer Status (VTPTRSTAT)
      • 0x96�VT#n Receive Pointer Increment Counter LSB (VTPJCNTL)
      • 0x97�VT#n Receive Pointer Increment Counter MSB (VTPJCNTH)
      • 0x98�VT#n Receive Pointer Decrement Counter LSB (VTNJCNTL)
      • 0x99�VT#n Receive Pointer Decrement Counter MSB (VTNJCNTH)
      • 0xB0�VT#n Receive VT Interrupt Source (RXVINTSRC)
      • 0xB3�VT#n Receive VT Start of Status Interrupt Enable 1 (RXVSINTEN1)
      • 0xB4�VT#n Receive VT Start of Status Interrupt Enable 2 (RXVSINTEN2)
      • 0xB5�VT#n Receive VT End of Status Interrupt Enable 1 (RXVEINTEN1)
      • 0xB6�VT#n Receive VT End of Status Interrupt Enable 2 (RXEINTEN2)
      • 0xB7�VT#n Receive VT Event Status Interrupt Enable (RXEVINTEN)
      • 0xB9�VT#n Receive VT Current Status 1 (RXVCSTAT1)
      • 0xBA�VT#n Receive VT Current Status 2 (RXVCSTAT2)
      • 0xBB�VT#n Receive VT Start of Status 1 (RXVSSTAT1)
      • 0xBC�VT#n Receive VT Start of Status 2 (RXVSSTAT2)
      • 0xBD�VT#n Receive VT End of Status 1 (RXVESTAT1)
      • 0xBE�VT#n Receive VT End of Status 2 (RXVESTAT2)
      • 0xBF�VT#n Receive VT Event Status (RXVEVSTAT)
  • 8.7 Command and Status Processor (CSP)
    • Table 8-61. CSP Control Registers (1 of 2)
    • 0x8000�General Purpose Register R0 (GEN_REG0)
    • 0x8001�General Purpose Register R1 (GEN_REG1)
    • 0x8002�General Purpose Register R2 (GEN_REG2)
    • 0x8003�General Purpose Register R3 (GEN_REG3)
    • 0x8004�Accumulator Register (ACC_REG)
    • 0x8005�Zero and Carry Flag Register (CTL_FLAGS)
    • 0x8006�Run and Download Configuration Register (RUN_CONFIG)
    • 0x8007�Instruction Address Low Byte (INS_ADDRL)
    • 0x8008�Instruction Address High Byte (INS_ADDRH)
    • 0x8009�Break 0 Address Low Byte (BRK0_ADDRL)
    • 0x800A�Break 0 Address High Byte (BRK0_ADDRH)
    • 0x800B�Break 1 Address Low Byte (BRK1_ADDRL)
    • 0x800C�Break 1 Address High Byte (BRK1_ADDRH)
    • 0x800D�Comm. Block Access Base Address Low Byte (CBLK_ADDRL)
    • 0x800E�Comm. Block Access Base Address High Byte (CBLK_ADDRH)
    • 0x800F�Comm. Block Access Offset Byte (N-Bit Counter) (CBLK_OFST)
    • 0x8010�Interrupt Control Register (INT_CTLR)
    • 0x8011�Real-Time Counter Period Detect Register (RT_CNTR)
    • 0x8012�Tx FIFO Status Register (TX_FIFO_STAT)
    • 0x8013�Rx FIFO Status Register (RX_FIFO_STAT)
    • 0x8014�CSP Device ID Byte (CSP_DEVID)
    • 0x8015�Interrupt 0 (One-Second) Source Priority Level (INTR0_PLVL)
    • 0x8016�Interrupt 1 (SMX-Rx) Source Priority Level (INTR1_PLVL)
    • 0x8017�Interrupt 2 (SMX-Tx) Source Priority Level (INTR2_PLVL)
    • 0x8018�Interrupt 3 (FR1) Source Priority Level (INTR3_PLVL)
    • 0x8019�Interrupt 4 (M13-MUX) Source Priority Level (INTR4_PLVL)
    • 0x801A�Interrupt 5 (M13-L3) Source Priority Level (INTR5_PLVL)
    • 0x801B�Interrupt 6 (TSB) Source Priority Level (INTR6_PLVL)
    • 0x801C�Period Compare Register Low Byte (PER_CMP_LO)
    • 0x801D�Period Compare Register Mid-Low Byte (PER_CMP_ML)
    • 0x801E�Period Compare Register Mid-High Byte (PER_CMP_MH)
    • 0x801F�Period Compare Register High Byte (PER_CMP_HI)
    • 0x8020�HDLC Controller Status (HDLC_STAT)
    • 0x8021�HDLC Transmit Message Length (HDLC_TX_LEN)
    • 0x8022�HDLC Received Message Length (HDLC_RX_LEN)
    • 0x8023�Parallel Interface Control (PAR_IF_CTL)
    • 0x8024�CSP Memory Offset (CSP_MM_OFST)
    • 0x8025�Watchdog Tickle Pattern (Low Byte) (TCKL_LO_ADDR)
    • 0x8026�Watchdog Tickle Pattern (High Byte) (TCKL_HI_ADDR)
    • 0x8027�Watchdog Time-Out Period (TIMO_LO_ADDR)
    • 0x8028�Watchdog Time-Out Period (TIMO_ML_ADDR)
    • 0x8029�Watchdog Time-Out Period (TIMO_MH_ADDR)
    • 0x802A�Watchdog Time-Out Period (TIMO_HI_ADDR)
  • 8.8 Clock and Test
    • Table 8-62. CLT Register Map
    • 0xA000�Clock Configuration
    • 0xA001�Test Bus Configuration (Used for Diagnostics)
• 9.0 Electrical and Mechanical Specifications
  • 9.1 Electrical Specification
    • 9.1.1 DC Characteristics
      • Table 9-1. Absolute Maximum Ratings Over Operating Free-Air Temperature Range
      • Table 9-2. Recommended DC Operating Conditions
      • Table 9-3. DC Characteristics Over Recommended Operating Conditions
    • 9.1.2 AC Characteristics
      • Figure 9-1. General Interface Timing Characteristics
      • Table 9-4. General Interface Timing Characteristics
      • Figure 9-2. SI-Bus Interface Timing Characteristics
      • Table 9-5. SI-Bus Interface Timing Characteristics (1 of 2)
      • Figure 9-3. TSB Interface Timing Characteristics
      • Table 9-6. TSB Interface Timing Characteristics
      • Figure 9-4. E-Bus Read Timing
      • Table 9-7. E-Bus Interface Read Timing Characteristics
      • Figure 9-5. E-Bus Write Timing
      • Table 9-8. E-Bus Interface Write Timing Characteristics
      • Figure 9-6. Serial DS3/E3 Interface Timing
      • Table 9-9. Serial DS3/E3 Interface Characteristics
  • 9.2 Mechanical Specification
    • Figure 9-7. CX29503 Tape Ball Grid Array (TBGA), 324-Pin, 31 x 31 mm, 1.0 mm Ball Pitch
• Appendix A: References
• Appendix B: Acronyms and Abbreviations
• Appendix C: Revision History