MOSEL VITELIC

V53C518160A
1M x 16 FAST PAGE MODE
CMOS DYNAMIC RAM

V53C518160A Rev. 1.3 March 1998

HIGH PERFORMANCE

Max. RAS Access Time, (t

RAC

)

50 ns

60 ns

Max. Column Address Access Time, (t

CAA

)

25 ns

30 ns

Min. Fast Page Mode Cycle Time, (t

)

35 ns

40 ns

Min. Read/Write Cycle Time, (t

)

90 ns

110 ns

Features

1MB x 16-bit organization

Fast Page Mode for a sustained data rate
of 29 MHz

RAS access time: 50, 60 ns

Dual CAS Inputs

Low power dissipation

Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Self Refresh
· Refresh Interval: 1024 cycles/16 ms

Available in 42-pin 400 mil SOJ and
44/50-pin 400 mil TSOP-II Packages

Single 5V

10% Power Supply

TTL Interface

Description

The V53C518160A is a 1048576 x 16 bit high-

performance CMOS dynamic random access
memory. The V53C518160A offers Fast Page
mode operation. The V53C518160A has symmet-
ric address, 10-bit row and 10-bit column.

All inputs are TTL compatible. Fast Page Mode

operation allows random access up to 1024 x 16
bits, within a page, with cycle times as short as
35ns.

These features make the V53C518160A ideally

suited for a wide variety of high performance com-
puter systems and peripheral applications.

Device Usage Chart

Operating

Temperature

Range

Package Outline

Access Time (ns)

Power

Temperature

Mark

Std.

C to 70

Blank

C to +85

V53C518160A Rev. 1.3 March 1998

MOSEL VITELIC

V53C518160A

Pin Names

Row, Column Address Inputs

RAS

Row Address Strobe

UCAS

Column Address Strobe/Upper Byte Control

LCAS

Column Address Strobe/Lower Byte Control

Write Enable

Output Enable

I/O

Data Input, Output

+5V Supply

0V Supply

No Connect

Description

Pkg.

Pin Count

TSOP-II

44/50

SOJ

I/O

VCC

I/O

NC
NC

RAS

NC
NC

I/O

NC
LCAS
UCAS
OE
A

5
6
7
8
9
10
11
12

1
2
3
4

40
39
38
37
36
35
34
33
32
31
30
29

13
14
15
16
17
18
19
20

28
27
26
25
24
23
22

I/O

VCC

I/O

NC
NC

RAS

NC
NC

I/O

NC
LCAS
UCAS
OE
A

5
6
7
8
9
10
11

1
2
3
4

15
16
17
18
19
20

511816500-02

21
22
23
24
25

46
45
44
43
42
41
40

50
49
48
47

36
35
34
33
32
31
30
29
28
27
26

42-Pin Plastic SOJ

PIN CONFIGURATION

Top View

44/50-Pin Plastic TSOP-II

PIN CONFIGURATION

Top View

V53C518160A Rev. 1.3 March 1998

MOSEL VITELIC

V53C518160A

Block Diagram

No. 2 Clock

Generator

Data In

Buffer

Data Out

Buffer

Column

Address

Buffers (10)

Refresh

Controller

Row

Decoder

Refresh

Counter (10)

Voltage Down

Generator

No. 1 Clock

Generator

Row

Address

Buffers (10)

I/O1 I/O2

I/O16

VCC
VCC (internal)

1024

x16

Memory Array

1024 x 1024 x 16

Sense Amplifier

I/O Gating

316516500-03

Column

Decoder

UCAS

LCAS

RAS

· · ·

Absolute Maximum Ratings*

Note:

Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

Capacitance*

= 25

C, V

= 5 V

10%, V

= 0 V, f = 1 MHz

Note:

Capacitance is sampled and not 100% tested.

Symbol

Parameter

Commercial

Extended

Units

Power Supply Voltage

-1 to +7

Input/Output Voltage

-0.5 to min (V

+0.5, 7.0)

-0.5 to min (V

+0.5, 7.0)

BIAS

Temperature Under Bias

-10 to +125

-65 to +135

STG

Storage Temperature

-55 to +125

-65 to +150

Symbol

Parameter

Min.

Max.

Unit

IN1

Address Input

IN2

RAS, UCAS, LCAS,
WE, OE

OUT

Data Input/Output

V53C518160A Rev. 1.3 March 1998

MOSEL VITELIC

V53C518160A

DC and Operating Characteristics

(1-2)

= 0

C to 70

C, V

= 5 V

10%, V

= 0 V, t

= 2ns, unless otherwise specified.

Symbol

Parameter

Access

Time

Commercial

Unit

Test Conditions

Notes

Min.

Max.

Input Leakage Current
(any input pin)

+ 0.5V

Output Leakage Current
(for High-Z State)

OUT

+ 0.5V

RAS, CAS at V

CC1

Supply Current,

Operating

200

= t

(min.)

2, 3, 4

180

CC2

Supply Current,

TTL Standby

RAS, CAS at V

other inputs

CC3

Supply Current,

RAS-Only Refresh

200

= t

(min.)

2, 4

180

CC4

Supply Current,

Fast Page Mode

Minimum Cycle

2, 3, 4

CC5

Supply Current,

during CAS-before-RAS Refresh

200

= t

(min.)

2, 4

180

CC6

Supply Current,

CMOS Standby

1.0

RAS

0.2 V,

CAS

0.2 V

other input

CC7

Self Refresh

1.0

CBR cycle with
t

RAS

RASS (min.)

CAS Held Low,
WE = V

-0.2V, Address and

= V

-0.2V or 0.2V

Power Supply Voltage

4.5

5.5

Input Low Voltage

0.5

0.8

Input High Voltage

2.4

+0.5

Output Low Voltage

0.4

= 4.2 mA

Output High Voltage

2.4

= 5.0 mA

V53C518160A Rev. 1.3 March 1998

MOSEL VITELIC

V53C518160A

AC Characteristics

(5,6)

= 0

C to 70

C, V

= 5 V

10%, t

= 2ns, unless otherwise noted

Symbol

Parameter

Limit Values

Unit

Note

-50

-60

Min.

Max.

Min.

Max.

Common Parameters

Random read or write cycle time

110

RAS precharge time

RAS

RAS pulse width

10k

CAS

CAS pulse width

10k

ASR

Row address setup time

RAH

Row address hold time

ASC

Column address setup time

CAH

Column address hold time

RCD

RAS to CAS delay time

RAD

RAS to column address delay

RSH

RAS hold time

CSH

CAS hold time

CRP

CAS to RAS precharge time

Transition time (rise and fall)

REF

Refresh period

Read Cycle

RAC

Access time from RAS

8, 9

CAC

Access time from CAS

8, 9

CAA

Access time from column address

8,10

OAC

OE access time

CAR

Column address to RAS lead time

RCS

Read command setup time

RCH

Read command hold time

RRH

Read command hold time referenced to RAS

CLZ

CAS to output in low-Z

OFF

Output buffer turn-off delay

OEZ

Output turn-off delay from OE

DZC

Data to CAS low delay

DZO

Data to OE low delay

CDD

CAS high to data delay

ODD

OE high to data delay

V53C518160A Rev. 1.3 March 1998

MOSEL VITELIC

V53C518160A

Write Cycle

WCH

Write command hold time

Write command pulse width

WCS

Write command setup time

RWL

Write command to RAS lead time

CWL

Write command to CAS lead time

Data setup time

Data hold time

Read-modify-Write Cycle

RWC

Read-write cycle time

126

150

RWD

RAS to WE delay time

CWD

CAS to WE delay time

AWD

Column address to WE delay time

OEH

OE command hold time

Fast Page Mode Cycle

Fast page mode cycle time

CAS precharge time

CPA

Access time from CAS precharge

COH

Output data hold time

RASP

RAS pulse width in fast page mode

200k

RHPC

CAS precharge to RAS Delay

OES

OE setup time prior to

CAS

Fast Page Mode Read-Modify-Write Cycle

PRWC

Fast page mode read-write cycle time

CPWD

CAS precharge to WE

CAS-before-RAS Refresh Cycle

CSR

CAS setup time

CHR

CAS hold time

RPC

RAS to CAS precharge time

WRP

Write to RAS precharge time

WRH

Write hold time referenced to RAS

CAS-before-RAS Counter Test Cycle

CPT

CAS precharge time (CAS-before-RAS counter test cycle)

Symbol

Parameter

Limit Values

Unit

Note

-50

-60

Min.

Max.

Min.

Max.

AC Characteristics

(Cont'd)

V53C518160A Rev. 1.3 March 1998

MOSEL VITELIC

V53C518160A

Notes:

1. All voltage are referenced to V

CC1

, I

CC3

, I

CC4

, and I

CC5

depend on cycle rate.

CC1

and I

CC4

depend on output loading. Specified values are measured with the output open.

Address can be changed once or less while RAS = V

. In the case of I

CC4

it can be changed once or less during

an Fast page mode cycle.

An initial pause of 200

s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be

a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of
8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.

AC measurements assume t

= 2ns.

(min.) and V

(max.) are reference levels for measuring timing of input signals. Transition times are also

measured between V

and V

Measured with the specified current load and 100pF at V

= 0.8 V and V

= 2.0 V. Access time is determined by

the latter of t

RAC

, t

CAC

, t

CAA

, t

CPA

, t

OAC

, t

CAC

is measured from tristate.

Operation within the t

RCD (max.)

limit ensures that t

RAC

(max.)

can be met. t

RCD (max.)

is specified as a reference point

only. If t

RCD

is greater than the specified t

RCD (max.)

limit, then access time is controlled by t

CAC

10.

Operation within the t

RAD (max.)

limit ensures that t

RAC

(max.)

can be met. t

RAD (max.)

is specified as a reference point

only. If t

RAD

is greater than the specified t

RAD (max.)

limit, then access time is controlled by t

CAA

11.

Either t

RCH

or t

RRH

must be satisfied for a read cycle.

12.

OFF (max.)

, t

OEZ (max.)

define the time at which the outputs acheive the open-circuit condition and are not referenced

to output voltage levels. t

OFF

is referenced from the rising edge of RAS or CAS, whichever occurs last.

13.

Either t

DZC

or t

DZO

must be satisfied.

14.

Either t

CDD

or t

ODD

must be satisfied.

15.

WCS

, t

RWD

, t

CWD

, and t

AWD

are not restrictive operating parameters. They are included in the data sheet as electri-

cal characteristics only. If t

WCS

> t

WCS

(min.)

, the cycle is an early write cycle and data out pin will remain open-circuit

(high impedance) through the entire cycle; if t

RWD

> t

RWD (min.)

, t

CWD

> t

CWD (min.)

, and t

AWD

> t

AWD

(min.), the cycle

is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of con-
ditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.

16.

These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in
read-write cycles.

17.

When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM oper-
ation:

If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.

If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh
interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit
from Self Refresh.

V53C518160A Rev. 1.3 March 1998

MOSEL VITELIC

V53C518160A

Waveforms of Fast Page Mode Read-Modify-Write Cycle

RAS

Address

I/O

(Inputs)

I/O

(Outputs)

Data In

Data

Out

Data

Out

Row

Column

Row

Column

RASP

PRWC

CSH

RCD

CAS

RSH

CRP

ASR

CAR

CAH

ASC

CAH

ASC

RAD

RAH

ASR

RWL

CWL

CPWD

CWD

CWL

CWD

CPWD

CWL

CWD

RWD

RCS

AWD

CAA

OAC

AWD

OAC

AWD

RAC

DZO

CAC

DZC

CLZ

ODD

OEZ

OEH

DZC

CPA

CAA

CLZ

ODD

OEZ

DZC

CPA

CLZ

OEH

CAC

CAA

OEH

ODD

OEZ

UCAS

LCAS

ASC

OAC

511816502-13

V53C518160A Rev. 1.3 March 1998

MOSEL VITELIC

V53C518160A

Functional Description

The V53C518160A is a CMOS dynamic RAM op-

timized for high data bandwidth, low power applica-
tions. It is functionally similar to a traditional
dynamic RAM. The V53C518160A reads and writes
data by multiplexing an 20-bit address into a 10-bit
row and a 10-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address "flows through" an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.

Memory Cycle

A memory cycle is initiated by bringing RAS low.

Any memory cycle, once initiated, must not be end-
ed or aborted before the minimum t

RAS

time has ex-

pired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time t

has elapsed.

Read Cycle

A Read cycle is performed by holding the Write

Enable (WE) signal High during a RAS/CAS opera-
tion. The column address must be held for a mini-
mum specified by t

. Data Out becomes valid only

when t

OAC

, t

RAC

, t

CAA

and t

CAC

are all satisifed. As

a result, the access time is dependent on the timing
relationships between these parameters. For exam-
ple, the access time is limited by t

CAA

when t

RAC

CAC

and t

OAC

are all satisfied.

Write Cycle

A Write Cycle is performed by taking WE and

CAS low during a RAS operation. The column ad-
dress is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAS-
controlled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.

In the WE controlled Write Cycle, OE must be in

the high state and t

OED

must be satisfied.

Fast Page Mode

Fast Page operation permits all 1024 columns

within a selected row of the device to be randomly

accessed at a high data rate. Maintaining RAS low
while performing successive CAS cycles retains the
row address internally and eliminates the need to
reapply it for each cycle. The column address buffer
acts as a transparent or flow-through latch while
CAS is high. Thus, access begins from the occur-
rence of a valid column address rather than from the
falling edge of CAS, eliminating t

ASC

and t

from the

critical timing path. CAS latches the address into the
column address buffer. During Fast Page operation,
Read, Write, Read-Modify-Write or Read-Write-
Read cycles are possible at random addresses
within a row. Following the initial entry cycle into
EDO Mode, access is t

CAA

or t

CAP

controlled. If the

column address is valid prior to the rising edge of
CAS, the access time is referenced to the CAS ris-
ing edge and is specified by t

CAP

. If the column ad-

dress is valid after the rising CAS edge, access is
timed from the occurrence of a valid address and is
specified by t

CAA

. In both cases, the falling edge of

CAS latches the address and enables the output.

Fast Page provides a sustained data rate of 29

MHz for applications that require high bandwidth
such as bit-mapped graphics or high-speed signal
processing. The following equation can be used to
calculate the maximum data rate:

Self Refresh

Self Refresh mode provides internal refresh con-

trol signals to the DRAM during extended periods of
inactivity. Device operation in this mode provides
additional power savings and design ease by elimi-
nation of external refresh control signals. Self Re-
fresh mode is initialed with a CAS before RAS
(CBR) Refresh cycle, holding both RAS low (t

RASS

)

and CAS low (t

CHD

) for a specified period. Both of

these parameters are specified with minimum val-
ues to guarantee entry into Self Refresh operation.
Once the device has been placed in to Self Refresh
mode the CAS clock is no longer required to main-
tain Self Refresh operation.

The Self Refresh mode is terminated by returning

the RAS clock to a high level for a specified (t

RPS

)

minimum time. After termination of the Self Refresh
cycle normal accesses to the device may be initiat-
ed immediately, poviding that subsequest refresh
cycles utilize the CAS before RAS (CBR) mode of
operation.

Data Rate

1024

1023

--------------------------------------------

MOSEL VITELIC

V53C518160A

V53C518160A Rev. 1.3 March 1998

Data Output Operation

The V53C518160A Input/Output is controlled by

OE, CAS, WE and RAS. A RAS low transition en-
ables the transfer of data to and from the selected
row address in the Memory Array. A RAS high tran-
sition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level dis-
ables the I/O path and the output driver if it is en-
abled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output driv-
ers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latch-
es. A WE low level can also disable the output driv-
ers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
normally cause the outputs to be active, it is neces-
sary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(t

) to be satisfied.

Power-On

After application of the V

supply, an initial

pause of 200

s is required followed by a minimum

of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).

During Power-On, the V

current requirement of

the V53C518160A is dependent on the input levels
of RAS and CAS. If RAS is low during Power-On,
the device will go into an active cycle and I

will ex-

hibit current transients. It is recommended that RAS
and CAS track with V

or be held at a valid V

dur-

ing Power-On to avoid current surges.

Table 1. V53C518160A Data Output

Operation for Various Cycle Types

Cycle Type

I/O State

Read Cycles

Data from Addressed
Memory Cell

CAS-Controlled Write Cycle
(Early Write)

High-Z

WE-Controlled Write
Cycle (Late Write)

OE Controlled. High
OE = High-Z I/Os

Read-Modify-Write Cycles

Data from Addressed
Memory Cell

EDO Read Cycle

Data from Addressed
Memory Cell

EDO Write Cycle (Early Write)

High-Z

EDO Read-Modify-Write Cycle

Data from Addressed
Memory Cell

RAS-only Refresh

High-Z

CAS-before-RAS
Refresh Cycle

High-Z

CAS-only Cycles

High-Z

V53C518160A Rev. 1.3 March 1998

MOSEL VITELIC

V53C518160A

Package Diagrams

42-Pin 400 mil SOJ

44/50-Pin 400 mil TSOP-II

1.08

0.010

[27.41

0.25

]

0.05 [1.27]

1.0 [25.4]

0.017

0.004

[0.43

0.1]

0.004 [0.1]

0.045 [1.15] MIN

0.145 [3.68] MAX

.406

0.012

[10.3

0.3

]

.441

0.006

[11.2

0.15

]

0.370

0.010 [9.4

0.25]

.406

0.012

(1)

[10.3 0.3]

.441

0.006

[11.2

0.15

]

(1)

0.2

Unit in inches [mm]

0.81 [.032] MAX

+0.12
0.05

0.008

+0.005
0.002

0.088

0.004

[2.24

0.1]

(1) Does not include plastic or metal protrusion of 0.010 [0.25] max per side.

0.016

+0.002
0.004

0.4

+0.05
0.1

0.006

+0.003
0.001

0.15

+0.08
0.03

0.008 [0.2]

44x

Unit in inches [mm]

0.004

0.002

[0.1

0.05]

0.031 [0.8]

0.039

0.002

0.05]

0.4

0.005

[10.16

0.13]

0.463

0.008

[11.76

0.2]

0.047 Max

[1.2 Max]

0.004 [0.1]

0.825

0.005

[20.95

0.13]

Does not include plastic or metal protrusion of 0.010 [0.25] max. per side

0.020

0.004

[0.5

0.1]

MOSEL VITELIC

WORLDWIDE OFFICES

V53C518160A

3/98
Printed in U.S.A.

MOSEL VITELIC

3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

U.S. SALES OFFICES

The information in this document is subject to change without
notice.

MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.

MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.

U.S.A.

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SAN JOSE, CA 95134
PHONE: 408-433-6000

FAX: 408-433-0185

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