DSP56F802/D
Rev. 0, 1/2002
Motorola, Inc., 2002. All rights reserved.
DSP56F802
Preliminary Technical Data
DSP56F802 16-bit Digital Signal Processor
Up to 40 MIPS operation at 80 MHz core
frequency
DSP and MCU functionality in a unified,
C-efficient architecture
MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
8K
16-bit words Program Flash
1K
16-bit words Program RAM
2K
16-bit words Data Flash
1K
16-bit words Data RAM
2K
16-bit words Boot Flash
Hardware DO and REP loops
6-channel PWM Module with fault input
Two 12-bit ADCs (1 x 2 channel, 1 x 3 channel)
Serial Communications Interface (SCI)
Two General Purpose Quad Timers with 2
external outputs
JTAG/OnCE
TM
port for debugging
4 shared GPIO
On-chip relaxation oscillator
32-pin LQFP Package
Figure 1. DSP56F802 Block Diagram
JTAG/
OnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36
36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
Bit
Manipulation
Unit
16-Bit
DSP56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
INTERRUPT
CONTROLS
IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP RESET
RESET
Application-
Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
Boot Flash
2048x 16 Flash
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
COP/
Watchdog
SCI0
or
GPIO
Quad Timer D
or GPIO
Quad Timer C
A/D1
A/D2
ADC
2
2
3
2
6
PWM Outputs
PWMA
16
16
VCAPC
V
DD
V
SS
* V
DDA
V
SSA
5
2
2
3
VREF
PLL
Relaxation
Oscillator
.
*
includes TCS pin which is reserved for factory use and is tied to
VSS
Fault A0
2
DSP56F802 Preliminary Technical Data
MOTOROLA
Part 1 Overview
1.1 DSP56F802 Features
1.1.1
Digital Signal Processing Core
Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency
Single-cycle 16
16-bit parallel Multiplier-Accumulator (MAC)
Two 36-bit accumulators including extension bits
16-bit bidirectional barrel shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
On-chip memory including a low-cost, high-volume flash solution
-- 8K
16 bit words of Program Flash
-- 1K
16-bit words of Program RAM
-- 2K
16-bit words of Data Flash
-- 1K
16-bit words of Data RAM
-- 2K
16-bit words of Boot Flash
Programmable Boot Flash supports customized boot code and field upgrades of stored code through
a variety of interfaces (JTAG)
1.1.3
Peripheral Circuits for DSP56F802
Pulse Width Modulator (PWM) with six PWM outputs with deadtime insertion and fault protection;
supports both center- and edge-aligned modes
Two 12-bit, Analog-to-Digital Converters (ADCs), 1 x 2 channel and 1 x 3 channel, which support
two simultaneous conversions; ADC and PWM modules can be synchronized
Two General Purpose Quad Timers with two external pins (or two GPIO)
Serial Communication Interface (SCI) with two pins (or two GPIO)
Four multiplexed General Purpose I/O (GPIO) pins
DSP56F802 Description
MOTOROLA
DSP56F802 Preliminary Technical Data
3
Computer-Operating Properly (COP) watchdog timer
External interrupts via GPIO
Trimmable on-chip relaxation oscillator
External reset pin for hardware reset
JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging
Software-programmable, Phase Lock Loop-based frequency synthesizer for the DSP core clock
1.1.4
Energy Information
Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs
Uses a single 3.3V power supply
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
Integrated power supervisor
1.2 DSP56F802 Description
The DSP56F802 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the DSP56F802 is well-suited for many applications.
The DSP56F802 includes many peripherals that are especially useful for applications such as motion
control, home appliances, encoders, tachometers, limit switches, power supply and control, engine
management, and industrial control for power, lighting, automation and HVAC.
The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating
in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The DSP56F802 supports program execution from either internal or external memories. Two data operands
can be accessed from the on-chip data RAM per instruction cycle. The DSP56F802 also provides and up to
4 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The DSP56F802 DSP controller includes 8K words (16-bit) of program Flash and 2K words of Data Flash
(each programmable through the JTAG port) with 1K words of both program and data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main program and data flash memory areas. Both program and data flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.
A key application-specific feature of the DSP56F802 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs to
enhance motor control functionality. Complementary operation permits programmable dead-time insertion,
and separate top and bottom output polarity control. The up-counter value is programmable to support a
continuously variable PWM frequency. Both edge and center aligned synchronous pulse width control (0%
to 100% modulation) are supported. The device is capable of controlling most motor types: ACIM (AC
4
DSP56F802 Preliminary Technical Data
MOTOROLA
Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and
Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection with sufficient
output drive capability to directly drive standard opto-isolators. A "smoke-inhibit", write-once protection
feature for key parameters is also included. The PWM is double-buffered and includes interrupt control to
permit integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output
to synchronize the Analog-to-Digital Converters.
The DSP56F802 incorporates two 12-bit Analog-to-Digital Converters (ADCs) with a total of five channels.
A full set of standard programmable peripherals is provided that include a Serial Communications Interface
(SCI), and two Quad Timers. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIO)
if that function is not required. An on-chip relaxation oscillator eliminates the need for an external crystal.
1.3 "Best in Class" Development Environment
The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces
that allow programmers to create their unique C application code independent of component architecture.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in
Table 1
are required for a complete description and proper design with the
DSP56F802. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors/dsp.
Table 1. DSP56F802 Chip Documentation
Topic
Description
Order Number
DSP56800
Family Manual
Detailed description of the DSP56800 family architecture, and
16-bit DSP core processor and the instruction set
DSP56800FM/D
DSP56F801/803/805/807
User's Manual
Detailed description of memory, peripherals, and interfaces of
the DSP56F801, DSP56F802, DSP56F803, DSP56F805, and
DSP56F807
DSP56F801-7UM/D
DSP56F802
Technical Data Sheet
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
DSP56F802/D
DSP56F802
Product Brief
Summary description and block diagram of the DSP56F802
core, memory, peripherals and interfaces
DSP56F802PB/D
Data Sheet Conventions
MOTOROLA
DSP56F802 Preliminary Technical Data
5
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
"asserted"
A high true (active high) signal is high or a low true (active low) signal is low.
"deasserted"
A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage
1
1.
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
PIN
True
Asserted
V
IL
/V
OL
PIN
False
Deasserted
V
IH
/V
OH
PIN
True
Asserted
V
IH
/V
OH
PIN
False
Deasserted
V
IL
/V
OL
6
DSP56F802 Preliminary Technical Data
MOTOROLA
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the DSP56F802 are organized into functional groups, as shown in
Table 2
and as illustrated in
Figure 2
. In
Table 3
through
Table 11
, each table row describes the signal or signals
present on a pin.
Table 2. Functional Group Pin Allocations
Functional Group
Number of
Pins
Detailed
Description
Power (V
DD
or V
DDA
)
3
Table 3
Ground (V
SS,
V
SSA,
TCS)
4
Table 4
Supply Capacitors
2
Table 5
Program Control
1
Table 6
Pulse Width Modulator (PWM) Port and Fault Input
7
Table 7
Serial Communications Interface (SCI) Port
1
1.
Alternately, GPIO pins
2
Table 8
Analog-to-Digital Converter (ADC) Port (including V
REF)
6
Table 9
Quad Timer Module Port
2
Table 10
JTAG/On-Chip Emulation (OnCE)
5
Table 11
Introduction
MOTOROLA
DSP56F802 Preliminary Technical Data
7
Figure 2. DSP56F802 Signals Identified by Functional Group
1
1. Alternate pin functionality is shown in parenthesis.
DSP56F802
Power Port
Ground Port
Power Port
Ground Port
SCI0 Port or
GPIO
V
DD
V
SS
V
DDA
V
SSA
VCAPC
TCK
TMS
TDI
TDO
TRST
JTAG/
OnCE
TM
Port
PWMA0-5
Fault A0
TXD0 (GPIOB0)
RXD0 (GPIOB1)
ANA2-4, ANA6-7
VREF
TD1-2 (GPIOA1-2)
RESET
Quad
Timer D or
GPIO
ADCA Port
Other
Supply Port
2
3*
1
1
2
1
1
1
1
1
Program
Control
6
1
1
1
5
1
2
1
*
includes TCS pin which is reserved for factory use and is tied to
VSS
8
DSP56F802 Preliminary Technical Data
MOTOROLA
2.2 Power and Ground Signals
2.3 Interrupt and Program Control Signals
Table 3. Power Inputs
No. of Pins
Signal Name
Signal Description
2
V
DD
Power--These pins provide power to the internal structures of the chip, and
should all be attached to V
DD.
1
V
DDA
Analog Power--This pin supplies an analog power source.
Table 4. Grounds
No. of Pins
Signal Name
Signal Description
2
V
SS
GND--These pins provide grounding for the internal structures of the chip, and
should all be attached to V
SS.
1
V
SSA
Analog Ground--This pin supplies an analog ground.
1
TCS
TCS--This pin is reserved for factory use and must be tied to V
SS
for normal
use. In block diagrams, this pin is considered an additional V
SS.
Table 5. Supply Capacitors and VPP
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
2
VCAPC Supply
Supply
VCAPC - Connect each pin to a 2.2
F bypass capacitor in order
to bypass the core logic voltage regulator (required for proper chip
operation). For more information, refer to
Section 5.2
Table 6. Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
RESET
Input
Input
Reset--This input is a direct hardware reset on the processor.
When RESET is asserted low, the DSP is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial chip operating
mode is latched from the EXTBOOT pin. The internal reset signal
will be deasserted synchronous with the internal clocks, after a
fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware DSP reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case,
assert RESET, but do not assert TRST.
Pulse Width Modulator (PWM) Signals
MOTOROLA
DSP56F802 Preliminary Technical Data
9
2.4 Pulse Width Modulator (PWM) Signals
2.5 Serial Communications Interface (SCI) Signals
2.6 Analog-to-Digital Converter (ADC) Signals
Table 7. Pulse Width Modulator (PWMA) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
PWMA0-5
Output
Tri-stated
PWMA0-5-- These are six PWMA output pins.
1
FAULTA0
Input
Input
FAULTA0 --This fault input is used for disabling selected
PWMA outputs in cases where fault conditions originate off
chip.
Table 8. Serial Communications Interface (SCI0) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TXD0
GPIOB0
Output
Input/
Output
Input
Input
Transmit Data (TXD0)--transmit data output
Port B GPIO--This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.
After reset, the default state is SCI output.
1
RXD0
GPIOB1
Input
Input/
Output
Input
Input
Receive Data (RXD0)--receive data input
Port B GPIO--This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.
After reset, the default state is SCI input.
Table 9. Analog to Digital Converter Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
3
ANA2-4
Input
Input
ANA2-4--Analog inputs to ADC channel 1
2
ANA6-7
Input
Input
ANA6-7--Analog inputs to ADC channel 2
1
VREF
Input
Input
VREF--Analog reference voltage. Must be set to V
DDA
- 0.3V
= 3.0V for optimal performance.
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DSP56F802 Preliminary Technical Data
MOTOROLA
2.7 Quad Timer Module Signals
2.8 JTAG/OnCE
Table 10. Quad Timer Module Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
2
TD1-2
GPIOA1-2
Input/
Output
Input/
Output
Input
Input
TD1-2--Timer D Channel 1-2
Port A GPIO--These pins are General Purpose I/O (GPIO)
pins that can individually be programmed as input or output
pins.
After reset, the default state is the quad timer input.
Table 11. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TCK
Input
Input, pulled
low internally
Test Clock Input--This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE port.
The pin is connected internally to a pull-down resistor.
1
TMS
Input
Input, pulled
high internally
Test Mode Select Input--This input pin is used to sequence the JTAG
TAP controller's state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
1
TDI
Input
Input, pulled
high internally
Test Data Input--This input pin provides a serial input data stream to
the JTAG/OnCE port. It is sampled on the rising edge of TCK and has
an on-chip pull-up resistor.
1
TDO
Output
Tri-stated
Test Data Output--This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
1
TRST
Input
Input, pulled
high internally
Test Reset--As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment, since the OnCE/JTAG
module is under the control of the debugger. In this case it is not
necessary to assert TRST when asserting RESET. Outside of a
debugging environment RESET should be permanently asserted by
grounding the signal, thus disabling the OnCE/JTAG module on the
DSP.
General Characteristics
MOTOROLA
DSP56F802 Preliminary Technical Data
11
Part 3 Specifications
3.1 General Characteristics
The DSP56F802 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs.
The term "5-volt tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture
of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-
compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
10%
during normal operation without causing damage). This 5V tolerant capability therefore offers the power
savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in
Table 12
are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The DSP56F802 DC and AC electrical specifications are preliminary and are from design simulations.
These specifications may not be fully tested or guaranteed at this early stage of the product life cycle.
Finalized specifications will be published after complete characterization and device qualifications have
been completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Table 12. Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Unit
Supply voltage
V
DD
V
SS
0.3
V
SS
+ 4.0
V
All other input voltages, excluding Analog inputs
V
IN
V
SS
0.3
V
SS
+ 5.5V
V
Analog Inputs ANAx, V
REF
V
IN
V
SS
0.3
V
DDA
+ 0.3V
V
Current drain per pin excluding V
DD
, V
SS
, & PWM ouputs
I
--
10
mA
Current drain per pin for PWM outputs
I
--
20
mA
Junction temperature
T
J
--
150
C
Storage temperature range
T
STG
-55
150
C
12
DSP56F802 Preliminary Technical Data
MOTOROLA
3.2 DC Electrical Characteristics
Table 13. Recommended Operating Conditions
Characteristic
Symbol
Min
Max
Unit
Supply voltage
V
DD
3.0
3.6
V
Ambient operating temperature
T
A
-40
85
C
Table 14. Thermal Characteristics
1
1.
See
Section 5.1
for more detail.
Characteristic
32-pin LQFP
Symbol
Value
Unit
Junction-to-ambient (estimated)
R
JA
53.2
C/W
I/O pin power dissipation
P
I/O
User Determined
W
Power dissipation
P
D
P
D
= (I
DD
x V
DD
) + P
I/O
W
Maximum allowed P
D
P
DMAX
(T
J
- T
A
) /
JA
C
Table 15. DC Electrical Characteristics
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50 pF, f
op
= 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Input high voltage
V
IH
2.0
--
5.5
V
Input low voltage
V
IL
-0.3
--
0.8
V
Input current low (pullups/pulldowns disabled)
I
IL
-1
--
1
A
Input current high (pullups/pulldowns disabled)
I
IH
-1
--
1
A
Typical pullup or pulldown resistance
R
PU
, R
PD
--
30
--
K
Input/output tri-state current low
I
OZL
-10
--
10
A
Input/output tri-state current low
I
OZH
-10
--
10
A
Output High Voltage (at IOH)
V
OH
V
DD
0.7
--
--
V
Output Low Voltage (at IOL)
V
OL
--
--
0.4
V
Output High Current
I
OH
--
--
-4
mA
Output Low Current
I
OL
--
--
4
mA
Input capacitance
C
IN
--
8
--
pF
Output capacitance
C
OUT
--
12
--
pF
DC Electrical Characteristics
MOTOROLA
DSP56F802 Preliminary Technical Data
13
Figure 3. Maximum Run Idd vs. Frequency (see Note 4 above)
PWM pin output source current
1
I
OHP
--
--
-10
mA
PWM pin output sink current
2
I
OLP
--
--
16
mA
V
DD
supply current
I
DDT
3
Run
4
--
103
138
mA
Wait
5
--
72
98
mA
Stop
--
60
84
mA
Low Voltage Interrupt
6
Core Voltage Interrupt
V
EI
2.4
--
2.7
2.2
2.9
--
V
Power on Reset
7
POR
--
1.7
2.0
V
1.
PWM pin output source current measured with 50% duty cycle.
2.
PWM pin output sink current measured with 50% duty cycle.
3.
I
DDT
= I
DD
+ I
DDA
(Total supply current for VDD + VDDA)
4.
Run (operating) I
DD
measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
configured as inputs; measured with all modules enabled.
5.
Wait I
DD
measured using internal relaxation oscillator set to 8 MHz; all inputs 0.2V from rail; no DC loads; less
than 50 pF on all outputs. C
L
= 20 pF on EXTAL; all ports configured as inputs; measured with PLL enabled.
6.
Low voltage interrupt monitors the V
DD
supply. When V
DD
drops below V
EI
value, an interrupt is generated.
Functionality of the device is guaranteed under transient conditions when V
DDA
>V
EI
.
7.
Power-on reset occurs whenever the internally regulated 2.5V digital supply drops below V
POR
. While power is
ramping up, this signal remains active for as long as the internal 2.5V supply is below 1.5V no matter how long the ramp
up rate is. The internally regulated voltage is typically 100 mV less than V
DD
during ramp up until 2.5V is reached, at
which time it self regulates.
Table 15. DC Electrical Characteristics
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50 pF, f
op
= 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
180
150
120
90
60
30
0
I
dd (
m
A)
Digital (VDD=3.6V)
Analog (VDDA=3.6V)
Total
Freq. (MHz)
0
40
60
80
20
I
dd (
m
A)
40
180
150
120
90
60
30
0
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DSP56F802 Preliminary Technical Data
MOTOROLA
3.3 AC Electrical Characteristics
Timing waveforms in
Section 3.3
are tested with a V
IL
maximum of 0.8 V and a V
IH
minimum of 2.0 V for
all pins except XTAL, which is tested using the input levels in
Section 3.2
In
Figure 4
the levels of V
IH
and
V
IL
for an input signal are shown.
Figure 4. Input Signal Measurement References
Figure 5
shows the definitions of the following signal states:
Active state, when a bus or signal is driven, and enters a low impedance state.
Tri-stated, when a bus or signal is placed in a high impedance state.
Data Valid state, when a signal level has reached V
OL
or V
OH.
Data Invalid state, when a signal level is in transition between V
OL
and V
OH.
Figure 5. Signal States
V
IH
V
IL
Fall Time
Input Signal
Note: The midpoint is V
IL
+ (V
IH
V
IL
)/2.
Midpoint1
Low
High
90%
50%
10%
Rise Time
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2
Data3
Data1 Valid
Data Active
Data Active
Flash Memory Characteristics
MOTOROLA
DSP56F802 Preliminary Technical Data
15
3.4 Flash Memory Characteristics
Table 16. Flash Memory Truth Table
Mode
XE
1
1.
X address enable, all rows are disabled when XE = 0
YE
2
2.
Y address enable, YMUX is disabled when YE = 0
SE
3
3.
Sense amplifier enable
OE
4
4.
Output enable, tri-state flash data out bus when OE = 0
PROG
5
5.
Defines program cycle
ERASE
6
6.
Defines erase cycle
MAS1
7
7.
Defines mass erase cycle, erase whole block
NVSTR
8
8.
Defines non-volatile store cycle
Standby
L
L
L
L
L
L
L
L
Read
H
H
H
H
L
L
L
L
Word Program
H
H
L
L
H
L
L
H
Page Erase
H
L
L
L
L
H
L
H
Mass Erase
H
L
L
L
L
H
H
H
Table 17. IFREN Truth Table
Mode
IFREN = 1
IFREN = 0
Read
Read information block
Read main memory block
Word program
Program information block
Program main memory block
Page erase
Erase information block
Erase main memory block
Mass erase
Erase both blocks
Erase main memory block
16
DSP56F802 Preliminary Technical Data
MOTOROLA
Table 18. Timing Symbols
Characteristic
Symbol
See Figure(s)
PROG/ERASE to NVSTR set up time
T
nvs
Figure 6
,
Figure 7
,
Figure 8
NVSTR hold time
T
nvh
Figure 6
,
Figure 7
NVSTR hold time(mass erase)
T
nvh1
Figure 8
NVSTR to program set up time
T
pgs
Figure 6
Program hold time
T
pgh
Figure 6
Address/data set up time
T
ads
Figure 6
Address/data hold time
T
adh
Figure 6
Recovery time
T
rcv
Figure 6
,
Figure 7
,
Figure 8
Cumulative program HV period
T
hv
Figure 6
Program time
T
prog
Figure 6
Erase time
T
erase
Figure 7
Mass erase time
T
me
Figure 8
Table 19. Flash Timing Parameters
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50 pF
Characteristic
Symbol
Min Typ
Max Unit
Program time
T
prog
20
--
--
us
Erase time
T
erase
20
--
--
ms
Mass erase time
T
me
100
--
--
ms
Endurance
1
1.
One cycle is equal to an erase, program, and read.
E
CYC
10,000
20,000
--
cycles
Data Retention @ 5,000 Cycles
1
D
RET
10
30
--
years
The following parameters should only be used in the Manual Word Programming mode.
PROG/ERASE to NVSTR set up time
T
nvs
--
5
--
us
NVSTR hold time
T
nvh
--
5
--
us
NVSTR hold time(mass erase)
T
nvh1
--
100
--
us
NVSTR to program set up time
T
pgs
--
10
--
us
Recovery time
T
rcv
--
1
--
us
Flash Memory Characteristics
MOTOROLA
DSP56F802 Preliminary Technical Data
17
Figure 6. Flash Program Cycle
Figure 7. Flash Erase Cycle
XADR
YADR
YE
DIN
PROG
NVSTR
Tnvs
Tpgs
Tadh
Tprog
Tads
Tpgh
Tnvh
Trcv
Thv
IFREN
XE
XADR
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Tnvh
Trcv
Terase
IFREN
XE
18
DSP56F802 Preliminary Technical Data
MOTOROLA
Figure 8. Flash Mass Erase Cycle
3.5 Clock Operation
The DSP56F802 device clock is derived from an on-chip relaxation oscillator. The internal PLL generates
a master reference frequency that determines the speed at which chip operations occur.
The PRECS bit in the PLLCR (phase-locked loop control register) word (bit 2) must be set to 0 for internal
oscillator use.
3.5.1
Use of On-Chip Relaxation Oscillator
The DSP56F802 internal relaxation oscillator provides the chip clock without the need for an external
crystal or ceramic resonator. The frequency output of this internal oscillator can be corrected by adjusting
the 8-bit IOSCTL (internal oscillator control) register. Each bit added or deleted changes the output
frequency of the oscillator allowing incremental adjustment until the desired frequency is achieved. Figures
9 and 10 show the typical characteristics of the DSP56F802 relaxation oscillator with respect to temperature
and trim value.
During factory production test, an oscillator calibration procedure is executed which determines an
optimum trim value for a given device (8 MHz at 25
o
C). This optimum trim value is then stored at address
$103F in the Data Flash Information Block and recalled during a trim routine in the boot sequence (executed
after power-up and RESET). This trim routine automatically sets the oscillator frequency by programming
the IOSCTL register with the optimum trim value.
Due to the inherent frequency tolerances required for SCI communication, changing the factory-trimmed
oscillator frequency is not recommended. If modification of the Boot Flash contents are required, code must
be included which retrieves the optimum trim value (from address $103F in the Data Flash Information
Block) and writes it to the IOSCTL register. Note that the IFREN bit in the Data Flash control register must
be set in order to read the Data Flash Information Block.
XADR
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1
Trcv
Tme
MAS1
IFREN
XE
Clock Operation
MOTOROLA
DSP56F802 Preliminary Technical Data
19
Figure 9. Typical Relaxation Oscillator Frequency vs. Temperature
(Trimmed to 8 MHz @ 25
o
C)
Table 20. Relaxation Oscillator Characteristics
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency Accuracy
1
1.
Over full temperature range.
f
--
+2
+5
%
Frequency Drift over Temp
f/
t
--
+0.1
--
%/
o
C
Frequency Drift over Supply
f/
V
--
0.1
--
%/V
8.2
8.0
8.3
8.4
7.9
8.1
7.8
75
55
-40
35
-25
15
-5
85
Temperature (
o
C)
O
u
tput
Freq
ue
ncy
20
DSP56F802 Preliminary Technical Data
MOTOROLA
Figure 10. Typical Relaxation Oscillator Frequency vs. Trim Value @ 25
o
C
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 21. Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 5
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50 pF
1.
In the formulas, T = clock cycle. For an operating frequency of 80 MHz, T = 12.5 ns.
Characteristic
Symbol
Typical
Min
Typical
Max
Unit
RESET Assertion to Address, Data and Control Signals High
Impedance
t
RAZ
--
21
ns
Minimum RESET Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
t
RA
275,000T
128T
--
--
ns
ns
RESET De-assertion to First External Address Output
t
RDA
33T
34T
ns
Edge-sensitive Interrupt Request Width
t
IRW
1.5T
--
ns
0
10
20
30 40 50
60 70 80
90 A0 B0 C0 D0 E0
F0
5
6
7
8
9
10
11
Quad Timer Timing
MOTOROLA
DSP56F802 Preliminary Technical Data
21
Figure 11. External Level-Sensitive Interrupt Timing
3.7 Quad Timer Timing
Table 22. Timer Timing
1, 2
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50 pF, f
OP
= 80 MHz
1.
In the formulas listed, T = clock cycle. For 80 MHz operation, T = 12.5 ns.
2.
Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical Min
Typical Max
Unit
Timer input period
P
IN
4T+6
--
ns
Timer input high/low period
P
INHL
2T+3
--
ns
Timer output period
P
OUT
2T
--
ns
Timer output high/low period
P
OUTHL
1T
--
ns
Figure 12. Timer Timing
General
Purpose
I/O Pin
IRQA
b) General Purpose I/O
t
IG
Timer Inputs
Timer Outputs
P
OUTHL
P
OUTHL
P
OUT
P
IN
P
INHL
P
INHL
22
DSP56F802 Preliminary Technical Data
MOTOROLA
3.8 Serial Communication Interface (SCI) Timing
Figure 13. RXD Pulse Width
Figure 14. TXD Pulse Width
3.9 Analog-to-Digital Converter (ADC) Characteristics
Table 23. SCI Timing
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50 pF, f
OP
= 80 MHz
Characteristic
Symbol
Min
Max
Unit
Baud Rate
1
1.
f
MAX
is the frequency of operation of the system clock in MHz.
BR
--
(f
MAX
*2.5)/(80)
Mbps
RXD
2
Pulse Width
2.
The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
RXD
PW
0.965/BR
1.04/BR
ns
TXD
3
Pulse Width
3.
The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4.
Parameters listed are guaranteed by design.
TXD
PW
0.965/BR
1.04/BR
ns
Table 24. ADC Characteristics
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, V
REF
= V
DD
-0.3V, ADCDIV = 4, 9, or 14,
ADC clock = 4MHz, 3.03.6 V, T
A
= 40
to +85
C, C
L
50 pF, f
OP
= 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Input voltages
V
ADIN
0
--
V
DDA
1
V
Resolution
R
ES
12
--
12
Bits
Integral Non-Linearity
2
INL
--
+/- 4
+/- 5
LSB
3
Differential Non-Linearity
DNL
--
+/- 0.9
+/- 1
LSB
3
Monotonicity
GUARANTEED
ADC internal clock
f
ADIC
0.5
--
5
MHz
Conversion range
R
AD
V
SSA
--
V
DDA
V
RXD
SCI receive
data pin
(Input)
RXD
PW
TXD
SCI receive
data pin
(Input)
TXD
PW
Analog-to-Digital Converter (ADC) Characteristics
MOTOROLA
DSP56F802 Preliminary Technical Data
23
Figure 15. Equivalent Analog Input Circuit
1.
Parasitic capacitance due to package, pin to pin, and pin to package base coupling. 1.8pf
2.
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing.
2.04pf
3.
Equivalent resistance for the ESD isolation resistor and the channel select mux. 500 ohms
Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the
input and is only connected to it at sampling time. 1pf
Power-up time
t
ADPU
--
2.5
--
msec
Conversion time
t
ADC
--
6
--
t
AIC
cycles
4
Sample time
t
ADS
--
1
--
t
AIC
cycles
4
Input capacitance
C
ADI
--
5
--
pF
4
Gain Error (transfer gain)
E
GAIN
1.00
1.10
1.15
--
Offset Voltage
V
OFFSET
+10
+230
+325
mV
Total Harmonic Distortion
THD
55
60
--
dB
Signal-to-Noise plus Distortion
SINAD
54
56
--
--
Effective Number of Bits
ENOB
8.5
9.5
--
bit
Spurious Free Dynamic Range
SFDR
60
65
--
dB
Spurious Free Dynamic Range
SFDR
65
70
--
dB
ADC Quiescent Current (both ADCs)
I
ADC
--
39.3
--
mA
V
REF
Quiescent Current (both ADCs)
I
VREF
--
11.85
14.5
mA
1.
V
DDA
should be tied to the same potential as
V
DD
via separate traces. V
REF
must be equal to or less than V
DD
and must be greater than or equal to 2.7V.
2.
Measured in 10-90% range.
3.
LSB = Least Significant Bit.
4.
t
AIC
= 1/
f
ADIC
Table 24. ADC Characteristics (Continued)
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, V
REF
= V
DD
-0.3V, ADCDIV = 4, 9, or 14,
ADC clock = 4MHz, 3.03.6 V, T
A
= 40
to +85
C, C
L
50 pF, f
OP
= 80 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
1
2
3
4
ADC analog input
24
DSP56F802 Preliminary Technical Data
MOTOROLA
3.10 JTAG Timing
Table 25. JTAG Timing
1, 3
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.03.6 V, T
A
= 40
to +85
C, C
L
50 pF, f
OP
= 80 MHz
1.
Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80 MHz
operation, T = 12.5 ns.
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation
2
2.
TCK frequency of operation must be less than 1/8 the processor rate.
3.
Parameters listed are guaranteed by design.
f
OP
DC
10
MHz
TCK cycle time
t
CY
100
--
ns
TCK clock pulse width
t
PW
50
--
ns
TMS, TDI data setup time
t
DS
0.4
--
ns
TMS, TDI data hold time
t
DH
1.2
--
ns
TCK low to TDO data valid
t
DV
--
26.6
ns
TCK low to TDO tri-state
t
TS
--
23.5
ns
TRST assertion time
t
TRST
50
--
ns
Figure 16. Test Clock Input Timing Diagram
TCK
(Input)
V
M
V
IL
V
M
= V
IL
+ (V
IH
V
IL
)/2
V
M
V
IH
t
PW
t
PW
t
CY
JTAG Timing
MOTOROLA
DSP56F802 Preliminary Technical Data
25
Figure 17. Test Access Port Timing Diagram
Figure 18. TRST Timing Diagram
Input Data Valid
Output Data Valid
Output Data Valid
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output
)
TDO
(Output)
TMS
t
DV
t
DV
t
TS
t
DS
t
DH
TRST
(Input)
t
TRST
26
DSP56F802 Preliminary Technical Data
MOTOROLA
Part 4 Packaging
4.1 Package and Pin-Out Information DSP56F802
This section contains package and pin-out information for the 32-pin LQFP configuration of the
DSP56F802.
Figure 19. Top View, DSP56F802 32-pin LQFP Package
PIN 1
ORIENTATION
MARK
PWMA4
PWMA5
TD1
TD2
TXDO
VSS
VDD
RXD0
TCS
TCK
TM
S
TD
I
VCAPC2
TDO
TR
S
T
RESET
ANA3
VREF
ANA2
FAULTA0
VSS
VDD
VSSA
VDDA
PWM
A
3
PWM
A
2
PWM
A
1
VCAPC1
PWM
A
0
ANA7
ANA6
ANA4
9
25
17
Motorola
DSP56F802
Package and Pin-Out Information DSP56F802
MOTOROLA
DSP56F802 Preliminary Technical Data
27
Table 26. DSP56F802 Pin Identification by Pin Number
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
Pin No.
Signal Name
1
PWMA4
9
TCS
17
V
DDA
25
ANA4
2
PWMA5
10
TCK
18
V
SSA
26
ANA6
3
TD1
11
TMS
19
V
DD
27
ANA7
4
TD2
12
TDI
20
V
SS
28
PWMA0
5
TXDO
13
VCAPC2
21
FAULTA0
29
VCAPC1
6
V
SS
14
TDO
22
ANA2
30
PWMA1
7
V
DD
15
TRST
23
VREF 31
PWMA2
8
RXD0
16
RESET
24
ANA3
32
PWMA3
28
DSP56F802 Preliminary Technical Data
MOTOROLA
Figure 20. 32-pin LQFP Mechanical Information (Case 873A)
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DATUM PLANE A, B AND D TO BE DETERMINED
AT DATUM PLANE H.
4.
DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5.
DIMENSIONS b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b DIMENSION
BY MORE THEN 0.08 MM. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION AND
ADJACENT LEAD OR PROTURSION: 0.07 MM.
6.
DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
MM PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC
BODY SIZE DIMENSIONS INCLUDING MOLD
MISMATCH.
7.
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8.
THESE DIMENSIONS APPLY TO THE
FLAT SECTION OF THE LEAD
DIM
A
MIN
MAX
MILLIMETERS
A1
A2
b
b1
0.30
0.40
c
0.09
0.20
c1
0.09
0.16
D
D1
7.00 BSC
e
E
E1
L1
1.00 REF
O
0
7
O1
12
L
0.70
R1
0.08
0.20
R2
1.40
1.60
0.05
1.45
0.15
1.35
0.45
0.30
9.00 BSC
S
0.20 REF
0.80 BSC
9.00 BSC
7.00 BSC
0.50
REF
0.08
--
Thermal Design Considerations
MOTOROLA
DSP56F802 Preliminary Technical Data
29
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, T
J
, in
C can be obtained from the equation:
Equation 1:
Where:
T
A
= ambient temperature C
R
JA
= package junction-to-ambient thermal resistance C/W
P
D
= power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2:
Where:
R
JA
= package junction-to-ambient thermal resistance C/W
R
JC
= package junction-to-case thermal resistance C/W
R
CA
= package case-to-ambient thermal resistance C/W
R
JC
is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, R
CA
. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from R
JA
do not satisfactorily answer whether the
thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.
Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.
Use the value obtained by the equation (T
J
T
T
)/P
D
where T
T
is the temperature of the package
case determined by a thermocouple.
T
J
T
A
P
D
R
JA
(
)
+
=
R
JA
R
JC
R
CA
+
=
30
DSP56F802 Preliminary Technical Data
MOTOROLA
The junction-to-case thermal resistances quoted in this data sheet are determined using the first definition
on page 45. From a practical standpoint, that value is also suitable for determining the junction temperature
from a case thermocouple reading in forced convection environments. In natural convection, using the
junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the
case of the package will estimate a junction temperature slightly hotter than actual. Hence, the new thermal
metric, Thermal Characterization Parameter, or
JT
, has been defined to be (T
J
T
T
)/P
D
. This value gives
a better estimate of the junction temperature in natural convection when using the surface temperature of
the package. Remember that surface temperature readings of packages are subject to significant errors
caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor.
The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the
package with thermally conductive epoxy.
5.2 Electrical Design Considerations
Use the following list of considerations to assure correct DSP operation:
Provide a low-impedance path from the board power supply to each V
DD
pin on the DSP, and from
the board ground to each V
SS
(GND) pin.
The minimum bypass requirement is to place six 0.010.1
F capacitors positioned as close as
possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the ten V
DD
/V
SS
pairs, including V
DDA
/V
SSA.
The VCAP capacitors must be
150 milliohm or less ESR capacitors.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip V
DD
and
V
SS
(GND) pins are less than 0.5 inch per capacitor lead.
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V
DD
and V
SS
.
Bypass the V
DD
and V
SS
layers of the PCB with approximately 100
F, preferably with a high-
grade capacitor such as a tantalum capacitor.
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V
DD
and GND circuits.
Take special care to minimize noise levels on the VREF, V
DDA
and V
SSA
pins.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
Electrical Design Considerations
MOTOROLA
DSP56F802 Preliminary Technical Data
31
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. Designs that do not require
debugging functionality, such as consumer products, should tie these pins together. TRST must be
asserted at power up for proper operation.
Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.
Part 6 Ordering Information
Table 27
lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales
office or authorized distributor to determine availability and to order parts.
Table 27. DSP56F802 Ordering Information
Part
Supply
Voltage
Package Type
Pin
Count
Frequency
(MHz)
Order Number
DSP56F802
3.03.6 V
Low Profile Plastic Quad Flat Pack
(LQFP)
32
80
DSP56F802TA80
DSP56F802/D
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