MOTOROLA CMOS LOGIC DATA

361

MC14511B

BCD-To-Seven Segment

Latch/Decoder/Driver

The MC14511B BCDtoseven segment latch/decoder/driver is

constructed with complementary MOS (CMOS) enhancement mode devices
and NPN bipolar output drivers in a single monolithic structure. The circuit
provides the functions of a 4bit storage latch, an 8421 BCDtoseven
segment decoder, and an output drive capability. Lamp test (LT), blanking
(BI), and latch enable (LE) inputs are used to test the display, to turnoff or
pulse modulate the brightness of the display, and to store a BCD code,
respectively. It can be used with sevensegment lightemitting diodes
(LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts
either directly or indirectly.

Applications include instrument (e.g., counter, DVM, etc.) display driver,

computer/calculator display driver, cockpit display driver, and various clock,
watch, and timer uses.

Low Logic Circuit Power Dissipation

HighCurrent Sourcing Outputs (Up to 25 mA)

Latch Storage of Code

Blanking Input

Lamp Test Provision

Readout Blanking on all Illegal Input Combinations

Lamp Intensity Modulation Capability

Time Share (Multiplexing) Facility

Supply Voltage Range = 3.0 V to 18 V

Capable of Driving Two Lowpower TTL Loads, One Lowpower
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range

Chip Complexity: 216 FETs or 54 Equivalent Gates

Triple Diode Protection on all Inputs

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

(Voltages Referenced to VSS)

Rating

Symbol

Value

Unit

DC Supply Voltage

VDD

0.5 to + 18

Input Voltage, All Inputs

Vin

0.5 to VDD + 0.5

DC Current Drain per Input Pin

Operating Temperature Range

55 to + 125

Power Dissipation per Package

500

Storage Temperature Range

Tstg

65 to + 150

Maximum Output Drive Current

(Source) per Output

IOHmax

Maximum Continuous Output Power

(Source) per Output

POHmax

POHmax = IOH (VDD VOH)
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:

Plastic "P and D/DW" Packages: 7.0 mW/

C From 65

C To 125

Ceramic "L" Packages: 12 mW/

C From 100

C To 125

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1995

REV 3
1/94

MC14511B

L SUFFIX

CERAMIC
CASE 620

ORDERING INFORMATION

MC14XXXBCP

Plastic

MC14XXXBCL

Ceramic

MC14XXXBDW

SOIC

MC14XXXBD

SOIC

TA = 55

to 125

C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

PIN ASSIGNMENT

DW SUFFIX

SOIC

CASE 751G

VDD

VSS

DISPLAY

Inputs

Outputs

LE BI LT

Display

Blank

X = Don't Care
* Depends upon the BCD code previously applied when LE = 0

TRUTH TABLE

MOTOROLA CMOS LOGIC DATA

MC14511B
362

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS

(Voltages Referenced to VSS)

Characteristic

Symbol

VDD

Vdc

 55

125

Unit

Characteristic

Symbol

VDD

Vdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

Output Voltage

"0" Level

Vin = VDD or 0

"1" Level

Vin = 0 or VDD

VOL

5.0

10
15

--
--
--

0.05
0.05
0.05

--
--
--

0
0
0

0.05
0.05
0.05

--
--
--

0.05
0.05
0.05

Vdc

"1" Level

Vin = 0 or VDD

VOH

5.0

10
15

4.1
9.1

14.1

--
--
--

4.1
9.1

14.1

4.57
9.58

14.59

--
--
--

4.1
9.1

14.1

--
--
--

Vdc

Input Voltage #

"0" Level

(VO = 3.8 or 0.5 Vdc)
(VO = 8.8 or 1.0 Vdc)
(VO = 13.8 or 1.5 Vdc)

"1" Level

(VO = 0.5 or 3.8 Vdc)
(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)

VIL

5.0

10
15

--
--
--

1.5
3.0
4.0

--
--
--

2.25
4.50
6.75

1.5
3.0
4.0

--
--
--

1.5
3.0
4.0

Vdc

"1" Level

(VO = 0.5 or 3.8 Vdc)
(VO = 1.0 or 8.8 Vdc)
(VO = 1.5 or 13.8 Vdc)

VIH

5.0

10
15

3.5
7.0

--
--
--

3.5
7.0

2.75
5.50
8.25

--
--
--

3.5
7.0

--
--
--

Vdc

Output Drive Voltage

(IOH = 0 mA)

Source

(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)

VOH

5.0

4.1

3.9

3.4

--
--
--
--
--
--

4.1

3.9

3.4

4.57
4.24
4.12
3.94
3.70
3.54

--
--
--
--
--
--

4.1

3.5

3.0

--
--
--
--
--
--

Vdc

(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)

9.1

9.0

8.6

--
--
--
--
--
--

9.1

9.0

8.6

9.58
9.26
9.17
9.04
8.90
8.70

--
--
--
--
--
--

9.1

8.6

8.2

--
--
--
--
--
--

Vdc

(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)
(IOH = 20 mA)
(IOH = 25 mA)

14.1

13.6

--
--
--
--
--
--

14.1

13.6

14.59
14.27
14.18
14.07
13.95
13.70

--
--
--
--
--
--

14.1

13.6

13.2

--
--
--
--
--
--

Vdc

Output Drive Current

(VOL = 0.4 V)

Sink

(VOL = 0.5 V)
(VOL = 1.5 V)

IOL

5.0

10
15

0.64

1.6
4.2

--
--
--

0.51

1.3
3.4

0.88
2.25

8.8

--
--
--

0.36

0.9
2.4

--
--
--

mAdc

Input Current

Iin

0.1

0.00001

0.1

1.0

Adc

Input Capacitance

Cin

5.0

7.5

Quiescent Current

(Per Package) Vin = 0 or VDD,
Iout = 0

IDD

5.0

10
15

--
--
--

5.0

10
20

--
--
--

0.005
0.010
0.015

5.0

10
20

--
--
--

150
300
600

Adc

Total Supply Current**

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

5.0

10
15

IT = (1.9

A/kHz) f + IDD

IT = (3.8

A/kHz) f + IDD

IT = (5.7

A/kHz) f + IDD

Adc

#Noise immunity specified for worstcase input combination.

Noise Margin for both "1" and "0" level =

1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD = 10 Vdc
2.5 Vdc min @ VDD = 15 Vdc

** The formulas given are for the typical characteristics only at 25

To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + 3.5 x 103 (CL 50) VDDf

where: IT is in

A (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.

MOTOROLA CMOS LOGIC DATA

363

MC14511B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS*

(CL = 50 pF, TA = 25

Characteristic

Symbol

VDD

Vdc

Min

Typ

Max

Unit

Output Rise Time

tTLH = (0.40 ns/pF) CL + 20 ns
tTLH = (0.25 ns/pF) CL + 17.5 ns
tTLH = (0.20 ns/pF) CL + 15 ns

tTLH

5.0

10
15

--
--
--

40
30
25

80
60
50

Output Fall Time

tTHL = (1.5 ns/pF) CL + 50 ns
tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns

tTHL

5.0

10
15

--
--
--

125

75
65

250
150
130

Data Propagation Delay Time

tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns

tPLH

5.0

10
15

--
--
--

640
250
175

1280

500
350

tPHL = (1.3 ns/pF) CL + 655 ns
tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns

tPHL

5.0

10
15

--
--
--

720
290
200

1440

580
400

Blank Propagation Delay Time

tPLH = (0.30 ns/pF) CL + 585 ns
tPLH = (0.25 ns/pF) CL + 187.5 ns
tPLH = (0.15 ns/pF) CL + 142.5 ns

tPLH

5.0

--
--
--

600
200
150

750
300
220

tPHL = (0.85 ns/pF) CL + 442.5 ns
tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns

tPHL

5.0

10
15

--
--
--

485
200
160

970
400
320

Lamp Test Propagation Delay Time

tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH = (0.20 ns/pF) CL + 80 ns

tPLH

5.0

10
15

--
--
--

313
125

625
250
180

tPHL = (1.3 ns/pF) CL + 248 ns
tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns

tPHL

5.0

10
15

--
--
--

313
125

625
250
180

Setup Time

tsu

5.0

10
15

100

40
30

--
--
--

Hold Time

5.0

10
15

60
40
30

--
--
--

Latch Enable Pulse Width

tWL

5.0

10
15

520
220
130

260

110

--
--
--

* The formulas given are for the typical characteristics only.

This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; how-

ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit. A destructive high current mode may occur if Vin and Vout are not constrained to the range VSS

(Vin or

Vout)

VDD.

Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to

VSS and are at a logical 1 (See Maximum Ratings).

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MC14511B

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