MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
1-of-8 Decoder/Demultiplexer
HighPerformance SiliconGate CMOS
The MC54/74HC138A is identical in pinout to the LS138. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC138A decodes a threebit Address to oneofeight activelow
outputs. This device features three Chip Select inputs, two activelow and
one activehigh to facilitate the demultiplexing, cascading, and chipselect-
ing functions. The demultiplexing function is accomplished by using the
Address inputs to select the desired device output; one of the Chip Selects is
used as a data input while the other Chip Selects are held in their active
states.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 100 FETs or 29 Equivalent Gates
LOGIC DIAGRAM
7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Y7
9
10
11
12
13
14
15
3
2
1
CS1
CS2
A0
A1
A2
ACTIVELOW
OUTPUTS
ADDRESS
INPUTS
CS3
CHIP
SELECT
INPUTS
5
4
6
PIN 16 = VCC
PIN 8 = GND
Inputs
Outputs
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
H
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
FUNCTION TABLE
H = high level (steady state); L = low level (steady state);
X = don't care
MC54/74HC138A
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
A0
CS2
A2
A1
Y7
CS1
CS3
GND
Y3
Y2
Y1
Y0
VCC
Y5
Y4
Y6
D SUFFIX
SOIC PACKAGE
CASE 751B05
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
1
16
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F01
J SUFFIX
CERAMIC PACKAGE
CASE 62010
1
16
MC54/74HC138A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP
SOIC Package
TSSOP Package
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
260
300
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
Ceramic DIP: 10 mW/
_
C from 100
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: 6.1 .W/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 2)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
Test Conditions
VCC
V
55
_
C to
25
_
C
v
85
_
C
v
125
_
C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout|
v
2.4 mA
|Iout|
v
4.0 mA
|Iout|
v
5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC138A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
3
MOTOROLA
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Unit
Guaranteed Limit
VCC
V
Test Conditions
Parameter
Symbol
Unit
v
125
_
C
v
85
_
C
55
_
C to
25
_
C
VCC
V
Test Conditions
Parameter
Symbol
VOL
Maximum LowLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout|
v
2.4 mA
|Iout|
v
4.0 mA
|Iout|
v
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
4
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
55
_
C to
25
_
C
v
85
_
C
v
125
_
C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 4)
2.0
3.0
4.5
6.0
135
90
27
23
170
125
34
29
205
165
41
35
ns
tPLH,
tPHL
Maximum Propagation Delay, CS1 to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
85
22
19
140
100
28
24
165
125
33
28
ns
tPLH,
tPHL
Maximum Propagation Delay, CS2 or CS3 to Output Y
(Figures 3 and 4)
2.0
3.0
4.5
6.0
120
90
24
20
150
120
30
26
180
150
36
31
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
Cin
Maximum Input Capacitance
--
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Package)*
Typical @ 25
C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per Package)*
55
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
MC54/74HC138A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
4
Figure 1.
50%
tPHL
tPLH
VCC
GND
Figure 2.
VALID
VALID
OUTPUT Y
50%
tf
tr
VCC
GND
tPLH
tTLH
90%
50%
10%
OUTPUT Y
INPUT CS1
tPHL
90%
50%
10%
tTHL
INPUT A
SWITCHING WAVEFORMS
tTHL
tTLH
VCC
GND
tr
tPHL
tPLH
OUTPUT Y
INPUT
CS2, CS3
90%
50%
10%
90%
50%
10%
Figure 3.
tf
* Includes all probe and jig capacitance
Figure 4. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
Address inputs. These inputs, when the chip is selected,
determine which of the eight outputs is activelow.
CONTROL INPUTS
CS1, CS2, CS3 (Pins 6, 4, 5)
Chip select inputs. For CS1 at a high level and CS2, CS3
at a low level, the chip is selected and the outputs follow the
Address inputs. For any other combination of CS1, CS2, and
CS3, the outputs are at a logic high.
OUTPUTS
Y0 Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
Activelow Decoded outputs. These outputs assume a low
level when addressed and the chip is selected. These out-
puts remain high when not addressed or the chip is not
selected.
MC54/74HC138A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
5
MOTOROLA
A0
A1
A2
CS3
CS2
CS1
1
2
3
4
5
6
15
14
13
12
11
10
9
7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y0
EXPANDED LOGIC DIAGRAM
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