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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
31
REV 6
Motorola, Inc. 1995
10/95
Quad 2-Input OR Gate
HighPerformance SiliconGate CMOS
The MC54/74HC32A is identical in pinout to the LS32. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 48 FETs or 12 Equivalent Gates
3
Y1
1
A1
PIN 14 = VCC
PIN 7 = GND
LOGIC DIAGRAM
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Y = A+B
Pinout: 14Lead Packages (Top View)
13
14
12
11
10
9
8
2
1
3
4
5
6
7
VCC
B4
A4
Y4
B3
A3
Y3
A1
B1
Y1
A2
B2
Y2
GND
L
L
H
H
L
H
L
H
MC54/74HC32A
FUNCTION TABLE
Inputs
Output
A
B
L
H
H
H
Y
D SUFFIX
SOIC PACKAGE
CASE 751A03
N SUFFIX
PLASTIC PACKAGE
CASE 64606
ORDERING INFORMATION
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Ceramic
Plastic
SOIC
TSSOP
1
14
1
14
DT SUFFIX
TSSOP PACKAGE
CASE 948B03
J SUFFIX
CERAMIC PACKAGE
CASE 63208
1
14
1
14
MC54/74HC32A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
32
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP
SOIC Package
TSSOP Package
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP
260
300
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
Ceramic DIP: 10 mW/
_
C from 100
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC32A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
33
MOTOROLA
DC CHARACTERISTICS
(Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
Condition
VCC
V
55 to 25
C
85
C
125
C
Unit
VIH
Minimum HighLevel Input Voltage
Vout = 0.1V or VCC 0.1V
|Iout|
20
A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum LowLevel Input Voltage
Vout = 0.1V or VCC 0.1V
|Iout|
20
A
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout|
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin =VIH or VIL
|Iout|
2.4mA
|Iout|
4.0mA
|Iout|
5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL
Maximum LowLevel Output
Voltage
Vin = VIH or VIL
|Iout|
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout|
2.4mA
|Iout|
4.0mA
|Iout|
5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
1.0
10
40
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
AC CHARACTERISTICS
(CL = 50pF, Input tr = tf = 6ns)
VCC
V
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to 25
C
85
C
125
C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Buffer)*
Typical @ 25
C, VCC = 5.0 V, VEE = 0 V
pF
CPD
Power Dissipation Capacitance (Per Buffer)*
20
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
MC54/74HC32A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
34
Figure 1. Switching Waveforms
OUTPUT Y
INPUT
A OR B
CL*
*Includes all probe and jig capacitance
TEST
POINT
90%
50%
10%
tTLH
DEVICE
UNDER
TEST
OUTPUT
Figure 2. Test Circuit
Y
A
B
Figure 3. Expanded Logic Diagram
(1/4 of the Device)
tTHL
tPLH
tPHL
tr
tf
GND
VCC
90%
50%
10%
MC54/74HC32A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
35
MOTOROLA
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC DIP PACKAGE
CASE 63208
ISSUE Y
MIN
MIN
MAX
MAX
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
J
K
L
M
N
0.785
0.280
0.200
0.020
0.065
0.015
0.170
15
0.040
0.750
0.245
0.155
0.015
0.055
0.008
0.125
0
0.020
19.94
7.11
5.08
0.50
1.65
0.38
4.31
15
1.01
19.05
6.23
3.94
0.39
1.40
0.21
3.18
0
0.51
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
14
8
1
7
-A-
-B-
-T-
SEATING
PLANE
F
G
N
K
C
L
M
0.25 (0.010)
T
A
M
S
0.25 (0.010)
T
B
M
S
J
14 PL
D
14 PL
N SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
1
7
14
8
B
A
F
H
G
D
K
C
N
L
J
M
SEATING
PLANE
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.715
0.770
18.16
19.56
B
0.240
0.260
6.10
6.60
C
0.145
0.185
3.69
4.69
D
0.015
0.021
0.38
0.53
F
0.040
0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052
0.095
1.32
2.41
J
0.008
0.015
0.20
0.38
K
0.115
0.135
2.92
3.43
L
0.300 BSC
7.62 BSC
M
0
10
0
10
N
0.015
0.039
0.39
1.01
_
_
_
_
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