NON-DISCLOSURE AGREEMENT REQUIRED

Technical Data

Technical Data

MC68HC05P18A

MOTOROLA

Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.

MC68HC05P18A

Technical Data

MOTOROLA

List of Sections

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Technical Data -- MC68HC05P18A

List of Sections

Section 1. General Description . . . . . . . . . . . . . . . . . . . . 15

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 33

Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Section 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . 49

Section 7. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . 55

Section 8. 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Section 9. Serial Input/Output Ports (SIOP) . . . . . . . . . . 77

Section 10. EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Section 11. Analog-to-Digital (A/D) Converter . . . . . . . . 91

Section 12. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . 97

Section 13. Electrical Specifications . . . . . . . . . . . . . . . 115

Section 14. Mechanical Specifications . . . . . . . . . . . . . 125

Section 15. Ordering Information . . . . . . . . . . . . . . . . . 127

MC68HC05P18A

Technical Data

MOTOROLA

Table of Contents

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Technical Data -- MC68HC05P18A

Table of Contents

Section 1. General Description

1.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

1.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

1.4

Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

1.5

Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

1.5.1

Power Supply (V

and V

) . . . . . . . . . . . . . . . . . . . . . . . .20

1.5.2

Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .20

1.5.2.1

Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

1.5.2.2

Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5.2.3

External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5.3

Reset

(

RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5.4

Port A (PA0璓A7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5.5

Port B (PB5/SDO, PB6/SDI, and PB7/SCK) . . . . . . . . . . . .23

1.5.6

Port C (PC0璓C2, PC3/AD3, PC4/AD2, PC5/AD1,

PC6/AD0, and PC7/V

REFH

) . . . . . . . . . . . . . . . . . . . . . . .23

1.5.7

Port D (PD5/CKOUT and PD7/TCAP) . . . . . . . . . . . . . . . . .23

1.5.8

Timer Output Compare (TCMP) . . . . . . . . . . . . . . . . . . . . . .23

1.5.9

Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . .24

1.5.10

CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Section 2. Memory Map

2.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.3

User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.4

I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.5

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

2.6

ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

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Technical Data

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Table of Contents

MOTOROLA

Section 3. Central Processor Unit (CPU)

3.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.3

CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.3.1

Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.3.2

Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.3.3

Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.3.4

Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3.3.5

Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .37

3.4

Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Section 4. Interrupts

4.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.3

CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.4

Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

4.4.1

Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .42

4.4.2

Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . .42

4.4.3

Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

4.4.3.1

External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . .43

4.4.3.2

Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .43

4.4.3.3

Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .44

4.4.3.4

Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .44

Section 5. Resets

5.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

5.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

5.3

External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

5.4

Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

5.4.1

Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

5.4.2

Computer Operating Properly (COP) Reset . . . . . . . . . . . . .47

5.4.3

Low-Voltage Reset (LVR). . . . . . . . . . . . . . . . . . . . . . . . . . .48

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Technical Data

MOTOROLA

Table of Contents

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Section 6. Operating Modes

6.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

6.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

6.3

User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

6.4

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

6.4.1

STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

6.4.1.1

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

6.4.1.2

Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

6.4.2

WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

6.5

COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .54

Section 7. Input/Output (I/O) Ports

7.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

7.3

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

7.4

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

7.5

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

7.6

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

7.7

I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Section 8. 16-Bit Timer

8.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

8.3

Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

8.4

Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

8.5

Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

8.6

Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

8.7

Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

8.8

Timer Operation during Wait Mode and Halt Mode . . . . . . . . .74

8.9

Timer Operating during Stop Mode . . . . . . . . . . . . . . . . . . . . .74

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MC68HC05P18A

Table of Contents

MOTOROLA

Section 9. Serial Input/Output Ports (SIOP)

9.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

9.3

SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

9.3.1

Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

9.3.2

Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

9.3.3

Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . .79

9.4

SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

9.4.1

SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

9.4.2

SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

9.4.3

SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Section 10. EEPROM

10.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

10.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

10.3

EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . .86

10.4

Programming/Erasing Procedures . . . . . . . . . . . . . . . . . . . . . .88

Section 11. Analog-to-Digital (A/D) Converter

11.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

11.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

11.3

Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

11.3.1

Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

11.3.2

Reference Supply Voltage (V

REFH

) . . . . . . . . . . . . . . . . . . .92

11.3.3

Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

11.4

Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

11.5

Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

11.5.1

Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

11.5.2

Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . .93

11.5.3

Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .94

11.6

A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . .94

11.7

A/D Conversion Value Data Register . . . . . . . . . . . . . . . . . . . .96

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Table of Contents

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11.8

A/D Subsystem Operation during Wait Mode

and Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

11.9

A/D Subsystem Operation during Stop Mode. . . . . . . . . . . . . .96

Section 12. Instruction Set

12.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

12.3

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

12.3.1

Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

12.3.2

Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

12.3.3

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

12.3.4

Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

12.3.5

Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

12.3.6

Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

12.3.7

Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

12.3.8

Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

12.4

Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

12.4.1

12.4.2

Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .103

12.4.3

Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .104

12.4.4

Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .106

12.4.5

Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

12.5

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Section 13. Electrical Specifications

13.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

13.2

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

13.3

Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .116

13.4

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

13.5

Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

13.6

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .118

13.7

Active Reset Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .119

13.8

A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .120

13.9

SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

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13.10 PD5 Clock Out Timing (PD5 Clock Out Option Enabled) . . . .122

13.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Section 14. Mechanical Specifications

14.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

14.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

14.3

28-Pin Plastic Dual In-Line Package (Case #710) . . . . . . . . .126

14.4

28-Pin Small Outline Package (Case #751F) . . . . . . . . . . . . .126

Section 15. Ordering Information

15.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

15.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

15.3

MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

MC68HC05P18A

Technical Data

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List of Figures

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Technical Data -- MC68HC05P18A

List of Figures

Figure

Title

Page

1-1

MC68HC05P18A Block Diagram . . . . . . . . . . . . . . . . . . . . . . .17

1-2

User Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

1-3

Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2-1

MC68HC05P18A User Mode Memory Map . . . . . . . . . . . . . . .27

2-2

MC68HC05P18A I/O and Control Registers

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2-3

I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

3-1

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3-2

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3-3

Index Register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3-4

Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3-5

Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3-6

Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .37

4-1

Interrupt Processing Flowchart . . . . . . . . . . . . . . . . . . . . . . . . .41

5-1

Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

5-2

COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

6-1

Stop, Halt, and Wait Modes Flowchart . . . . . . . . . . . . . . . . . . .51

7-1

Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

7-2

Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

7-3

Port C I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

7-4

Port D I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

NON-DISCLOSURE AGREEMENT REQUIRED

List of Figures

Technical Data

MC68HC05P18A

List of Figures

MOTOROLA

Figure

Title

Page

8-1

16-Bit Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .64

8-2

Timer Counter Registers (TMRH/TMRL) . . . . . . . . . . . . . . . . .66

8-3

Alternate Counter Registers (ACRH/ACRL) . . . . . . . . . . . . . . .66

8-4

State Timing Diagram for Timer Overflow . . . . . . . . . . . . . . . .67

8-5

State Timing Diagram for Timer Reset . . . . . . . . . . . . . . . . . . .67

8-6

Output Compare Registers (OCRH/OCRL) . . . . . . . . . . . . . . .68

8-7

Output Compare Software Initialization Example . . . . . . . . . . .69

8-8

Input Capture Registers (ICRH/ICRL) . . . . . . . . . . . . . . . . . . .70

8-9

State Timing Diagram for Input Capture . . . . . . . . . . . . . . . . . .71

8-10

Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . .72

8-11

Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . .73

9-1

SIOP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

9-2

SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

9-3

SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . .80

9-4

SIOP Status Register (SSR). . . . . . . . . . . . . . . . . . . . . . . . . . .82

9-5

SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

10-1

EEPROM Programming Register (EEPROG) . . . . . . . . . . . . .86

11-1

A/D Status and Control Register (ADSCR). . . . . . . . . . . . . . . .94

11-2

A/D Conversion Value Data Register (ADC) . . . . . . . . . . . . . .96

13-1

SIOP Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

13-2

PD5 Clock Out Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

13-3

Power-On Reset and External Reset Timing Diagram . . . . . .124

MC68HC05P18A

Technical Data

MOTOROLA

List of Tables

NON-DISCLOSURE AGREEMENT REQUIRED

Technical Data -- MC68HC05P18A

List of Tables

Table

Title

Page

4-1

Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . . .40

6-1

COP Watchdog Timer Recommendations . . . . . . . . . . . . . . . .54

7-1

Port A I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7-2

Port B I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7-3

Port C I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7-4

Port D I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

10-1

Erase Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

11-1

A/D Multiplexer Input Channel Assignments . . . . . . . . . . . . . .95

12-1

12-2

Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .103

12-3

Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .105

12-4

Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .106

12-5

Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

12-6

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

12-7

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

15-1

MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

MC68HC05P18A

Technical Data

MOTOROLA

General Description

NON-DISCLOSURE AGREEMENT REQUIRED

Technical Data -- MC68HC05P18A

Section 1. General Description

1.1 Contents

1.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

1.4

Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

1.5

Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

1.5.1

Power Supply (V

and V

) . . . . . . . . . . . . . . . . . . . . . . . .20

1.5.2

Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . .20

1.5.2.1

Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

1.5.2.2

Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5.2.3

External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5.3

Reset

(

RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5.4

Port A (PA0璓A7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

1.5.5

Port B (PB5/SDO, PB6/SDI, and PB7/SCK) . . . . . . . . . . . .23

1.5.6

Port C (PC0璓C2, PC3/AD3, PC4/AD2, PC5/AD1,

PC6/AD0, and PC7/V

REFH

) . . . . . . . . . . . . . . . . . . . . . . .23

1.5.7

Port D (PD5/CKOUT and PD7/TCAP) . . . . . . . . . . . . . . . . .23

1.5.8

Timer Output Compare (TCMP) . . . . . . . . . . . . . . . . . . . . . .23

1.5.9

Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . .24

1.5.10

CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

NON-DISCLOSURE AGREEMENT REQUIRED

General Description

Technical Data

MC68HC05P18A

General Description

MOTOROLA

1.2 Introduction

The Motorola MC68HC05P18A is a low-cost microcontroller with:

�

4-channel, 8-bit analog-to-digital (A/D) converter

�

16-bit timer with output compare and input capture

�

Serial communications port (SIOP)

�

Computer operating properly (COP) watchdog timer

The HC05 central processor unit (CPU) core contains:

�

192 bytes of random-access memory (RAM)

�

8064 bytes of user read-only memory (ROM)

�

128 bytes of electrically erasable programmable read-only
memory (EEPROM)

�

21 input/output (I/O) pins (20 bidirectional, 1 input-only)

This device is available in:

�

28-pin plastic dual in-line package (PDIP)

�

28 pin small-outline integrated circuit package (SOIC)

A functional block diagram of the MC68HC05P18A is shown in

Figure 1-1

General Description

Introduction

MC68HC05P18A

Technical Data

MOTOROLA

General Description

NON-DISCLOSURE AGREEMENT REQUIRED

Figure 1-1. MC68HC05P18A Block Diagram

NOTE:

A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.

PH2

A/ D CONVERTER

16-BIT TIMER

1 INPUT CAPTURE

1 OUTPUT COMPARE

PORT D LOGIC

COP

OSC

CONDITION CODE

1 1 1

N Z C

INDEX REGISTER

CPU CONTROL

0 0 0

STK PNTR

RESET

OSC1

OSC2

PD7/TCAP

SRAM -- 192 BYTES

USER ROM -- 8064 BYTES

TCMP

IRQ

ALU

68HC05 CPU

ACCUMULATOR

PROGRAM COUNTER

CPU REGISTERS

�

PA7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

A
T
A

DIRECTION REGISTER

POR

T A

PB5/SDO

PB6/SDI

PB7/SCK

PORT B AND

SIOP

REGISTERS

AND LOGIC

PD5/CKOUT

A
T
A

DIRECTION REGISTER

PC3/AD3

PC4/AD2

PC5/AD1

PC6/AD0

PC7/V

REFH

PC2

POR

T C

MUX

PC1

PC0

EEPROM -- 128 BYTES

�

NON-DISCLOSURE AGREEMENT REQUIRED

General Description

Technical Data

MC68HC05P18A

General Description

MOTOROLA

1.3 Features

Features of the MC68HC05P18A include:

�

Low-cost, HC05 core running at 2-MHz bus speed, or the 4-MHz
high-speed option

�

28-pin DIP or SOIC package

�

On-chip crystal/ceramic resonator

�

8064 bytes of user ROM including:

�

48 bytes of page zero ROM

�

16 bytes of user vectors

�

192 bytes of on-chip RAM

�

128 bytes of EEPROM

�

Low-voltage reset (LVR)

�

Four-channel, 8-bit A/D converter

�

Serial communications port

�

COP watchdog timer with active pull down on RESET

�

16-bit timer with output compare and input capture

�

Edge- and level-sensitive interrupt or edge-sensitive only (mask
option)

�

20 bidirectional I/O lines and 1 input-only line

�

Individually mask selectable pullups/interrupts on port A pins

�

High current sink and source on two I/O pins, PC0 and PC1

�

Power-saving stop mode and wait mode instructions and stop
conversion to halt mode (mask option)

�

Mask option for clock output pin

General Description

Mask Options

MC68HC05P18A

Technical Data

MOTOROLA

General Description

NON-DISCLOSURE AGREEMENT REQUIRED

1.4 Mask Options

The MC68HC05P18A has eight mask options:

1. IRQ is edge- and level-sensitive or edge-sensitive only.

2. SIOP MSB (most-significant bit) first or LSB (least-significant bit)

first

3. SIOP clock rate set to OSC divided by 2, 4, 8, 16, 32, 64, 128, or

256

4. COP watchdog timer enabled or disabled

5. Stop instruction enabled or converted to halt mode

6. Option to enable clock output pin to replace PD5

7. Option to individually enable pullups/interrupts on each of the

eight port A pins

8. LVR enabled or disabled

1.5 Functional Pin Description

This subsection describes the functionality of each pin on the
MC68HC05P18A package.

NOTE:

For pins connected to subsystems described in other sections, a
reference to the section is given instead of a detailed functional
description.

The pinout is shown in

Figure 1-2

NON-DISCLOSURE AGREEMENT REQUIRED

General Description

Technical Data

MC68HC05P18A

General Description

MOTOROLA

Figure 1-2. User Mode Pinout

1.5.1 Power Supply (V

and V

)

Power is supplied to the MCU through V

and V

. V

is connected

to a regulated +5-volt supply and V

is connected to ground.

Very fast signal transitions occur on the MCU pins. The short rise and
fall times place very high short-duration current demands on the power
supply. To prevent noise problems, take special care to provide good
power supply bypassing at the MCU. Use bypass capacitors with good
high-frequency characteristics and position them as close to the MCU as
possible. Bypassing requirements vary, depending on how heavily the
MCU pins are loaded.

1.5.2 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the control connections for the on-chip
oscillator. The OSC1 and OSC2 pins can accept:

1. A crystal or ceramic resonator, as shown in

Figure 1-3

(a)

2. An external clock signal, as shown in

Figure 1-3

(b)

RESET

IRQ

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

SDO/PB5

SDI/PB6

SCK/PB7

OSC1

OSC2

PD7/TCAP

TCMP

PD5/CKOUT

PC0

PC1

PC2

PC3/AD3

PC4/AD2

PC5/AD1

PC6/AD0

PC7/V

REFH

General Description

Functional Pin Description

MC68HC05P18A

Technical Data

MOTOROLA

General Description

NON-DISCLOSURE AGREEMENT REQUIRED

The frequency, f

OSC

, of the oscillator or external clock source is divided

by two to produce the internal PH2 bus clock operating frequency, f

The oscillator cannot be turned off by software if the stop-to-halt
conversion is enabled via mask option.

Figure 1-3. Oscillator Connections

1.5.2.1 Crystal

The circuit in

Figure 1-3

(a) shows a typical oscillator circuit for an

AT-cut, parallel resonant crystal.

NOTE:

The crystal manufacturer's recommendations should be followed, as the
crystal parameters determine the external component values required to
provide maximum stability and reliable startup.

The load capacitance values used in the oscillator circuit design should
include all stray capacitances. Mount the crystal and components as
close as possible to the pins for startup stabilization and to minimize
output distortion.

TO V

OR STOP

TO V

OR STOP

(a)

Crystal or Ceramic
Resonator Connections

(b)

External Clock Source
Connections

OSC1

OSC2

MCU

37 pF

4.7 M

MCU

OSC1

OSC2

UNCONNECTED

EXTERNAL CLOCK

NON-DISCLOSURE AGREEMENT REQUIRED

General Description

Technical Data

MC68HC05P18A

General Description

MOTOROLA

1.5.2.2 Ceramic Resonator

In cost-sensitive applications, a ceramic resonator can be used in place
of the crystal. The circuit in

Figure 1-3

(a) can be used for a ceramic

resonator.

NOTE:

The crystal manufacturer's recommendations should be followed, as the
crystal parameters determine the external component values required to
provide maximum stability and reliable startup.

The load capacitance values used in the oscillator circuit design should
include all stray capacitances. Mount the resonator and components as
close as possible to the pins for startup stabilization and to minimize
output distortion.

1.5.2.3 External Clock

An external clock from another CMOS-compatible device can be
connected to the OSC1 input, with the OSC2 input not connected, as
shown in

Figure 1-3

(b).

1.5.3 Reset (RESET)

Driving this input low resets the MCU to a known startup state. As an
output pin, the RESET pin indicates that an internal MCU reset has
occurred. The RESET pin contains an internal Schmitt trigger to improve
its noise immunity. Refer to

Section 5. Resets

1.5.4 Port A (PA0璓A7)

Port A is comprised of eight I/O pins (PA0璓A7). The state of any pin is
software programmable and all port A lines are configured as inputs
during power-on or reset. Eight mask options can be chosen to enable
pullups and interrupts (active low) on port A pins (see

1.4 Mask

Options

). Refer to

Section 7. Input/Output (I/O) Ports

and

Section 4.

Interrupts

General Description

Functional Pin Description

MC68HC05P18A

Technical Data

MOTOROLA

General Description

NON-DISCLOSURE AGREEMENT REQUIRED

1.5.5 Port B (PB5/SDO, PB6/SDI, and PB7/SCK)

Port B is comprised of three I/O pins which are shared with the SIOP
communications subsystem. The state of any pin is software
programmable and all port B lines are configured as inputs during
power-on or reset. Refer to

Section 7. Input/Output (I/O) Ports

and

Section 9. Serial Input/Output Ports (SIOP)

1.5.6 Port C (PC0璓C2, PC3/AD3, PC4/AD2, PC5/AD1, PC6/AD0, and PC7/V

REFH

)

Port C is comprised of eight I/O pins which are shared with the A/D
converter subsystem. The state of any pin is software programmable
and all port C lines are configured as inputs during power-on or reset.
Port pins PC0 and PC1 are capable of sourcing and sinking high
currents. Refer to

Section 7. Input/Output (I/O) Ports

1.5.7 Port D (PD5/CKOUT and PD7/TCAP)

Port D is comprised of two I/O pins and one of them is shared with the
16-bit timer subsystem. The state of PD5/CKOUT is software
programmable and is configured as an input during power-on or reset.
PD7 is always an input; it may be read at any time, regardless of the
mode of operation the 16-bit timer may be in. Refer to

Section 7.

Input/Output (I/O) Ports

and

Section 8. 16-Bit Timer

NOTE:

A mask option turns the PD5/CKOUT pin into a clock output which is a
buffered OSC2 signal with a CMOS output driver. The clock output or the
port D function must be chosen with the mask option and is not alterable
in software.

1.5.8 Timer Output Compare (TCMP)

TCMP is the output from the 16-bit timer's output compare function. It is
low after reset. Refer to

Section 8. 16-Bit Timer

NON-DISCLOSURE AGREEMENT REQUIRED

General Description

Technical Data

MC68HC05P18A

General Description

MOTOROLA

1.5.9 Maskable Interrupt Request (IRQ)

This input pin drives the asynchronous interrupt function of the MCU.
The MCU completes the current instruction being executed before it
responds to the IRQ interrupt request. When IRQ is driven low, the event
is latched internally to signify an interrupt has been requested. When the
MCU completes its current instruction, the interrupt latch is tested. If the
interrupt latch is set, and the interrupt mask bit (I bit) in the condition
code register (CCR) is clear, the MCU begins the interrupt sequence.

Depending on the mask option selected, the IRQ pin triggers this
interrupt on either a negative going edge at the IRQ pin and/or while the
IRQ pin is held in the low state. In either case, the IRQ pin must be held
low for at least one t

ILIH

time period.

If the edge- and level-sensitive mask option is selected, the IRQ input
requires an external resistor connected to V

for a wired-OR operation.

If the IRQ pin is not used, it must be tied to the V

supply. The IRQ pin

contains an internal Schmitt trigger as part of its input circuitry to improve
noise immunity. Refer to

Section 4. Interrupts

1.5.10 CPU Core

The MC68HC05P18A uses a standard M68HC05 series CPU core. A
description of the instruction set is in

Section 12. Instruction Set

MC68HC05P18A

Technical Data

MOTOROLA

Memory Map

NON-DISCLOSURE AGREEMENT REQUIRED

Technical Data -- MC68HC05P18A

Section 2. Memory Map

2.1 Contents

2.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.3

User Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.4

I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.5

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

2.6

ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

2.2 Introduction

The MC68HC05P18A utilizes 14 address lines to access an internal
memory space covering 16 Kbytes. This memory space is divided into:

�

Input/output (I/O)

�

Random-access memory (RAM)

�

Electrically erasable programmable read-only memory
(EEPROM)

�

Read-only memory (ROM)

Memory Map

I/O and Control Registers

MC68HC05P18A

Technical Data

MOTOROLA

Memory Map

NON-DISCLOSURE AGREEMENT REQUIRED

Figure 2-1. MC68HC05P18A User Mode Memory Map

0000

0031
0032

0079
0080

0191
0192

0255
0256
0271
0272

0399
0400

8127
8128

16127
16128

16367
16368

16383

$0000

$001F

$0020

$004F

$0050

$00BF
$00C0

$00FF

$0100

$010F

$0140

$01BF
$01C0

$1FBF
$1FC0

$3EFF

$3F00

$3FEF

$3FF0

$3FFF

RESET VECTOR (LOW BYTE)

RESET VECTOR (HIGH BYTE)

SWI VECTOR (LOW BYTE)

SWI VECTOR (HIGH BYTE)

IRQ VECTOR (LOW BYTE)

IRQ VECTOR (HIGH BYTE)

TIMER VECTOR (LOW BYTE)

TIMER VECTOR (HIGH BYTE)

UNIMPLEMENTED

$3FF6

$3FF7

$3FF8

$3FF9

$3FFA

$3FFB

$3FFC

$3FFD

$3FFE

$3FFF

UNIMPLEMENTED

$3FF5

UNIMPLEMENTED

$3FF4

UNIMPLEMENTED

$3FF3

UNIMPLEMENTED

$3FF2

UNIMPLEMENTED

$3FF1

COP CONTROL REGISTER

$3FF0

$001F

$0000

STACK

64 BYTES

INTERNAL RAM

192 BYTES

I/O

32 BYTES

USER VECTORS ROM

16 BYTES

RESERVED FOR

TEST

240 BYTES

USER ROM

8000 BYTES

USER ROM

48 BYTES

I/O REGISTERS

SEE

FIGURE 2-2

EEPROM

128 BYTES

UNUSED

7728 BYTES

NON-DISCLOSURE AGREEMENT REQUIRED

Memory Map

Technical Data

MC68HC05P18A

Memory Map

MOTOROLA

Figure 2-2. MC68HC05P18A I/O and Control Registers

Memory Map

PORT A DATA REGISTER

$0000

PORT B DATA REGISTER

$0001

PORT C DATA REGISTER

$0002

PORT D DATA REGISTER

$0003

PORT A DATA DIRECTION REGISTER

$0004

PORT B DATA DIRECTION REGISTER

$0005

PORT C DATA DIRECTION REGISTER

$0006

PORT D DATA DIRECTION REGISTER

$0007

UNIMPLEMENTED

$0008

UNIMPLEMENTED

$0009

SIOP CONTROL REGISTER

$000A

SIOP STATUS REGISTER

$000B

SIOP DATA REGISTER

$000C

UNIMPLEMENTED

$000D

UNIMPLEMENTED

$000E

UNIMPLEMENTED

$000F

UNIMPLEMENTED

$0010

UNIMPLEMENTED

$0011

TIMER CONTROL REGISTER

$0012

TIMER STATUS REGISTER

$0013

INPUT CAPTURE MSB

$0014

INPUT CAPTURE LSB

$0015

OUTPUT COMPARE MSB

$0016

OUTPUT COMPARE LSB

$0017

TIMER MSB

$0018

TIMER LSB

$0019

ALTERNATE COUNTER MSB

$001A

ALTERNATE COUNTER LSB

$001B

EEPROM PROGRAMMING REGISTER

$001C

A/D CONVERTER DATA REGISTER

$001D

A/D CONVERTER CONTROL & STATUS REGISTER

$001E

RESERVED FOR TEST

$001F

Memory Map

I/O and Control Registers

MC68HC05P18A

Technical Data

MOTOROLA

Memory Map

NON-DISCLOSURE AGREEMENT REQUIRED

Addr.

Register Name

Bit 7

Bit 0

$0000

Port A Data Register

(PORTA)

See page 56.

Read:

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Write:

Reset:

Unaffected by reset

$0001

Port B Data Register

(PORTB)

See page 57.

Read:

PB7

PB6

PB5

Write:

Reset:

Unaffected by reset

$0002

Port C Data Register

(PORTC)

See page 58.

Read:

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

Write:

Reset:

Unaffected by reset

$0003

Port D Data Register

(PORTD)

See page 59.

Read:

PD7

PD5

Write:

Reset:

Unaffected by reset

$0004

Port A Data Direction

(DDRA)

See page 56.

Read:

DDRA7

DDRA6

DDRA5

DDRA4

DDRA3

DDRA2

DDRA1

DDRA0

Write:

Reset:

$0005

Port B Data Direction

(DDRB)

See page 57.

Read:

DDRB7

DDRB6

DDRB5

Write:

Reset:

$0006

Port C Data Direction

(DDRC)

See page 58.

Read:

DDRC7

DDRC6

DDRC5

DDRC4

DDRC3

DDRC2

DDRC1

DDRC0

Write:

Reset:

$0007

Port D Data Direction

(DDRD)

See page 59.

Read:

DDRD5

Write:

Reset:

$0008

Unimplemented

= Unimplemented

= Reserved

U = Unaffected

Figure 2-3. I/O and Control Registers (Sheet 1 of 4)

NON-DISCLOSURE AGREEMENT REQUIRED

Memory Map

Technical Data

MC68HC05P18A

Memory Map

MOTOROLA

$0009

Unimplemented

$000A

SIOP Control Register

(SCR)

See page 80.

Read:

SPE

MSTR

Write:

Reset:

$000B

SIOP Status Register

(SSR)

See page 82.

Read:

SPIF

DCOL

Write:

Reset:

$000C

SIOP Data Register

(SDR)

See page 83.

Read:

SDR7

SDR6

SDR5

SDR4

SDR3

SDR2

SDR1

SDR0

Write:

Reset:

Unaffected by reset

$000D

Reserved

$000E

Unimplemented

$0011

Unimplemented

$0012

Timer Control Register

(TCR)

See page 72.

Read:

ICIE

OCIE

TOIE

IEDG

OLVL

Write:

Reset:

$0013

Timer Status Register

(TSR)

See page 73.

Read:

ICF

OCF

TOF

Write:

Reset:

$0014

Input Capture Register

(ICRH)

See page 70.

Read: ICRH7

ICRH6

ICRH5

ICRH4

ICRH3

ICRH2

ICRH1

ICRH0

Write:

Reset:

Unaffected by reset

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

= Reserved

U = Unaffected

Figure 2-3. I/O and Control Registers (Sheet 2 of 4)

Memory Map

I/O and Control Registers

MC68HC05P18A

Technical Data

MOTOROLA

Memory Map

NON-DISCLOSURE AGREEMENT REQUIRED

$0015

Input Capture Register

(ICRL)

See page 70.

Read:

ICRL7

ICRL6

ICRL5

ICRL4

ICRL3

ICRL2

ICRL1

ICRL0

Write:

Reset:

Unaffected by reset

$0016

Output Compare Register

(OCRH)

See page 68.

Read:

OCRH7

OCRH6

OCRH5

OCRH4

OCRH3

OCRH2

OCRH1

OCRH0

Write:

Reset:

Unaffected by reset

$0017

Output Compare Register

(OCRL)

See page 68.

Read:

OCRL7

OCRL6

OCRL5

OCRL4

OCRL3

OCRL2

OCRL1

OCRL0

Write:

Reset:

Unaffected by reset

$0018

Timer Counter Register

(TMRH)

See page 66.

Read:

TMRH7

TMRH6

TMRH5

TMRH4

TMRH3

TMRH2

TMRH1

TMRH0

Write:

Reset:

$0019

Timer Counter Register

(TMRL)

See page 66.

Read:

TMRL7

TMRL6

TMRL5

TMRL4

TMRL3

TMRL2

TMRL1

TMRL0

Write:

Reset:

$001A

Alternate Counter Register

(ACRH)

See page 66.

Read: ACRH7

ACRH6

ACRH5

ACRH4

ACRH3

ACRH2

ACRH1

ACRH0

Write:

Reset:

$001B

Alternate Counter Register

(ACRL)

See page 66.

Read: ACRL7

ACRL6

ACRL5

ACRL4

ACRL3

ACRL2

ACRL1

ACRL0

Write:

Reset:

$001C

EEPROM Programming

See page 86.

Read:

CPEN

ER1

ER0

LATCH

EERC

EEPGM

Write:

Reset:

$001D

A/D Conversion Value Data

See page 96.

Read:

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Write:

Reset:

Unaffected by reset

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

= Reserved

U = Unaffected

Figure 2-3. I/O and Control Registers (Sheet 3 of 4)

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Memory Map

Technical Data

MC68HC05P18A

Memory Map

MOTOROLA

2.5 RAM

The user RAM consists of 192 bytes (including the stack) at locations
$0050�$010F. The stack begins at address $00FF. The stack pointer
can access 64 bytes of RAM from $00FF to $00C0.

NOTE:

Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.

2.6 ROM

There are 8064 bytes of user ROM available, consisting of:

�

8000 bytes at locations $1FC0�$3EFF

�

48 bytes in page zero locations $0020�$004F

�

16 additional bytes for user vectors at locations $3FF0�$3FFF

NOTE:

Address space $3F00�$3FEF is reserved for test code. Unlike other
M68HC05 devices, the MC68HC05P18A does not contain self-check
code.

$001E

A/D Converter Status and

Control Register (ADSCR)

See page 94.

Read:

ADON

CH2

CH1

CH0

Write:

Reset:

$001F

Reserved

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

= Reserved

U = Unaffected

Figure 2-3. I/O and Control Registers (Sheet 4 of 4)

MC68HC05P18A

Technical Data

MOTOROLA

Central Processor Unit (CPU)

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Technical Data -- MC68HC05P18A

Section 3. Central Processor Unit (CPU)

3.1 Contents

3.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

3.3

CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.3.1

Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.3.2

Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.3.3

Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

3.3.4

Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

3.3.5

Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .37

3.4

Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

3.2 Introduction

This section describes the central processor unit (CPU) registers.

Central Processor Unit (CPU)

CPU Registers

MC68HC05P18A

Technical Data

MOTOROLA

Central Processor Unit (CPU)

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3.3.1 Accumulator

The accumulator (A) is a general-purpose 8-bit register. The CPU uses
the accumulator to hold operands and results of arithmetic and non-
arithmetic operations.

3.3.2 Index Register

In the indexed addressing modes, the CPU uses the byte in the index
register (X) to determine the conditional address of the operand.

The 8-bit index register can also serve as a temporary data storage
location.

3.3.3 Stack Pointer

The stack pointer (SP) is a 16-bit register that contains the address of
the next location on the stack. During a reset or after the reset stack
pointer (RSP) instruction, the stack pointer is preset to $00FF. The
address in the stack pointer decrements as data is pushed onto the
stack and increments as data is pulled from the stack.

Bit 7

Bit 0

Read:

Write:

Reset:

Unaffected by reset

Figure 3-2. Accumulator (A)

Bit 7

Bit 0

Read:

Write:

Reset:

Unaffected by reset

Figure 3-3. Index Register (X)

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Central Processor Unit (CPU)

Technical Data

MC68HC05P18A

Central Processor Unit (CPU)

MOTOROLA

The 10 most significant bits of the stack pointer are permanently fixed at
000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations.
An interrupt uses five locations.

3.3.4 Program Counter

The program counter (PC) is a 16-bit register that contains the address
of the next instruction or operand to be fetched. The two most significant
bits of the program counter are ignored internally and appear as 00.

Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.

Bit
15

Bit

Read:

Write:

Reset:

Figure 3-4. Stack Pointer (SP)

Bit
15

Bit

Read:

Write:

Reset:

Loaded with vectors from $3FF3 and $3FFF

Figure 3-5. Program Counter (PC)

Central Processor Unit (CPU)

CPU Registers

MC68HC05P18A

Technical Data

MOTOROLA

Central Processor Unit (CPU)

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3.3.5 Condition Code Register

The condition code register (CCR) is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed. The following paragraphs describe the
functions of the condition code register.

Half-Carry Flag

The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The half-
carry flag is required for binary coded decimal (BCD) arithmetic
operations.

Interrupt Mask

Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic 0, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is set, the interrupt request is latched. Normally, the CPU processes
the latched interrupt as soon as the interrupt mask is cleared again.

A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After any
reset, the interrupt mask is set and can be cleared only by a software
instruction.

Negative Flag

The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result.

Bit 7

Bit 0

Read:

Write:

Reset:

= Unimplemented

U = Unaffected

Figure 3-6. Condition Code Register (CCR)

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Central Processor Unit (CPU)

Technical Data

MC68HC05P18A

Central Processor Unit (CPU)

MOTOROLA

Zero Flag

The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00.

Carry/Borrow Flag

The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.

3.4 Arithmetic/Logic Unit

The arithmetic/logic unit (ALU) performs the arithmetic and logical
operations defined by the instruction set.

The binary arithmetic circuits decode instructions and set up the ALU for
the selected operation. Most binary arithmetic is based on the addition
algorithm, carrying out subtraction as negative addition. Multiplication is
not performed as a discrete operation but as a chain of addition and shift
operations within the ALU. The multiply instruction (MUL) requires 11
internal clock cycles to complete this chain of operations.

MC68HC05P18A

Technical Data

MOTOROLA

Interrupts

NON-DISCLOSURE AGREEMENT REQUIRED

Technical Data -- MC68HC05P18A

Section 4. Interrupts

4.1 Contents

4.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.3

CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.4

Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

4.4.1

Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .42

4.4.2

Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . .42

4.4.3

Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

4.4.3.1

External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . .43

4.4.3.2

Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .43

4.4.3.3

Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .44

4.4.3.4

Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .44

4.2 Introduction

The MCU can be interrupted six different ways:

1. Non-maskable software interrupt instruction (SWI)

2. External asynchronous interrupt (IRQ)

3. Input capture interrupt (TIMER)

4. Output compare interrupt (TIMER)

5. Timer overflow interrupt (TIMER)

6. Port A interrupt, if selected as a mask option

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Interrupts

Technical Data

MC68HC05P18A

Interrupts

MOTOROLA

4.3 CPU Interrupt Processing

Interrupts cause the processor to save the register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
reset, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is
completed.

When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked (I bit in the
condition code register is clear), and the corresponding interrupt enable
bit is set, the processor proceeds with interrupt processing. Otherwise,
the next instruction is fetched and executed. The SWI is executed the
same as any other instruction, regardless of the I-bit state.

When an interrupt is to be processed, the CPU puts the register contents
on the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$3FF0�$3FFF. If more than one interrupt is pending when the interrupt
vector is fetched, the interrupt with the highest vector location, shown in

Table 4-1

, is serviced first.

A return-from-interrupt (RTI) instruction is used to signify when the
interrupt software service routine is completed. The RTI instruction

Table 4-1. Vector Address for Interrupts and Reset

Register

Flag

Name

Interrupts

CPU

Interrupt

Vector Address

N/A

Reset

RESET

$3FFE�$3FFF

N/A

Software

SWI

$3FFC�$3FFD

N/A

External interrupt

IRQ

$3FFA�$3FFB

TSR

ICF

Timer input capture

TIMER

$3FF8�$3FF9

TSR

OCF

Timer output compare

TIMER

$3FF8�$3FF9

TSR

TOF

Timer overflow

TIMER

$3FF8�$3FF9

N/A

Unimplemented

N/A

$3FF6�$3FF7

N/A

Unimplemented

N/A

$3FF4�$3FF5

N/A

Unimplemented

N/A

$3FF2�$3FF3

N/A

Unimplemented

N/A

$3FF0�$3FF1

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Interrupts

Technical Data

MC68HC05P18A

Interrupts

MOTOROLA

4.4 Interrupt Types

The interrupts fall into these three categories which are discussed here:

�

Reset interrupt sequence

�

Software interrupt (SWI)

�

Hardware interrupts

4.4.1 Reset Interrupt Sequence

The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in

Figure 4-1

. A low-level input

on the RESET pin or internally generated RST signal causes:

�

The program to vector to its starting address, which is specified by
the contents of memory locations $3FFE and $3FFF

�

The I bit in the condition code register (CCR) to be set

�

The MCU to be configured to a known state as described in

Section 5. Resets

4.4.2 Software Interrupt (SWI)

The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction are
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $3FFC and $3FFD.

Interrupts

Interrupt Types

MC68HC05P18A

Technical Data

MOTOROLA

Interrupts

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4.4.3 Hardware Interrupts

All hardware interrupts are maskable by the I bit in the CCR. If the I bit
is set, all hardware interrupts (internal and external) are disabled.
Clearing the I bit enables the hardware interrupts.

The four hardware interrupts are explained here:

�

External interrupt (IRQ)

�

Input capture interrupt

�

Output compare interrupt

�

Timer overflow interrupt

4.4.3.1 External Interrupt (IRQ)

The IRQ pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ. If either the output
from the internal edge detector flip-flop or the level on the IRQ pin is low,
a request is synchronized to the CPU to generate the IRQ interrupt. If the
edge-sensitive only mask option is selected, the output of the internal
edge detector flip-flop is sampled and the input level on the IRQ pin is
ignored. If port A interrupts are selected as a mask option, a port A
interrupt uses the same vector. The interrupt service routine address is
specified by the contents of memory locations $3FFA and $3FFB.

NOTE:

The internal interrupt latch is cleared 9 PH2 clock cycles after the
interrupt is recognized (after location $3FFA is read). Therefore, another
external interrupt pulse could be latched during the IRQ service routine.

When the edge- and level-sensitive mask option is selected, the voltage
applied to the IRQ pin must return to the high state before the return-
from-interrupt (RTI) instruction in the interrupt service routine is
executed.

4.4.3.2 Input Capture Interrupt

The input capture interrupt is generated by the 16-bit timer as described
in

Section 8. 16-Bit Timer

. The input capture interrupt flag is located in

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Interrupts

Technical Data

MC68HC05P18A

Interrupts

MOTOROLA

the timer status register (TSR) and its corresponding enable bit can be
found in the timer control register (TCR).

The I bit in the CCR must be clear in order for the input capture interrupt
to be enabled. The interrupt service routine address is specified by the
contents of memory locations $3FF8 and $3FF9.

4.4.3.3 Output Compare Interrupt

The output compare interrupt is generated by the 16-bit timer as
described in

Section 8. 16-Bit Timer

. The output compare interrupt flag

is located in register TSR and its corresponding enable bit can be found
in register TCR.

The I bit in the CCR must be clear in order for the output compare
interrupt to be enabled. The interrupt service routine address is specified
by the contents of memory locations $3FF8 and $3FF9.

4.4.3.4 Timer Overflow Interrupt

The timer overflow interrupt is generated by the 16-bit timer as described
in

Section 8. 16-Bit Timer

. The timer overflow interrupt flag is located in

The I bit in the CCR must be clear in order for the timer overflow interrupt
to be enabled. This internal interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
locations $3FF8 and $3FF9.

MC68HC05P18A

Technical Data

MOTOROLA

Resets

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Technical Data -- MC68HC05P18A

Section 5. Resets

5.1 Contents

5.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

5.3

External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

5.4

Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

5.4.1

Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

5.4.2

Computer Operating Properly (COP) Reset . . . . . . . . . . . . .47

5.4.3

Low-Voltage Reset (LVR). . . . . . . . . . . . . . . . . . . . . . . . . . .48

5.2 Introduction

The MCU can be reset from four sources:

�

One external input

�

Three internal reset conditions

The RESET pin is an input with a Schmitt trigger as shown in

Figure 5-1

. The CPU and all peripheral modules are reset by the internal

reset signal (RST), which is the logical OR of internal reset functions and
is clocked by PH2.

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Resets

Technical Data

MC68HC05P18A

Resets

MOTOROLA

Figure 5-1. Reset Block Diagram

5.3 External Reset (RESET)

The RESET input is the only external reset and is connected to an
internal Schmitt trigger. The external reset occurs whenever the RESET
input is driven below the lower threshold and remains in reset until the
RESET pin rises above the upper threshold. The upper and lower
thresholds are given in

Section 13. Electrical Specifications

5.4 Internal Resets

The three internally generated resets are:

�

Initial power-on reset (POR)

�

Computer operating properly (COP) watchdog timer

�

Low-voltage reset (LVR)

CPU

LATCH

RESET

COP WATCHDOG

(COPR)

RST

OSC

DATA

ADDRESS

PH2

TO OTHER

PERIPHERALS

LOW-VOLTAGE

RESET (LVR)

TO IRQ

LOGIC

POWER-ON RESET

(POR)

PH2

CLOCKED

ONE-SHOT

PULSE WIDTH = 4 X E-CLK

IRQ

Resets

Internal Resets

MC68HC05P18A

Technical Data

MOTOROLA

Resets

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5.4.1 Power-On Reset (POR)

The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
PH2 clock cycle oscillator stabilization delay after the oscillator becomes
active.

The POR generates the RST signal and resets the MCU. At the same
time, the POR pulls the RESET pin low allowing external devices to be
reset with the MCU. If any other reset function is active at the end of this
4064 PH2 clock cycle delay, the RST signal remains active until the
other reset condition(s) end.

5.4.2 Computer Operating Properly (COP) Reset

When the COP watchdog timer is enabled by mask option, the internal
COP reset is generated automatically by a timeout of the COP watchdog
timer. This timer is implemented with an 18-stage ripple counter that
provides a timeout period of 65.5 ms when a 4-MHz oscillator is used.
The COP watchdog counter is cleared by writing a logical 0 to bit 0 at
location $3FF0.

The COP register is shared with the most-significant bit (MSB) of an
unimplemented user interrupt vector, as shown in

Figure 5-2

. Reading

this location returns the MSB of the unimplemented user interrupt vector.
Writing to this location clears the COP watchdog timer.

Address:

$3FF0

Bit 7

Bit 0

Read:

Write:

COPR

Reset:

Unaffected by reset

= Reserved

= Unimplemented

Figure 5-2. COP Register (COPR)

MC68HC05P18A

Technical Data

MOTOROLA

Operating Modes

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Technical Data -- MC68HC05P18A

Section 6. Operating Modes

6.1 Contents

6.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

6.3

User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

6.4

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

6.4.1

STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

6.4.1.1

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

6.4.1.2

Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

6.4.2

WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

6.5

COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .54

6.2 Introduction

The MC68HC05P18A has one user mode of operation and several low-
power modes which are described in this section.

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Operating Modes

Technical Data

MC68HC05P18A

Operating Modes

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6.3 User Mode

The user mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU and is not
available externally. User mode is entered on the rising edge of RESET
if the IRQ pin is within the normal operating voltage range.

In the user mode, there is:

�

An 8-bit input/output (I/O) port

�

A second 8-bit I/O port shared with the analog-to-digital (A/D)
subsystem

�

One 3-bit I/O port shared with the serial input/output port (SIOP)

�

One 2-bit I/O port shared with the 16-bit timer subsystem

6.4 Low-Power Modes

The MC68HC05P18A is capable of running in a low-power mode in each
of its configurations. The WAIT and STOP instructions provide three
modes that reduce the power required for the MCU by stopping various
internal clocks and/or the on-chip oscillator. The STOP and WAIT
instructions are not normally used if the computer operating properly
(COP) watchdog timer is enabled. The stop conversion mask option is
used to modify the behavior of the STOP instruction from stop mode to
halt mode. The flow of the stop, halt, and wait modes is shown in

Figure 6-1

Operating Modes

Low-Power Modes

MC68HC05P18A

Technical Data

MOTOROLA

Operating Modes

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Figure 6-1. Stop, Halt, and Wait Modes Flowchart

FETCH RESET VECTOR
OR

SERVICE INTERRUPT
A.

STACK

SET I BIT

VECTOR TO INTERRUPT ROUTINE

WAIT

STOP

TO HALT MASK

OPTION?

OR EXTERNAL

RESET

IRQ

EXTERNAL

INTERRUPT?

STOP EXTERNAL OSCILLATOR

STOP INTERNAL TIMER CLOCK

RESET STARTUP DELAY

RESTART EXTERNAL

OSCILLATOR

START STABILIZATION DELAY

END

OF STABILIZATION

DELAY?

IRQ

EXTERNAL

INTERRUPT?

EXTERNAL OSCILLATOR ACTIVE

AND

INTERNAL TIMER CLOCK ACTIVE

RESTART INTERNAL

PROCESSOR CLOCK

STOP INTERNAL

PROCESSOR CLOCK

CLEAR I BIT IN CCR

TIMER

INTERNAL

INTERRUPT?

OR EXTERNAL

RESET?

STOP

HALT

OR EXTERNAL

RESET?

IRQ

EXTERNAL

INTERRUPT?

EXTERNAL OSCILLATOR ACTIVE

AND

INTERNAL TIMER CLOCK ACTIVE

TIMER

INTERNAL

INTERRUPT?

COP

INTERNAL

RESET?

COP

INTERNAL

RESET?

STOP RC OSCILLATOR

LVR

STOP INTERNAL

PROCESSOR CLOCK

CLEAR I BIT IN CCR

STOP RC OSCILLATOR

STOP INTERNAL

PROCESSOR CLOCK

CLEAR I BIT IN CCR

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MC68HC05P18A

Operating Modes

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6.4.1 STOP Instruction

The STOP instruction can result in one of two modes of operation,
depending on the mask option.

1. If the stop conversion to halt mask option is not chosen, the STOP

instruction behaves like a normal STOP instruction in the
M68HC05 Family and places the MCU in stop mode.

2. If the stop conversion to halt mask option is chosen, the STOP

instruction behaves like a WAIT instruction (with the exception of
a brief delay at startup) and places the MCU in halt mode.

6.4.1.1 Stop Mode

Execution of the STOP instruction without conversion to halt places the
MCU in its lowest power consumption mode. In stop mode, the internal
oscillator is turned off, halting all internal processing, including the COP
watchdog timer. The RC oscillator that feeds the electrically erasable
programmable read-only memory (EEPROM) and the A/D converter is
also stopped. Execution of the STOP instruction automatically clears the
I bit in the condition code register so that the IRQ external interrupt is
enabled. All other registers and memory remain unaltered. All
input/output lines remain unchanged.

The MCU can be brought out of the stop mode only by:

�

An IRQ external interrupt

�

Port A external interrupt, if selected as a mask option

�

An externally generated reset

When exiting stop mode, the internal oscillator resumes after a 4064
PH2 clock cycle oscillator stabilization delay.

NOTE:

Execution of the STOP instruction without conversion to halt (via mask
option) causes the oscillator to stop, and therefore disable the COP
watchdog timer. If the COP watchdog timer is to be used, stop mode
should be changed to halt mode by selecting the appropriate mask
option.

Operating Modes

Low-Power Modes

MC68HC05P18A

Technical Data

MOTOROLA

Operating Modes

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6.4.1.2 Halt Mode

Execution of the STOP instruction with the conversion to halt places the
MCU in this low-power mode. Halt mode consumes the same amount of
power as wait mode.

NOTE:

Both halt and wait modes consume more power than stop mode.

In halt mode the PH2 clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register,
enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.

If the 16-bit timer interrupt is enabled, it causes the processor to exit halt
mode and resume normal operation. Halt mode also can be exited when
an IRQ external interrupt or external RESET occurs. When exiting halt
mode, the PH2 clock resumes after a delay of one to 4064 PH2 clock
cycles. This varied delay time is the result of the halt mode exit circuitry
testing the oscillator stabilization delay timer (a feature of stop mode)
which has been free-running (a feature of wait mode).

NOTE:

Halt mode is not intended for normal use. This feature is provided to
keep the COP watchdog timer active in the event a STOP instruction is
inadvertently executed.

6.4.2 WAIT Instruction

The WAIT instruction places the MCU in a low-power mode, which
consumes more power than stop mode. In wait mode, the PH2 clock is
halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-
bit timer and reset to be generated from the COP watchdog timer.
Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other
registers, memory, and input/output lines remain in their previous state.

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Operating Modes

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If the 16-bit timer interrupt is enabled, it causes the processor to exit wait
mode and resume normal operation. The 16-bit timer may be used to
generate a periodic exit from wait mode. Wait mode may also be exited
when an IRQ or RESET occurs.

NOTE:

If port A interrupts are selected as a mask option, the processor also will
exit wait mode.

6.5 COP Watchdog Timer Considerations

The COP watchdog timer is active in the user mode of operation when
selected by mask option. Executing the STOP instruction without
conversion to halt via mask option causes the COP to be disabled.
Therefore, it is recommended that the STOP instruction be modified to
produce halt mode via mask option if the COP watchdog timer is
enabled.

Furthermore, it is recommended that the COP watchdog timer be
disabled for applications that use the halt or wait mode for time periods
that exceed the COP timeout period.

COP watchdog timer interactions are summarized in

Table 6-1

Table 6-1. COP Watchdog Timer Recommendations

IF These Conditions Exist:

THEN the COP Watchdog

Timer Should:

STOP Instruction

WAIT Time

Halt mode selected

via mask option

WAIT time less than

COP timeout

Enable or disable COP

via mask option

Halt mode selected

via mask option

WAIT time MORE than

COP timeout

Disable COP

via mask option

Stop mode selected

via mask option

Any length WAIT time

Disable COP

via mask option

MC68HC05P18A

Technical Data

MOTOROLA

Input/Output (I/O) Ports

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Technical Data -- MC68HC05P18A

Section 7. Input/Output (I/O) Ports

7.1 Contents

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

7.3

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

7.4

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

7.5

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

7.6

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

7.7

I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7.2 Introduction

In user mode, 20 bidirectional input/output (I/O) lines are arranged as:

�

Two 8-bit I/O ports, port A and port C

�

One 3-bit I/O port, port B

�

One 1-bit I/O port, port D

These ports are programmable as either inputs or outputs under
software control of the data direction registers (DDRs). There is also an
input-only pin associated with port D.

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Input/Output (I/O) Ports

Technical Data

MC68HC05P18A

Input/Output (I/O) Ports

MOTOROLA

7.3 Port A

Port A is an 8-bit bidirectional port which can share its pins with the IRQ
interrupt system, as shown in

Figure 7-1

. Each port A pin is controlled

by the corresponding bits in a data direction register and a data register.
The port a data register is located at address $0000. The port A data
direction register (DDRA) is located at address $0004. Reset clears the
DDRA thereby initializing port A as an input port. The port A data register
is unaffected by reset.

Figure 7-1. Port A I/O Circuitry

100

�

PULLUP

READ $0000

WRITE $0000

READ $0004

DATA

TO IRQ

INTERRUPT

SYSTEM

I/O

OUTPUT

MASK OPTION

(PULLUP INHIBIT)

INTERNAL HC05

DATA BUS

RESET

(RST)

WRITE $0004

DATA DIRECTION

Input/Output (I/O) Ports

Port B

MC68HC05P18A

Technical Data

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Input/Output (I/O) Ports

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7.4 Port B

Port B is a 3-bit bidirectional port that can share pins PB5璓B7 with the
serial input/output port (SIOP) communications subsystem. The port B
data register is located at address $0001 and its data direction register
(DDR) is located at address $0005. Reset does not affect the data
registers, but clears the DDRs, thereby setting all of the port pins to input
mode. Writing a 1 to a DDR bit sets the corresponding port pin to output
mode (see

Figure 7-2

Port B may be used for general I/O applications when the SIOP
subsystem is disabled. The SPE bit in register SIOP control register
(SPCR) is used to enable/disable the SIOP subsystem. When the SIOP
subsystem is enabled, port B registers are still accessible to software.
Writing to either of the port B registers while a data transfer is under way
could corrupt the data. See

Section 9. Serial Input/Output Ports

(SIOP)

for a discussion of the SIOP subsystem.

Figure 7-2. Port B I/O Circuitry

READ $0001

WRITE $0001

READ $0005

DATA

I/O

OUTPUT

INTERNAL HC05

DATA BUS

RESET

(RST)

WRITE $0005

DATA DIRECTION

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Input/Output (I/O) Ports

Technical Data

MC68HC05P18A

Input/Output (I/O) Ports

MOTOROLA

7.5 Port C

Port C is an 8-bit bidirectional port that can share pins PC3璓C7 with the
analog-to-digital (A/D) converter subsystem. The port C data register is
located at address $0002 and its data direction register (DDR) is located
at address $0006. Reset does not affect the data registers, but clears the
DDRs, thereby setting all of the port pins to input mode. Writing a 1 to a
DDR bit sets the corresponding port pin to output mode (see

Figure 7-3

). Two port C pins, PC0 and PC1, can source and sink a

higher current than a typical I/O pin. See

Section 13. Electrical

Specifications

regarding current specifications.

Port C may be used for general I/O applications when the A/D
subsystem is disabled. The ADON bit in the A/D status and control
register (ADSC) is used to enable/disable the A/D subsystem.

CAUTION:

Care must be exercised when using pins PC0璓C2 while the A/D
subsystem is enabled. Accidental changes to bits that affect pins
PC3璓C7 in the data or DDR registers will produce unpredictable results
in the A/D subsystem.

See

Section 11. Analog-to-Digital (A/D) Converter

Figure 7-3. Port C I/O Circuitry

READ $0002

WRITE $0002

READ $0006

DATA

I/O

OUTPUT

INTERNAL HC05

DATA BUS

RESET

(RST)

WRITE $0006

DATA DIRECTION

HIGH CURRENT

CAPABILITY, PC0

AND PC1 ONLY

Input/Output (I/O) Ports

Port D

MC68HC05P18A

Technical Data

MOTOROLA

Input/Output (I/O) Ports

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7.6 Port D

Port D is a 2-bit port with:

�

One bidirectional pin, PD5/CKOUT

�

One input-only pin, PD7

Pin PD7 is shared with the 16-bit timer. There is a mask option to have
PD5 replaced with the clock output. The port D data register is located
at address $0003 and its data direction register (DDR) is located at
address $0007. Reset does not affect the data registers, but clears the
DDRs, thereby setting PD5/CKOUT to input mode. Writing a 1 to DDR
bit 5 sets PD5/CKOUT to output mode (see

Figure 7-4

Port D may be used for general I/O applications regardless of the state
of the 16-bit timer. Since PD7 is an input-only line, its state can be read
from the port D data register at any time.

Figure 7-4. Port D I/O Circuitry

READ $0003

WRITE $0003

READ $0007

DATA

I/O

OUTPUT

INTERNAL HC05

DATA BUS

RESET

(RST)

WRITE $0007

DATA DIRECTION

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Input/Output (I/O) Ports

Technical Data

MC68HC05P18A

Input/Output (I/O) Ports

MOTOROLA

7.7 I/O Port Programming

Each pin on ports A through port D, with the exception of pin 7 of port D,
may be programmed as an input or an output under software control as
shown in

Table 7-1

Table 7-2

Table 7-3

, and

Table 7-4

The direction of a pin is determined by the state of its corresponding bit
in the associated port data direction register (DDR). A pin is configured
as an output if its corresponding DDR bit is set to a logic 1. A pin is
configured as an input if its corresponding DDR bit is cleared to a logic 0.

Table 7-1. Port A I/O Pin Functions

DDRA

I/O Pin Mode

Access

to DDRA @ $0004

Access

to Data Register @ $0000

Read/Write

Read

Write

In, Hi-Z

DDRA0璂DRA7

I/O pin

See note

Out

DDRA0璂DRA7

PA0璓A7

Note: Does not affect input, but stored to data register

Table 7-2. Port B I/O Pin Functions

DDRB

I/O Pin Mode

Access

to DDRB @ $0005

Access

to Data Register @ $0001

Read/Write

Read

Write

In, Hi-Z

DDRB5璂DRB7

I/O pin

See note

Out

DDRB5璂DRB7

PB5璓B7

Note: Does not affect input, but stored to data register

Table 7-3. Port C I/O Pin Functions

DDRC

I/O Pin Mode

Access

to DDRC @ $0006

Access

to Data Register @ $0002

Read/Write

Read

Write

In, Hi-Z

DDRC0璂DRC7

I/O pin

See note

Out

DDRC0璂DRC7

PC0璓C7

Note: Does not affect input, but stored to data register

MC68HC05P18A

Technical Data

MOTOROLA

16-Bit Timer

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Technical Data -- MC68HC05P18A

Section 8. 16-Bit Timer

8.1 Contents

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

8.3

Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

8.4

Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

8.5

Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

8.6

Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

8.7

Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

8.8

Timer Operation during Wait Mode and Halt Mode . . . . . . . . .74

8.9

Timer Operating during Stop Mode . . . . . . . . . . . . . . . . . . . . .74

8.2 Introduction

The MC68HC05P18A MCU contains a single 16-bit programmable timer
with an input capture function and an output compare function. The 16-
bit timer is driven by the output of a fixed divide-by-four prescaler
operating from the PH2 clock. The 16-bit timer may be used for many
applications, including input waveform measurement while
simultaneously generating an output waveform. Pulse widths can vary
from microseconds to seconds depending on the oscillator frequency
selected. The 16-bit timer is also capable of generating periodic
interrupts. See

Figure 8-1

16-Bit Timer

Timer

MC68HC05P18A

Technical Data

MOTOROLA

16-Bit Timer

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Because the timer has a 16-bit architecture, each function is represented
by two registers. Each register pair contains the high and low byte of that
function. Generally, accessing the low byte of a specific timer function
allows full control of that function; however, an access of the high byte
inhibits that specific timer function until the low byte is also accessed.

NOTE:

The I bit in the condition code register (CCR) should be set while
manipulating both the high and low byte registers of a specific timer
function. This prevents interrupts from occurring between the time that
the high and low bytes are accessed.

8.3 Timer

The key element of the programmable timer is a 16-bit free-running
counter, or timer registers, preceded by a prescaler, which divides the
PH2 clock by four. The prescaler gives the timer a resolution of 2.0 ms
when a 4-MHz crystal is used. The counter is incremented to increasing
values during the low portion of the PH2 clock cycle.

The double byte free-running counter can be read from either of two
locations:

�

The timer registers, TMRH and TMRL

�

The alternate counter registers, ACRH and ACRL

Both locations will contain identical values. A read sequence containing
only a read of the least-significant bit (LSB) of the counter (TMRL/ACRL)
returns the count value at the time of the read. If a read of the counter
accesses the most-significant bit (MSB) first (TMRH/ACRH), it causes
the LSB (TMRL/ACRL) to be transferred to a buffer. This buffer value
remains fixed after the first MSB byte read even if the MSB is read
several times. The buffer is accessed when reading the counter LSB
(TMRL/ACRL), and thus completes a read sequence of the total counter
value. When reading either the timer or alternate counter registers, if the
MSB is read, the LSB must also be read to complete the read sequence.
See

Figure 8-2

and

Figure 8-3

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16-Bit Timer

Technical Data

MC68HC05P18A

16-Bit Timer

MOTOROLA

The timer registers and alternate counter registers can be read at any
time without affecting their values. However, the alternate counter
registers differ from the timer registers in one respect: A read of the timer
register MSB can clear the timer overflow flag (TOF). Therefore, the
alternate counter registers can be read at any time without the possibility

Address:

$0018

Bit 7

Bit 0

Read:

TMRH7

TMRH6

TMRH5

TMRH4

TMRH3

TMRH2

TMRH1

TMRH0

Write:

Reset:

Address:

$0019

Bit 7

Bit 0

Read:

TMRL7

TMRL6

TMRL5

TMRL4

TMRL3

TMRL2

TMRL1

TMRL0

Write:

Reset:

= Unimplemented

Figure 8-2. Timer Counter Registers (TMRH/TMRL)

Address:

$001A

Bit 7

Bit 0

Read:

ACRH7

ACRH6

ACRH5

ACRH4

ACRH3

ACRH2

ACRH1

ACRH0

Write:

Reset:

Address:

$001B

Bit 7

Bit 0

Read:

ACRL7

ACRL6

ACRL5

ACRL4

ACRL3

ACRL2

ACRL1

ACRL0

Write:

Reset:

= Unimplemented

Figure 8-3. Alternate Counter Registers (ACRH/ACRL)

16-Bit Timer

Timer

MC68HC05P18A

Technical Data

MOTOROLA

16-Bit Timer

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of missing timer overflow interrupts due to clearing of the TOF. See

Figure 8-4

The free-running counter is initialized to $FFFC during reset and is a
read-only register. During power-on reset (POR), the counter is
initialized to $FFFC and begins counting after the oscillator startup
delay. Since the counter is 16 bits preceded by a fixed divide-by-four
prescaler, the value in the counter repeats every 262,144 PH2 clock
cycles (524,288 oscillator cycles). When the free-running counter rolls
over from $FFFF to $0000, the timer overflow flag bit (TOF) in the timer
status register (TSR) is set. An interrupt can also be enabled when
counter rollover occurs by setting the timer overflow interrupt enable bit
(TOIE) in the timer control register (TCR). See

Figure 8-5

Figure 8-4. State Timing Diagram for Timer Overflow

Figure 8-5. State Timing Diagram for Timer Reset

$FFFE

$FFFF

$0000

$0001

$0002

16-BIT FREE-RUNNING

COUNTER

TIMER OVERFLOW

FLAG (TOF)

PH2 CLOCK

Note: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer

status register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register
pair (TCRL).

Note: The counter and control registers are the only 16-bit timer registers affected by reset.

PH2 CLOCK

INTERNAL RESET

16-BIT FREE-RUNNING

COUNTER

RESET

(EXTERNAL OR OTHER)

$FFFC

$FFFD

$FFFE

$FFFF

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16-Bit Timer

Technical Data

MC68HC05P18A

16-Bit Timer

MOTOROLA

8.4 Output Compare

The output compare function may be used to generate an output
waveform and/or as an elapsed time indicator. All of the bits in the output
compare register pair, OCRH/OCRL, are readable and writable and are
not altered by the 16-bit timer's control logic. Reset does not affect the
contents of these registers. If the output compare function is not utilized,
its registers may be used for data storage. See

Figure 8-6

The contents of the output compare registers are compared with the
contents of the free-running counter once every four PH2 clock cycles.
If a match is found, the output compare flag bit (OCF) is set and the
output level bit (OLVL) is clocked to the output latch. The values in the
output compare registers and output level bit should be changed after
each successful comparison to control an output waveform or to
establish a new elapsed timeout. An interrupt can also accompany a
successful output compare if the output compare interrupt enable bit
(OCIE) is set.

After a CPU write cycle to the MSB of the output compare register pair
(OCRH), the output compare function is inhibited until the LSB (OCRL)
is written. Both bytes must be written if the MSB is written. A write made
only to the LSB will not inhibit the compare function. The free-running

Address:

$0016

Bit 7

Bit 0

Read:

OCRH7

OCRH6

OCRH5

OCRH4

OCRH3

OCRH2

OCRH1

OCRH0

Write:

Reset:

Unaffected by reset

Address:

$0017

Bit 7

Bit 0

Read:

OCRL7

OCRL6

OCRL5

OCRL4

OCRL3

OCRL2

OCRL1

OCRL0

Write:

Reset:

Unaffected by reset

Figure 8-6. Output Compare Registers (OCRH/OCRL)

16-Bit Timer

Output Compare

MC68HC05P18A

Technical Data

MOTOROLA

16-Bit Timer

NON-DISCLOSURE AGREEMENT REQUIRED

counter increments every four PH2 clock cycles. The minimum time
required to update the output compare registers is a function of software
rather than hardware.

The output compare output level bit (OLVL) will be clocked to its output
latch regardless of the state of the output compare flag bit (OCF). A valid
output compare must occur before the OLVL bit is clocked to its output
latch (TCMP).

Since neither the output compare flag (OCF) nor the output compare
registers are affected by reset, care must be exercised when initializing
the output compare function. This procedure is recommended:

1. Block interrupts by setting the I bit in the condition code register

(CCR).

2. Write the MSB of the output compare register pair (OCRH) to

inhibit further compares until the LSB is written.

3. Read the timer status register (TSR) to arm the output compare

flag (OCF).

4. Write the LSB of the output compare register pair (OCRL) to

enable the output compare function and to clear its flag and
interrupt.

5. Unblock interrupts by clearing the I bit in the CCR.

This procedure prevents the output compare flag bit (OCF) from being
set between the time it is read and the time the output compare registers
are updated. A software example is shown in

Figure 8-7

�

B7
B6

�

�
�

XX
XX

16
13
17

�

SEI

�
�

LDA
LDX

STA

LDA
STX

�

�
�

DATAH

DATAL
OCRH

TSR

OCRL

�

BLOCK INTERRUPTS
�
�
HI BYTE FOR COMPARE
LOW BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COMPARE
�

Figure 8-7. Output Compare Software Initialization Example

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16-Bit Timer

Technical Data

MC68HC05P18A

16-Bit Timer

MOTOROLA

8.5 Input Capture

Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input
capture. They are used to latch the value of the free-running counter
after a defined transition is sensed by the input capture edge detector.

NOTE:

The input capture edge detector contains a Schmitt trigger to improve
noise immunity.

The edge that triggers the counter transfer is defined by the input edge
bit (IEDG) in TCR. Reset does not affect the contents of the input
capture registers. See

Figure 8-8

The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the PH2 clock preceding
the external transition (see

Figure 8-9

). This delay is required for internal

synchronization. Resolution is affected by the prescaler, allowing the
free-running counter to increment once every four PH2 clock cycles.

The contents of the free-running counter are transferred to the input
capture registers on each proper signal transition regardless of the state
of the input capture flag bit (ICF) in register TSR. The input capture
registers always contain the free-running counter value which
corresponds to the most recent input capture.

Address:

$0014

Bit 7

Bit 0

Read:

ICRH7

ICRH6

ICRH5

ICRH4

ICRH3

ICRH2

ICRH1

ICRH0

Write:

Reset:

Unaffected by reset

Address:

$0015

Bit 7

Bit 0

Read:

ICRL7

ICRL6

ICRL5

ICRL4

ICRL3

ICRL2

ICRL1

ICRL0

Write:

Reset:

Unaffected by reset

Figure 8-8. Input Capture Registers (ICRH/ICRL)

16-Bit Timer

Input Capture

MC68HC05P18A

Technical Data

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16-Bit Timer

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After a read of the MSB of the input capture register pair (ICRH), counter
transfers are inhibited until the LSB of the register pair (ICRL) is also
read. This characteristic forces the minimum pulse period attainable to
be determined by the time required to execute an input capture software
routine in an application.

Reading the LSB of the input capture register pair (ICRL) does not inhibit
transfer of the free-running counter. Again, minimum pulse periods are
ones which allow software to read the LSB of the register pair (ICRL) and
perform needed operations. There is no conflict between reading the
LSB (ICRL) and the free-running counter transfer since they occur on
opposite edges of the PH2 clock.

Figure 8-9. State Timing Diagram for Input Capture

INPUT CAPTURE

FLAG

INPUT CAPTURE

16-BIT FREE-RUNNING

COUNTER

TCAP PIN

INPUT CAPTURE

LATCH

PH2 CLOCK

Note: If the input edge occurs in the shaded area from one T10 timer state to the other T10 timer state, the input capture

flag is set during the next T11 timer state.

$FFEC

$FFED

$FFEE

$FFEF

$FFEB

$FFED

(SEE NOTE)

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16-Bit Timer

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8.6 Timer Control Register

The timer control (TCR) shown in

Figure 8-10

and free-running counter

(TMRH, TMRL, ACRH, ACRL) registers are the only registers of the 16-
bit timer affected by reset. The output compare port (TCMP) is forced
low after reset and remains low until OLVL is set and a valid output
compare occurs.

ICIE -- Input Capture Interrupt Enable Bit

Bit 7, when set, enables input capture interrupts to the CPU. The
interrupt will occur at the same time bit 7 (ICF) in the TSR register is
set.

OCIE -- Output Comapre Interrupt Enable Bit

Bit 6, when set, enables output compare interrupts to the CPU. The
interrupt will occur at the same time bit 6 (OCF) in the TSR register is
set.

TOIE -- Timer Overflow Interrupt Enable Bit

Bit 5, when set, enables timer overflow (rollover) interrupts to the
CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR
register is set.

IEDG -- Input Capture Edge Select Bit

Bit 1 selects which edge of the input capture signal will trigger a
transfer of the contents of the free-running counter registers to the
input capture registers. Clearing this bit will select the falling edge,
setting it selects the rising edge.

Address:

$0012

Bit 7

Bit 0

Read:

ICIE

OCIE

TOIE

IEDG

OLVL

Write:

Reset:

= Unimplemented

U = Unaffected

Figure 8-10. Timer Control Register (TCR)

16-Bit Timer

Timer Status Register

MC68HC05P18A

Technical Data

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16-Bit Timer

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OLVL -- Output Compare Output Level Select Bit

Bit 0 selects the output level (high or low) that is clocked into the
output compare output latch at the next successful output compare.

8.7 Timer Status Register

Reading the timer status register (TSR) satisfies the first condition
required to clear status flags and interrupts (see

Figure 8-11

). The only

remaining step is to read (or write) the register associated with the active
status flag (and/or interrupt). This method does not present any
problems for input capture or output compare functions.

However, a problem can occur when using a timer interrupt function and
reading the free-running counter at random times to, for example,
measure an elapsed time. If the proper precautions are not designed into
the application software, a timer interrupt flag (TOF) could
unintentionally be cleared if:

1. The TSR is read when bit 5 (TOF) is set.

2. The LSB of the free-running counter is read, but not for the

purpose of servicing the flag or interrupt.

The alternate counter registers (ACRH and ACRL) contain the same
values as the timer registers (TMRH and TMRL). Registers ACRH and
ACRL can be read at any time without affecting the timer overflow flag
(TOF) or interrupt.

Address:

$0013

Bit 7

Bit 0

Read:

ICF

OCF

TOF

Write:

Reset:

= Unimplemented

U = Unaffected

Figure 8-11. Timer Status Register (TSR)

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16-Bit Timer

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16-Bit Timer

MOTOROLA

ICF -- Input Capture Flag

Bit 7 is set when the edge specified by IEDG in register TCR has been
sensed by the input capture edge detector fed by pin TCAP. This flag,
and the input capture interrupt, can be cleared by reading register
TSR followed by reading the LSB of the input capture register pair
(ICRL).

OCF -- Output Compare Bit

Bit 6 is set when the contents of the output compare registers match
the contents of the free-running counter. This flag, and the output
compare interrupt, can be cleared by reading register TSR followed
by writing the LSB of the output compare register pair (OCRL).

TOF -- Timer Overflow Flag

Bit 5 is set by a rollover of the free-running counter from $FFFF to
$0000. This flag, and the timer overflow interrupt, can be cleared by
reading register TSR followed by reading the LSB of the timer register
pair (TMRL).

8.8 Timer Operation during Wait Mode and Halt Mode

During wait mode and halt mode the 16-bit timer continues to operate
normally and may generate an interrupt to trigger the MCU out of the wait
mode and halt mode.

8.9 Timer Operating during Stop Mode

When the MCU enters the stop mode, the free-running counter stops
counting. (The PH2 clock is stopped.) It remains at that particular count
value until the stop mode is exited by applying a low signal to the IRQ
pin, at which time the counter resumes from its stopped value as if
nothing had happened. If stop mode is exited via an external RESET
(logic low applied to the RESET pin), the counter is forced to $FFFC.

If a valid input capture edge occurs at the TCAP pin during stop mode,
the input capture detect circuitry is armed. This action does not set any
flags or wake up the MCU, but when the MCU does wake up there will

MC68HC05P18A

Technical Data

MOTOROLA

Serial Input/Output Ports (SIOP)

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Technical Data -- MC68HC05P18A

Section 9. Serial Input/Output Ports (SIOP)

9.1 Contents

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

9.3

SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

9.3.1

Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

9.3.2

Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

9.3.3

Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . .79

9.4

SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

9.4.1

SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

9.4.2

SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

9.4.3

SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

9.2 Introduction

The simple synchronous serial input/output (I/O) port (SIOP) subsystem
is designed to provide efficient serial communications between
peripheral devices or other MCUs. The SIOP is implemented as a 3-wire
master/slave system with:

�

Serial clock (SCK)

�

Serial data input (SDI)

�

Serial data output (SDO)

A block diagram of the SIOP is shown in

Figure 9-1

The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled, SPE bit set in the SIOP control register (SCR), port B
data direction register (DDR), and data register are modified by the
SIOP. Although port B DDR and data registers can be altered by

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Serial Input/Output Ports (SIOP)

Technical Data

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Serial Input/Output Ports (SIOP)

MOTOROLA

application software, these actions could affect the transmitted or
received data.

Figure 9-1. SIOP Block Diagram

9.3 SIOP Signal Format

The SIOP subsystem is software configurable for master or slave
operation. There are no external mode selection inputs available (for
example, slave select pin).

9.3.1 Serial Clock (SCK)

The state of the SCK output normally remains a logic 1 during idle
periods between data transfers. The first falling edge of SCK signals the
beginning of a data transfer. At this time the first bit of received data is
accepted at the SDI pin and the first bit of transmitted data is presented
at the SDO pin (see

Figure 9-2

). Data is captured at the SDI pin on the

rising edge of SCK, and the first bit of transmitted data is presented at
the SDO pin. The transfer is terminated upon the eighth rising edge of
SCK.

8-BIT

SHIFT

STATUS

BAUD

RATE

CONTROL

GENERATOR

HCO5 INTERNAL BUS

PH2 CLOCK

SCK

SDI

SDO

7 6 5 4 3 2 1 0

I/O

$0B

$0C

$0A

CONTROL

LOGIC

SPE

SDI/PB6

SCK/PB7

SDO/PB5

Serial Input/Output Ports (SIOP)

SIOP Signal Format

MC68HC05P18A

Technical Data

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Serial Input/Output Ports (SIOP)

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Figure 9-2. SIOP Timing Diagram

The master and slave modes of operation differ only by the sourcing of
SCK. In master mode, SCK is driven from an internal source within the
MCU. In slave mode, SCK is driven from a source external to the MCU.
The SCK frequency is mask option selectable. Available rates are OSC
divided by 2, 4, 8, or 16.

NOTE:

OSC divided by 2 is four times faster than the standard rate available on
the 68HC05P6.

Refer to

1.4 Mask Options

for a description of available mask options.

9.3.2 Serial Data Input (SDI)

The SDI pin becomes an input as soon as the SIOP subsystem is
enabled. New data is presented to the SDI pin on the falling edge of
SCK. Valid data must be present at least 100 ns before the rising edge
of SCK and remain valid for 100 ns after the rising edge of SCK. See

Figure 9-2

9.3.3 Serial Data Output (SDO)

The SDO pin becomes an output as soon as the SIOP subsystem is
enabled. Prior to enabling the SIOP, PB5 can be initialized to determine
the beginning state. While the SIOP is enabled, PB5 cannot be used as
a standard output since that pin is connected to the last stage of the
SIOP serial shift register. A mask option is included to allow the data to

SCK

SDO

SDI

100 ns

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

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Serial Input/Output Ports (SIOP)

MOTOROLA

be transmitted in either most-significant bit (MSB) first format or the
least-significant bit (LSB) format.

On the first falling edge of SCK, the first data bit will be shifted out to the
SDO pin. The remaining data bits will be shifted out to the SDI pin on
subsequent falling edges of SCK. The SDO pin will present valid data at
least 100 ns before the rising edge of the SCK and remain valid for
100 ns after the rising edge of SCK. See

Figure 9-2

9.4 SIOP Registers

The SIOP is programmed and controlled by these registers:

�

SIOP control register (SCR) located at address $000A

�

SIOP status register (SSR) located at address $000B

�

SIOP data register (SDR) located at address $000C

9.4.1 SIOP Control Register

This register is located at address $000A and contains two bits.

Figure 9-3

shows the position of each bit in the register and indicates

the value of each bit after reset.

Address:

$000A

Bit 7

Bit 0

Read:

SPE

MSTR

Write:

Reset:

= Unimplemented

Figure 9-3. SIOP Control Register (SCR)

Serial Input/Output Ports (SIOP)

SIOP Registers

MC68HC05P18A

Technical Data

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Serial Input/Output Ports (SIOP)

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SPE -- Serial Peripheral Enable Bit

When set, the SPE bit enables the SIOP subsystem such that
SDO/PB5 is the serial data output, SDI/PB6 is the serial data input,
and SCK/PB7 is a serial clock input in the slave mode or a serial clock
output in the master mode. The port B DDR and data registers can be
manipulated as usual (except for PB5); however, these actions could
affect the transmitted or received data.

The SPE bit is readable and writable at any time. Clearing the SPE bit
while a transmission is in progress will:

1. Abort the transmission

2. Reset the serial bit counter

3. Convert the port B/SIOP port to a general-purpose I/O port

Reset clears the SPE bit.

MSTR -- Master Mode Select Bit

When set, the MSTR bit configures the serial I/O port for master
mode. A transfer is initiated by writing to the SDR. Also, the SCK pin
becomes an output providing a synchronous data clock dependent
upon the oscillator frequency. When the device is in slave mode, the
SDO and SDI pins do not change function. These pins behave exactly
the same in both the master and slave modes.

The MSTR bit is readable and writable at any time regardless of the
state of the SPE bit. Clearing the MSTR bit will abort any transfers that
may have been in progress. Reset clears the MSTR bit, placing the
SIOP subsystem in slave mode.

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Serial Input/Output Ports (SIOP)

Technical Data

MC68HC05P18A

Serial Input/Output Ports (SIOP)

MOTOROLA

9.4.2 SIOP Status Register

This register is located at address $000B and contains two bits.

Figure 9-4

shows the position of each bit in the register and indicates

the value of each bit after reset.

SPIF -- Serial Port Interface Flag

SPIF is a read-only status bit that is set on the last rising edge of SCK
and indicates that a data transfer has been completed. It has no effect
on any future data transfers and can be ignored. The SPIF bit is
cleared by reading the SSR followed by a read or write of the SDR. If
the SPIF is cleared before the last rising edge of SCK it will be set
again on the last rising edge of SCK. Reset clears the SPIF bit.

DCOL -- Data Collision Bit

DCOL is a read-only status bit, which indicates that an illegal access
of the SDR has occurred. The DCOL bit will be set when reading or
writing the SDR after the first falling edge of SCK and before SPIF is
set. Reading or writing the SDR during this time will result in invalid
data being transmitted or received.

The DCOL bit is cleared by reading the SSR (when the SPIF bit is set)
followed by a read or write of the SDR. If the last part of the clearing
sequence is done after another transfer has started, the DCOL bit will
be set again. Reset clears the DCOL bit.

Address:

$000B

Bit 7

Bit 0

Read:

SPIF

DCOL

Write:

Reset:

= Unimplemented

Figure 9-4. SIOP Status Register (SSR)

Serial Input/Output Ports (SIOP)

SIOP Registers

MC68HC05P18A

Technical Data

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Serial Input/Output Ports (SIOP)

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9.4.3 SIOP Data Register

This register is located at address $000C and serves as both the
transmit and receive data register. Writing to this register will initiate a
message transmission if the SIOP is in master mode. The SIOP
subsystem is not double buffered and any write to this register will
destroy the previous contents. The SDR can be read at any time;
however, if a transfer is in progress, the results may be ambiguous and
the DCOL bit will be set. Writing to the SDR while a transfer is in
progress can cause invalid data to be transmitted and/or received.

Figure 9-5

shows the position of each bit in the register. This register is

not affected by reset.

Address:

$000C

Bit 7

Bit 0

Read:

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

Write:

Reset:

Unaffected by reset

Figure 9-5. SIOP Data Register (SDR)

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EEPROM

Technical Data

MC68HC05P18A

EEPROM

MOTOROLA

10.3 EEPROM Programming Register

The contents and use of the programming register (EEPROG) are
discussed here.

CPEN -- Charge Pump Enable Bit

When set, CPEN enables the charge pump that produces the internal
EEPROM programming voltage. This bit should be set concurrently
with the LATCH bit. The programming voltage will not be available
until EEPGM is set. The charge pump should be disabled when not in
use. CPEN is readable and writable and is cleared by reset.

ER1 and ER0 -- Erase Select Bits

ER1 and ER0 form a 2-bit field that is used to select one of three
erase modes: byte, block, or bulk.

Table 10-1

shows the modes

selected for each bit configuration. These bits are readable and
writable and are cleared by reset.

Address: $001C

Bit 7

Bit 0

Read:

CPEN

ER1

ER0

LATCH

EERC

EEPGM

Write:

Reset:

= Unimplemented

Figure 10-1. EEPROM Programming Register (EEPROG)

Table 10-1. Erase Mode Select

ER1

ER0

Mode

Program, no erase

Byte erase

Block erase

Bulk erase

EEPROM

EEPROM Programming Register

MC68HC05P18A

Technical Data

MOTOROLA

EEPROM

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In byte erase mode, only the selected byte is erased. In block mode,
a 32-byte block of EEPROM is erased. The EEPROM memory space
is divided into four 32-byte blocks ($140�$15F, $160�$17F,
$180�$19F, $1A0�$1BF), and doing a block erase to any address
within a block erases the entire block. In bulk erase mode, the entire
128-byte EEPROM section is erased.

LATCH -- EEPROM Programming Latch Bit

When set, LATCH configures the EEPROM address and data bus for
programming. When LATCH is set, writes to the EEPROM array
cause the data bus and the address bus to be latched. This bit is
readable and writable, but reads from the array are inhibited if the
LATCH bit is set and a write to the EEPROM space has taken place.
When clear, address and data buses are configured for normal
operation. Reset clears this bit.

EERC -- EEPROM RC Oscillator Control Bit

When this bit is set, the EEPROM section uses the internal RC
oscillator instead of the CPU clock. The RC oscillator is shared with
the analog-to-digital (A/D) converter, so this bit should be set by the
user when the internal bus frequency is below 1.5 MHz to guarantee
reliable operation of the EEPROM or A/D converter. After setting the
EERC bit, delay a time, t

RCON

, to allow the RC oscillator to stabilize.

This bit is readable and writable. The EERC bit is cleared by reset.
The RC oscillator is disabled while the MCU is in stop mode.

EEPGM -- EEPROM Programming Power Enable Bit

EEPGM must be written to enable (or disable) the EEPGM function.
When set, EEPGM turns on the charge pump and enables the
programming (or erasing) power to the EEPROM array. When clear,
this power is switched off. This enables pulsing of the programming
voltage to be controlled internally. This bit can be read at any time, but
can only be written to if LATCH = 1. If LATCH is not set, EEPGM
cannot be set. LATCH and EEPGM cannot both be set with one write
if LATCH is cleared. EEPGM is cleared automatically when LATCH is
cleared. Reset clears this bit.

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EEPROM

Technical Data

MC68HC05P18A

EEPROM

MOTOROLA

10.4 Programming/Erasing Procedures

To program a byte of EEPROM:

1. Set EELAT = CPEN = 1.

2. Set ER1 = ER0 = 0.

3. Write data to the desired address.

4. Set EEPGM for a time, t

EEPGM

Any bit should be erased before it is programmed. However, if
write/erase cycling is a concern, a procedure can be followed to
minimize the cycling of each bit in each EEPROM byte.

Here is the procedure:

�

If PB � EB = 0 -- Program the new data over the existing data
without erasing it first.

�

If PB � EB

0 -- Erase byte before programming.

Where:

PB = Byte data to be programmed
EB = Existing EEPROM byte data

To erase a byte of EEPROM:

1. Set LATCH = 1, CPEN = 1, ER1 = 0, and ER0 = 1.

2. Write to the address to be erased.

3. Set EEPGM for a time, t

EBYT

To erase a block of EEPROM:

1. Set LATCH = 1, CPEN = 1, ER1 = 1, and ER0 = 0.

2. Write to any address in the block.

3. Set EEPGM for a time, t

EBLOCK

MC68HC05P18A

Technical Data

MOTOROLA

Analog-to-Digital (A/D) Converter

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Technical Data -- MC68HC05P18A

Section 11. Analog-to-Digital (A/D) Converter

11.1 Contents

11.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

11.3

Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

11.3.1

Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

11.3.2

Reference Supply Voltage (V

REFH

) . . . . . . . . . . . . . . . . . . .92

11.3.3

Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

11.4

Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

11.5

Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

11.5.1

Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

11.5.2

Internal versus External Oscillator . . . . . . . . . . . . . . . . . . . .93

11.5.3

Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .94

11.6

A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . .94

11.7

A/D Conversion Data Register . . . . . . . . . . . . . . . . . . . . . . . . .96

11.8

A/D Subsystem Operation during Wait Mode

and Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

11.9

A/D Subsystem Operation during Stop Mode. . . . . . . . . . . . . .96

11.2 Introduction

The MC68HC05P18A includes a 4-channel, multiplexed input, 8-bit,
successive approximation analog-to-digital (A/D) converter. The A/D
subsystem shares its inputs with port C pins PC3璓C7.

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Analog-to-Digital (A/D) Converter

Technical Data

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Analog-to-Digital (A/D) Converter

MOTOROLA

11.3 Analog Section

The following paragraphs describe the operation and performance of
analog modules within the analog subsystem.

11.3.1 Ratiometric Conversion

The A/D converter is ratiometric, with pin V

REFH

supplying the high

reference voltage. Applying an input voltage equal to V

REFH

produces a

conversion result of $FF (full scale). Applying an input voltage equal to
V

produces a conversion result of $00. An input voltage greater than

REFH

converts to $FF with no overflow indication. For ratiometric

conversions, V

REFH

should be at the same potential as the supply

voltage being used by the analog signal being measured and be
referenced to V

11.3.2 Reference Supply Voltage (V

REFH

)

The reference supply for the A/D converter shares pin PC7 with port C.
The low reference is tied to the V

pin internally. V

REFH

can be any

voltage between V

and V

; however, the accuracy of conversions is

tested and guaranteed only for V

REFH

= V

11.3.3 Accuracy and Precision

The 8-bit conversion result is accurate to within

�

1 1/2 LSB (least

significant bit), including quantization; however, the accuracy of
conversions is tested and guaranteed only with external oscillator
operation.

11.4 Conversion Process

The A/D reference inputs are applied to a precision digital-to-analog
(D/A) converter. Control logic drives the D/A and the analog output is
successively compared to the selected analog input that was sampled at

Analog-to-Digital (A/D) Converter

Digital Section

MC68HC05P18A

Technical Data

MOTOROLA

Analog-to-Digital (A/D) Converter

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the beginning of the conversion cycle. The conversion process is
monotonic and has no missing codes.

11.5 Digital Section

The following paragraphs describe the operation and performance of
digital modules within the analog subsystem.

11.5.1 Conversion Times

Each input conversion requires 32 PH2 clock cycles, which must be at a
frequency equal to or greater than 1 MHz.

11.5.2 Internal versus External Oscillator

If the MCU PH2 clock frequency is less than 1 MHz (2 MHz external
oscillator), the internal RC oscillator (approximately 1.5 MHz) must be
used for the A/D converter clock. The internal RC clock is selected by
setting the EERC bit in the EEPROM program register (EEPROG).

NOTE:

The RC oscillator is shared with the EEPROM module. The RC oscillator
is disabled while the MCU is in stop mode.

When the internal RC oscillator is being used, these limitations apply:

1. Since the internal RC oscillator is running asynchronously with

respect to the PH2 clock, the conversion complete (CC) bit in the
A/D status and control register (ADSC) must be used to determine
when a conversion sequence has been completed.

2. Electrical noise slightly degrades the accuracy of the A/D

converter. The A/D converter is synchronized to read voltages
during the quiet period of the clock driving it. Since the internal and
external clocks are not synchronized, the A/D converter
occasionally measures an input when the external clock is making
a transition.

3. If the PH2 clock is 1 MHz or greater (for example, external

oscillator 2 MHz or greater), the internal RC oscillator should be
turned off and the external oscillator used as the conversion clock.

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Analog-to-Digital (A/D) Converter

Technical Data

MC68HC05P18A

Analog-to-Digital (A/D) Converter

MOTOROLA

11.5.3 Multi-Channel Operation

An input multiplexer allows the A/D converter to select from one of four
external analog signals. Port C pins PC3璓C6 are shared with the inputs
to the multiplexer.

11.6 A/D Status and Control Register

The A/D status and control register (ADSCR) reports the completion of
A/D conversion and provides control over:

�

Oscillator selection

�

Analog subsystem power

�

Input channel selection

See

Figure 11-1

CC -- Conversion Complete Bit

This read-only status bit is set when a conversion sequence has
completed and data is ready to be read from the ADC register. CC is
cleared when a channel is selected for conversion, when data is read
from the ADC register, or when the A/D subsystem is turned off. Once
a conversion is started, conversions of the selected channel continue
every 32 PH2 clock cycles until the ADSC register is written to again.
During continuous conversion operation, the ADC register is updated
with new data, and the CC bit is set, every 32 PH2 clock cycles. Also,
data from the previous conversion is overwritten regardless of the
state of the CC bit.

Address:

$001E

Bit 7

Bit 0

Read:

ADON

CH2

CH1

CH0

Write:

Reset:

= Unimplemented

= Reserved

Figure 11-1. A/D Status and Control Register (ADSCR)

Analog-to-Digital (A/D) Converter

A/D Status and Control Register

MC68HC05P18A

Technical Data

MOTOROLA

Analog-to-Digital (A/D) Converter

NON-DISCLOSURE AGREEMENT REQUIRED

R -- Reserved Bit

This bit is not currently used. It can be read or written, but does not
control anything.

ADON -- A/D Subsystem On Bit

When the A/D subsystem is turned on (ADON = 1), it requires a time
t

ADON

to stabilize before accurate conversion results can be attained.

CH2瑿H0 -- Channel Select Bits

CH2, CH1, and CH0 form a 3-bit field that is used to select an input to
the A/D converter. Channels 0�3 correspond to port C input pins
PC6璓C3. Channels 4�6 are used for reference measurements. In
user mode, channel 7 is reserved. If a conversion is attempted with
channel 7 selected, the result is $00.

Table 11-1

lists the inputs

selected by bits CH0瑿H3.

If the ADON bit is set, and an input from channels 0�4 is selected, the
corresponding port C pin's DDR bit is cleared (making that port C pin
an input). If the port C data register is read while the A/D is on, and
one of the shared input channels is selected using bit CH0瑿H2, the
corresponding port C pin reads as a logic 0. The remaining port C pins
read normally. To digitally read a port C pin, the A/D subsystem must
be disabled (ADON = 0) or input channel 5�7 must be selected.

Table 11-1. A/D Multiplexer Input

Channel Assignments

Channel

Signal

AD0 port C bit 6

AD1 port C bit 5

AD2 port C bit 4

AD3 port C bit 3

REFH

port C bit 7

REFH

+ V

)/2

Reserved

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Analog-to-Digital (A/D) Converter

Technical Data

MC68HC05P18A

Analog-to-Digital (A/D) Converter

MOTOROLA

11.7 A/D Conversion Value Data Register

This register contains the output of the A/D converter. See

Figure 11-2

11.8 A/D Subsystem Operation during Wait Mode and Halt Mode

The A/D subsystem continues normal operation during wait mode and
halt mode. To decrease power consumption during wait or halt, the
ADON bit in the ADSC register and the EERC bit in the EEPROG
register should be cleared if the A/D subsystem is not being used.

11.9 A/D Subsystem Operation during Stop Mode

When stop mode is enabled, execution of the STOP instruction
terminates all A/D subsystem functions. Any pending conversion is
aborted. When the oscillator resumes operation upon leaving the stop
mode, a finite amount of time passes before the A/D subsystem
stabilizes sufficiently to provide conversions at its rated accuracy. The
delays built into the MC68HC05P18A when coming out of stop mode are
sufficient for this purpose. No explicit delays need to be added to the
application software.

Address:

$001D

Bit 7

Bit 0

Read:

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Write:

Reset:

Unaffected by reset

= Unimplemented

= Reserved

Figure 11-2. A/D Conversion Value Data Register (ADC)

MC68HC05P18A

Technical Data

MOTOROLA

Instruction Set

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Technical Data -- MC68HC05P18A

Section 12. Instruction Set

12.1 Contents

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

12.3

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

12.3.1

Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

12.3.2

Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

12.3.3

Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

12.3.4

Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

12.3.5

Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

12.3.6

Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

12.3.7

Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

12.3.8

Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

12.4

Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

12.4.1

12.4.2

Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .103

12.4.3

Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .104

12.4.4

Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .106

12.4.5

Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

12.5

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

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Instruction Set

Technical Data

MC68HC05P18A

Instruction Set

MOTOROLA

12.2 Introduction

The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.

12.3 Addressing Modes

The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction.

The eight addressing modes are:

�

Inherent

�

Immediate

�

Direct

�

Extended

�

Indexed, no offset

�

Indexed, 8-bit offset

�

Indexed, 16-bit offset

�

Relative

Instruction Set

Addressing Modes

MC68HC05P18A

Technical Data

MOTOROLA

Instruction Set

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12.3.1 Inherent

Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.

12.3.2 Immediate

Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.

12.3.3 Direct

Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.

12.3.4 Extended

Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.

When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.

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Instruction Set

Technical Data

MC68HC05P18A

100

Instruction Set

MOTOROLA

12.3.5 Indexed, No Offset

Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000�$00FF.

Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.

12.3.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000�$01FE.

Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.

12.3.7 Indexed,16-Bit Offset

Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.

Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.

As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.

Instruction Set

Instruction Types

MC68HC05P18A

Technical Data

MOTOROLA

Instruction Set

101

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12.3.8 Relative

Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two's complement byte that gives
a branching range of �128 to +127 bytes from the address of the next
location after the branch instruction.

When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.

12.4 Instruction Types

The MCU instructions fall into five categories:

�

Read-modify-write instructions

�

Jump/branch instructions

�

Bit manipulation instructions

�

Control instructions

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Instruction Set

Technical Data

MC68HC05P18A

102

Instruction Set

MOTOROLA

12.4.1 Register/Memory Instructions

These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.

Table 12-1. Register/Memory Instructions

Instruction

Mnemonic

Add memory byte and carry bit to accumulator

ADC

Add memory byte to accumulator

ADD

AND memory byte with accumulator

AND

Bit test accumulator

BIT

Compare accumulator

CMP

Compare index register with memory byte

CPX

Exclusive OR accumulator with memory byte

EOR

Load accumulator with memory byte

LDA

Load Index register with memory byte

LDX

Multiply

MUL

OR accumulator with memory byte

ORA

Subtract memory byte and carry bit from
accumulator

SBC

Store accumulator in memory

STA

Store index register in memory

STX

Subtract memory byte from accumulator

SUB

Instruction Set

Instruction Types

MC68HC05P18A

Technical Data

MOTOROLA

Instruction Set

103

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12.4.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.

NOTE:

Do not use read-modify-write operations on write-only registers.

Table 12-2. Read-Modify-Write Instructions

Instruction

Mnemonic

Arithmetic shift left (same as LSL)

ASL

Arithmetic shift right

ASR

Bit clear

BCLR

(1)

1. Unlike other read-modify-write instructions, BCLR and BSET use

only direct addressing.

Bit set

BSET

(1)

Clear register

CLR

Complement (one's complement)

COM

Decrement

DEC

Increment

INC

Logical shift left (same as ASL)

LSL

Logical shift right

LSR

Negate (two's complement)

NEG

Rotate left through carry bit

ROL

Rotate right through carry bit

ROR

Test for negative or zero

TST

(2)

2. TST is an exception to the read-modify-write sequence because it

does not write a replacement value.

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Instruction Set

Technical Data

MC68HC05P18A

104

Instruction Set

MOTOROLA

12.4.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.

The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from �128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.

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Instruction Set

Technical Data

MC68HC05P18A

108

Instruction Set

MOTOROLA

12.5 Instruction Set Summary

Table 12-6. Instruction Set Summary (Sheet 1 of 6)

Source

Form

Operation

Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

H I N Z C

ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X

Add with Carry

(A) + (M) + (C)

IMM

DIR

EXT

IX2
IX1

A9
B9
C9
D9
E9
F9

hh ll

ee ff

2
3
4
5
4
3

ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X

Add without Carry

(A) + (M)

IMM

DIR

EXT

IX2
IX1

AB
BB
CB
DB
EB
FB

hh ll

ee ff

2
3
4
5
4
3

AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X

Logical AND

(A)

(M)

-- --

IMM

DIR

EXT

IX2
IX1

A4
B4
C4
D4
E4
F4

hh ll

ee ff

2
3
4
5
4
3

ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X

Arithmetic Shift Left (Same as LSL)

-- --

DIR
INH
INH

IX1

38
48
58
68
78

5
3
3
6
5

ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X

Arithmetic Shift Right

-- --

DIR
INH
INH

IX1

37
47
57
67
77

5
3
3
6
5

BCC rel

Branch if Carry Bit Clear

(PC) + 2 + rel ? C = 0

-- -- -- -- --

REL

BCLR n opr

Clear Bit n

-- -- -- -- --

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

11
13
15
17
19

1B
1D
1F

dd
dd
dd
dd
dd
dd
dd
dd

5
5
5
5
5
5
5
5

BCS rel

Branch if Carry Bit Set (Same as BLO)

(PC) + 2 + rel ? C = 1

-- -- -- -- --

REL

BEQ rel

Branch if Equal

(PC) + 2 + rel ? Z = 1

-- -- -- -- --

REL

BHCC rel

Branch if Half-Carry Bit Clear

(PC) + 2 + rel ? H = 0

-- -- -- -- --

REL

BHCS rel

Branch if Half-Carry Bit Set

(PC) + 2 + rel ? H = 1

-- -- -- -- --

REL

BHI rel

Branch if Higher

(PC) + 2 + rel ? C

Z = 0 -- -- -- -- --

REL

BHS rel

Branch if Higher or Same

(PC) + 2 + rel ? C = 0

-- -- -- -- --

REL

Instruction Set

Instruction Set Summary

MC68HC05P18A

Technical Data

MOTOROLA

Instruction Set

109

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BIH rel

Branch if IRQ Pin High

(PC) + 2 + rel ? IRQ = 1

-- -- -- -- --

REL

BIL rel

Branch if IRQ Pin Low

(PC) + 2 + rel ? IRQ = 0

-- -- -- -- --

REL

BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X

Bit Test Accumulator with Memory Byte

(A)

(M)

-- --

IMM

DIR

EXT

IX2
IX1

A5
B5
C5
D5
E5
F5

hh ll

ee ff

2
3
4
5
4
3

BLO rel

Branch if Lower (Same as BCS)

(PC) + 2 + rel ? C = 1

-- -- -- -- --

REL

BLS rel

Branch if Lower or Same

(PC) + 2 + rel ? C

Z = 1 -- -- -- -- --

REL

BMC rel

Branch if Interrupt Mask Clear

(PC) + 2 + rel ? I = 0

-- -- -- -- --

REL

BMI rel

Branch if Minus

(PC) + 2 + rel ? N = 1

-- -- -- -- --

REL

BMS rel

Branch if Interrupt Mask Set

(PC) + 2 + rel ? I = 1

-- -- -- -- --

REL

BNE rel

Branch if Not Equal

(PC) + 2 + rel ? Z = 0

-- -- -- -- --

REL

BPL rel

Branch if Plus

(PC) + 2 + rel ? N = 0

-- -- -- -- --

REL

BRA rel

Branch Always

(PC) + 2 + rel ? 1 = 1

-- -- -- -- --

REL

BRCLR n opr rel Branch if Bit n Clear

(PC) + 2 + rel ? Mn = 0

-- -- -- --

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

01
03
05
07
09

0B
0D
0F

dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr

5
5
5
5
5
5
5
5

BRN rel

Branch Never

(PC) + 2 + rel ? 1 = 0

-- -- -- -- --

REL

BRSET n opr rel Branch if Bit n Set

(PC) + 2 + rel ? Mn = 1

-- -- -- --

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

00
02
04
06
08

0A
0C
0E

dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr

5
5
5
5
5
5
5
5

BSET n opr

Set Bit n

-- -- -- -- --

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

10
12
14
16
18

1A
1C
1E

dd
dd
dd
dd
dd
dd
dd
dd

5
5
5
5
5
5
5
5

BSR rel

Branch to Subroutine

(PC) + 2; push (PCL)

(SP) � 1; push (PCH)

(SP) � 1

(PC) + rel

-- -- -- -- --

REL

CLC

Clear Carry Bit

-- -- -- -- 0

INH

CLI

Clear Interrupt Mask

-- 0 -- -- --

INH

Table 12-6. Instruction Set Summary (Sheet 2 of 6)

Source

Form

Operation

Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

H I N Z C

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Instruction Set

Technical Data

MC68HC05P18A

110

Instruction Set

MOTOROLA

CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X

Clear Byte

$00

-- -- 0

1 --

DIR
INH
INH

IX1

3F
4F
5F
6F
7F

5
3
3
6
5

CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X

Compare Accumulator with Memory Byte

(A) � (M)

-- --

IMM

DIR

EXT

IX2
IX1

A1
B1
C1
D1
E1
F1

hh ll

ee ff

2
3
4
5
4
3

COM opr
COMA
COMX
COM opr,X
COM ,X

Complement Byte (One's Complement)

(M) = $FF � (M)

(A) = $FF � (A)

(X) = $FF � (X)

(M) = $FF � (M)

-- --

DIR
INH
INH

IX1

33
43
53
63
73

5
3
3
6
5

CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X

Compare Index Register with Memory Byte

(X) � (M)

-- --

IMM

DIR

EXT

IX2
IX1

A3
B3
C3
D3
E3
F3

hh ll

ee ff

2
3
4
5
4
3

DEC opr
DECA
DECX
DEC opr,X
DEC ,X

Decrement Byte

(M) � 1

(A) � 1

(X) � 1

(M) � 1

-- --

DIR
INH
INH

IX1

3A
4A
5A
6A
7A

5
3
3
6
5

EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X

EXCLUSIVE OR Accumulator with Memory
Byte

(A)

(M)

-- --

IMM

DIR

EXT

IX2
IX1

A8
B8
C8
D8
E8
F8

hh ll

ee ff

2
3
4
5
4
3

INC opr
INCA
INCX
INC opr,X
INC ,X

Increment Byte

(M) + 1

(A) + 1

(X) + 1

(M) + 1

-- --

DIR
INH
INH

IX1

3C
4C
5C
6C
7C

5
3
3
6
5

JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X

Unconditional Jump

Jump Address

-- -- -- -- --

DIR

EXT

IX2
IX1

BC
CC
DC
EC
FC

hh ll

ee ff

2
3
4
3
2

Table 12-6. Instruction Set Summary (Sheet 3 of 6)

Source

Form

Operation

Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

H I N Z C

Instruction Set

Instruction Set Summary

MC68HC05P18A

Technical Data

MOTOROLA

Instruction Set

111

NON-DISCLOSURE AGREEMENT REQUIRED

JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X

Jump to Subroutine

(PC) + n (n = 1, 2, or 3)

Push (PCL); SP

(SP) � 1

Push (PCH); SP

(SP) � 1

Effective Address

-- -- -- -- --

DIR

EXT

IX2
IX1

BD
CD
DD
ED
FD

hh ll

ee ff

5
6
7
6
5

LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X

Load Accumulator with Memory Byte

(M)

-- --

IMM

DIR

EXT

IX2
IX1

A6
B6
C6
D6
E6
F6

hh ll

ee ff

2
3
4
5
4
3

LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X

Load Index Register with Memory Byte

(M)

-- --

IMM

DIR

EXT

IX2
IX1

AE
BE
CE
DE
EE
FE

hh ll

ee ff

2
3
4
5
4
3

LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X

Logical Shift Left (Same as ASL)

-- --

DIR
INH
INH

IX1

38
48
58
68
78

5
3
3
6
5

LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X

Logical Shift Right

-- -- 0

DIR
INH
INH

IX1

34
44
54
64
74

5
3
3
6
5

MUL

Unsigned Multiply

X : A

(X)

�

(A)

0 -- -- -- 0

INH

1
1

NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X

Negate Byte (Two's Complement)

�(M) = $00 � (M)

�(A) = $00 � (A)

�(X) = $00 � (X)

�(M) = $00 � (M)

-- --

DIR
INH
INH

IX1

30
40
50
60
70

5
3
3
6
5

NOP

No Operation

-- -- -- -- --

INH

ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X

Logical OR Accumulator with Memory

(A)

(M)

-- --

IMM

DIR

EXT

IX2
IX1

AA
BA
CA
DA
EA

hh ll

ee ff

2
3
4
5
4
3

ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X

Rotate Byte Left through Carry Bit

-- --

DIR
INH
INH

IX1

39
49
59
69
79

5
3
3
6
5

Table 12-6. Instruction Set Summary (Sheet 4 of 6)

Source

Form

Operation

Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

H I N Z C

NON-DISCLOSURE AGREEMENT REQUIRED

Instruction Set

Technical Data

MC68HC05P18A

112

Instruction Set

MOTOROLA

ROR opr
RORA
RORX
ROR opr,X
ROR ,X

Rotate Byte Right through Carry Bit

-- --

DIR
INH
INH

IX1

36
46
56
66
76

5
3
3
6
5

RSP

Reset Stack Pointer

$00FF

-- -- -- -- --

INH

RTI

Return from Interrupt

(SP) + 1; Pull (CCR)

(SP) + 1; Pull (A)

(SP) + 1; Pull (X)

(SP) + 1; Pull (PCH)

(SP) + 1; Pull (PCL)

INH

RTS

Return from Subroutine

(SP) + 1; Pull (PCH)

(SP) + 1; Pull (PCL)

-- -- -- -- --

INH

SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X

Subtract Memory Byte and Carry Bit from
Accumulator

(A) � (M) � (C)

-- --

IMM

DIR

EXT

IX2
IX1

A2
B2
C2
D2
E2
F2

hh ll

ee ff

2
3
4
5
4
3

SEC

Set Carry Bit

-- -- -- -- 1

INH

SEI

Set Interrupt Mask

-- 1 -- -- --

INH

STA opr
STA opr
STA opr,X
STA opr,X
STA ,X

Store Accumulator in Memory

(A)

-- --

DIR

EXT

IX2
IX1

B7
C7
D7
E7
F7

hh ll

ee ff

4
5
6
5
4

STOP

Stop Oscillator and Enable IRQ Pin

-- 0 -- -- --

INH

STX opr
STX opr
STX opr,X
STX opr,X
STX ,X

Store Index Register In Memory

(X)

-- --

DIR

EXT

IX2
IX1

BF
CF
DF
EF
FF

hh ll

ee ff

4
5
6
5
4

SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X

Subtract Memory Byte from Accumulator

(A) � (M)

-- --

IMM

DIR

EXT

IX2
IX1

A0
B0
C0
D0
E0
F0

hh ll

ee ff

2
3
4
5
4
3

SWI

Software Interrupt

(PC) + 1; Push (PCL)

(SP) � 1; Push (PCH)

(SP) � 1; Push (X)

(SP) � 1; Push (A)

(SP) � 1; Push (CCR)

(SP) � 1; I

PCH

Interrupt Vector High Byte

PCL

Interrupt Vector Low Byte

-- 1 -- -- --

INH

1
0

TAX

Transfer Accumulator to Index Register

(A)

-- -- -- -- --

INH

Table 12-6. Instruction Set Summary (Sheet 5 of 6)

Source

Form

Operation

Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

H I N Z C

Instruction Set

Instruction Set Summary

MC68HC05P18A

Technical Data

MOTOROLA

Instruction Set

113

NON-DISCLOSURE AGREEMENT REQUIRED

TST opr
TSTA
TSTX
TST opr,X
TST ,X

Test Memory Byte for Negative or Zero

(M) � $00

-- --

DIR
INH
INH

IX1

3D
4D
5D
6D
7D

4
3
3
5
4

TXA

Transfer Index Register to Accumulator

(X)

-- -- -- -- --

INH

WAIT

Stop CPU Clock and Enable Interrupts

-- 0 -- -- --

INH

Accumulator

opr

Operand (one or two bytes)

Carry/borrow flag

Program counter

CCR

Condition code register

PCH

Program counter high byte

Direct address of operand

PCL

Program counter low byte

dd rr

Direct address of operand and relative offset of branch instruction

REL

Relative addressing mode

DIR

Direct addressing mode

rel

Relative program counter offset byte

ee ff

High and low bytes of offset in indexed, 16-bit offset addressing

Relative program counter offset byte

EXT

Extended addressing mode

Stack pointer

Offset byte in indexed, 8-bit offset addressing

Index register

Half-carry flag

Zero flag

hh ll

High and low bytes of operand address in extended addressing

Immediate value

Interrupt mask

Logical AND

Immediate operand byte

Logical OR

IMM

Immediate addressing mode

Logical EXCLUSIVE OR

INH

Inherent addressing mode

( )

Contents of

Indexed, no offset addressing mode

�( )

Negation (two's complement)

IX1

Indexed, 8-bit offset addressing mode

Loaded with

IX2

Indexed, 16-bit offset addressing mode

Memory location

Concatenated with

Negative flag

Set or cleared

Any bit

Not affected

Table 12-6. Instruction Set Summary (Sheet 6 of 6)

Source

Form

Operation

Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

H I N Z C

N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D

Technical Data

MC68HC05P18A

114

Instruction Set

MOTOROLA

Instr

uction Set

Table 12-7. Opcode Map

Bit Manipulation

Branch

Read-Modify-Write

Control

Register/Memory

DIR

REL

DIR

INH

IX1

INH

IMM

DIR

EXT

IX2

IX1

BRSET0

DIR

BSET0

DIR

BRA

REL

NEG

DIR

NEGA

INH

NEGX

INH

NEG

IX1

NEG

RTI

INH

SUB

IMM

SUB

DIR

SUB

EXT

SUB

IX2

SUB

IX1

SUB

BRCLR0

DIR

BCLR0

DIR

BRN

REL

RTS

INH

CMP

IMM

CMP

DIR

CMP

EXT

CMP

IX2

CMP

IX1

CMP

BRSET1

DIR

BSET1

DIR

BHI

REL

MUL

INH

SBC

IMM

SBC

DIR

SBC

EXT

SBC

IX2

SBC

IX1

SBC

BRCLR1

DIR

BCLR1

DIR

BLS

REL

COM

DIR

COMA

INH

COMX

INH

COM

IX1

COM

SWI

INH

CPX

IMM

CPX

DIR

CPX

EXT

CPX

IX2

CPX

IX1

CPX

BRSET2

DIR

BSET2

DIR

BCC

REL

LSR

DIR

LSRA

INH

LSRX

INH

LSR

IX1

LSR

AND

IMM

AND

DIR

AND

EXT

AND

IX2

AND

IX1

AND

BRCLR2

DIR

BCLR2

DIR

BCS/BLO

REL

BIT

IMM

BIT

DIR

BIT

EXT

BIT

IX2

BIT

IX1

BIT

BRSET3

DIR

BSET3

DIR

BNE

REL

ROR

DIR

RORA

INH

RORX

INH

ROR

IX1

ROR

LDA

IMM

LDA

DIR

LDA

EXT

LDA

IX2

LDA

IX1

LDA

BRCLR3

DIR

BCLR3

DIR

BEQ

REL

ASR

DIR

ASRA

INH

ASRX

INH

ASR

IX1

ASR

TAX

INH

STA

DIR

STA

EXT

STA

IX2

STA

IX1

STA

BRSET4

DIR

BSET4

DIR

BHCC

REL

ASL/LSL

DIR

ASLA/LSLA
1

INH

ASLX/LSLX
1

INH

ASL/LSL

IX1

ASL/LSL

CLC

INH

EOR

IMM

EOR

DIR

EOR

EXT

EOR

IX2

EOR

IX1

EOR

BRCLR4

DIR

BCLR4

DIR

BHCS

REL

ROL

DIR

ROLA

INH

ROLX

INH

ROL

IX1

ROL

SEC

INH

ADC

IMM

ADC

DIR

ADC

EXT

ADC

IX2

ADC

IX1

ADC

BRSET5

DIR

BSET5

DIR

BPL

REL

DEC

DIR

DECA

INH

DECX

INH

DEC

IX1

DEC

CLI

INH

ORA

IMM

ORA

DIR

ORA

EXT

ORA

IX2

ORA

IX1

ORA

BRCLR5

DIR

BCLR5

DIR

BMI

REL

SEI

INH

ADD

IMM

ADD

DIR

ADD

EXT

ADD

IX2

ADD

IX1

ADD

BRSET6

DIR

BSET6

DIR

BMC

REL

INC

DIR

INCA

INH

INCX

INH

INC

IX1

INC

RSP

INH

JMP

DIR

JMP

EXT

JMP

IX2

JMP

IX1

JMP

BRCLR6

DIR

BCLR6

DIR

BMS

REL

TST

DIR

TSTA

INH

TSTX

INH

TST

IX1

TST

NOP

INH

BSR

REL

JSR

DIR

JSR

EXT

JSR

IX2

JSR

IX1

JSR

BRSET7

DIR

BSET7

DIR

BIL

REL

STOP

INH

LDX

IMM

LDX

DIR

LDX

EXT

LDX

IX2

LDX

IX1

LDX

BRCLR7

DIR

BCLR7

DIR

BIH

REL

CLR

DIR

CLRA

INH

CLRX

INH

CLR

IX1

CLR

WAIT

INH

TXA

INH

STX

DIR

STX

EXT

STX

IX2

STX

IX1

STX

INH = Inherent

REL = Relative

IMM = Immediate

IX = Indexed, No Offset

DIR = Direct

IX1 = Indexed, 8-Bit Offset

EXT = Extended

IX2 = Indexed, 16-Bit Offset

MSB of Opcode in Hexadecimal

LSB of Opcode in Hexadecimal

BRSET0

DIR

Number of Cycles
Opcode Mnemonic
Number of Bytes/Addressing Mode

LSB

MSB

LSB

MSB

LSB

MSB

MC68HC05P18A

Technical Data

MOTOROLA

Electrical Specifications

115

NON-DISCLOSURE AGREEMENT REQUIRED

Technical Data -- MC68HC05P18A

Section 13. Electrical Specifications

13.1 Contents

13.2

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

13.3

Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .116

13.4

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

13.5

Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

13.6

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .118

13.7

Active Reset Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .119

13.8

A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .120

13.9

SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

13.10 PD5 Clock Out Timing (PD5 Clock Out Option Enabled) . . . .122

13.11 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

NON-DISCLOSURE AGREEMENT REQUIRED

Electrical Specifications

Technical Data

MC68HC05P18A

116

Electrical Specifications

MOTOROLA

13.2 Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.

The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep V

and V

Out

within the range

or V

Out

)

. Connect unused inputs to the appropriate

voltage level, either V

or V

NOTE:

This device is not guaranteed to operate properly at the maximum
ratings. Refer to

13.6 DC Electrical Characteristics

for guaranteed

operating conditions.

13.3 Operating Temperature Range

13.4 Thermal Characteristics

Rating

Symbol

Value

Unit

Supply voltage

�0.3 to +7.0

Input voltage

�0.3

to V

+0.3

Current drain per pin excluding

and V

Storage temperature range

STG

�65 to +150

�

Characteristic

Symbol

Value

Unit

Operating temperature range

Standard
Extended
Automotive

to T

0 to +70

�40 to +85

�40 to +125

�

Maximum junction temperature

150

�

Characteristic

Symbol

Value

Unit

Thermal resistance

PDIP (28 pin)
SOIC (28 pin)

60
60

�

C/W

Electrical Specifications

Power Considerations

MC68HC05P18A

Technical Data

MOTOROLA

Electrical Specifications

117

NON-DISCLOSURE AGREEMENT REQUIRED

13.5 Power Considerations

The average chip junction temperature, T

, in

�

C can be obtained from:

= T

+ (P

)

(1)

Where:

= ambient temperature in

�

= package thermal resistance, junction to ambient in

�

C/W

= P

INT

+ P

I/O

INT

= I

�

= chip internal power dissipation

I/O

= power dissipation on input and output pins (user-determined)

For most applications, P

I/O

INT

and can be neglected.

Ignoring P

I/O

, the relationship between P

and T

is approximately:

(2)

Solving equations (1) and (2) for K gives:

= P

x (T

+ 273

�

C) +

x (P

)

(3)

where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring P

(at equilibrium) for a

known T

. Using this value of K, the values of P

and T

can be obtained

by solving equations (1) and (2) iteratively for any value of T

+ 273

�

NON-DISCLOSURE AGREEMENT REQUIRED

Electrical Specifications

Technical Data

MC68HC05P18A

118

Electrical Specifications

MOTOROLA

13.6 DC Electrical Characteristics

Characteristic

(1)

Symbol

Min

Max

Unit

Output voltage

Load

= 10.0

�

�0.1

0.1

Output high voltage

Load

0.8 mA) PA0璓A7, PB5璓B7, PC0璓C7, PD5/CKOUT

Load

5 mA) PC0, PC1

�0.8

Output low voltage

Load

= 1.6 mA) PA0璓A7, PB5璓B7, PC0璓C7, PD5/CKOUT

Load

10 mA) PC0, PC1

0.4

Input high voltage

PA0璓A7, PB5璓B7, PC0璓C7, PD5/CKOUT, TCAP/PD7,
IRQ, RESET, OSC1

0.7 x V

Input low voltage

PA0璓A7, PB5璓B7, PC0璓C7, PD5, TCAP/PD7, IRQ,
RESET, OSC1

0.3 x V

Supply current

(2) (3) (4)

Low frequency (2-MHz bus)

Run
Wait (A2D on)
Wait (A2D off)

High frequency (4-MHz bus)

Run
Wait (A2D on)
Wait (A2D off)

Stop (�40

�

C to +132

�

LVR disabled
LVR enabled

--
--
--

--
--

3.5
2.5

4.5
4.6

200

mA
mA
mA

�

I/O ports hi-z leakage current

PA0璓A7, PB5璓B7, PC0璓C7, PD5/CKOUT, TCAP/PD7

�

I/O ports switch resistance (pullup enabled PA0璓A7)

PTA

A/D ports hi-z leakage current

PC3璓C7

�

Input current

RESET, IRQ, OSC1

�

Capacitance

Ports (as input or output)
RESET, IRQ

Out

--
--

Continued

Electrical Specifications

Active Reset Characteristics

MC68HC05P18A

Technical Data

MOTOROLA

Electrical Specifications

119

NON-DISCLOSURE AGREEMENT REQUIRED

13.7 Active Reset Characteristics

EEPROM program/erase time

Byte
Block
Bulk

--
--
--

100

Low-voltage reset inhibit

LVRI

3.5

4.3

1. V

= 5.0 Vdc

�

10%, V

= 0 Vdc, T

= �40

�

C to +125

�

C, unless otherwise noted. All values shown reflect average

measurements.

2. Run (Operating) I

, wait I

: Measured using external square wave clock source to OSC1 (f

OSC

= 4.2 MHz), all inputs

0.2 Vdc from rail; no DC loads, less than 50 pF on all outputs, C

= 20 pF on OSC2

3. Wait I

: Only timer system active

Wait I

is affected linearly by the OSC2 capacitance.

Wait, Stop I

: All ports configured as inputs, V

= 0.2 Vdc, V

= V

�0.2 Vdc

Stop I

measured with OSC1 = V

4. Run and wait I

limit values are with no load on PD5 clockout, when PD5 is enabled.

Run and wait I

values are for both PD5 enabled and disabled and LVR enabled and disabled.

Characteristic

(1)

Symbol

Min

Max

Unit

Rise Time

Fall Time

Pulse Width

Load

Pullup

0.5

�

13 ns

2.4

�

59 pF

10 K

1.0

�

20 ns

2.7

�

100 pF

10 K

2.5

�

42 ns

3.7

�

250 pF

10 K

Note: V

= 4.5 Vdc, V

= 0 Vdc, T

= 125

�

NON-DISCLOSURE AGREEMENT REQUIRED

Electrical Specifications

Technical Data

MC68HC05P18A

120

Electrical Specifications

MOTOROLA

13.8 A/D Converter Characteristics

Characteristic

(1)

= 5.0

�

10% Vdc

�

10%, V

= 0 Vdc, T

�

C to +125

�

C, unless otherwise noted

Min

Max

Unit

Comments

Resolution

Bits

Absolute accuracy

REFH

> 4.5

+1 1/2

LSB

Including quantization

Conversion range

REFH

A/D accuracy may decrease
proportionately as V

REFH

reduced below 4.5 V.

Input leakage

AD0, AD1, AD2, AD3
V

REFH

--
--

+1
+1

�

Conversion time

(2)

(Includes sampling time)

2. t

= t

CYC

if clock source equals MCU

(Note 2)

Monotonicity

Inherent (within total error)

Zero input reading

External
Internal

00
00

01
03

Hex

= 0 V

Full-scale reading

Hex

= V

REFH

Sample time

(Note 3)

Input capacitance

Analog input voltage

REFH

Electrical Specifications

SIOP Timing

MC68HC05P18A

Technical Data

MOTOROLA

Electrical Specifications

121

NON-DISCLOSURE AGREEMENT REQUIRED

13.9 SIOP Timing

Figure 13-1. SIOP Timing Diagram

SDI

BIT 1 ... 6

BIT 7

BIT 0

SDO

BIT 0

BIT 1 ... 6

BIT 7

SCK

No.

Characteristic

(1)

Symbol

Min

Max

Unit

Operating frequency

(2)

Master
Slave

OP(

)

OP(

)

1
1

Cycle time

Master
Slave

CYC(m)

CYC(s)

4.0

4.0
4.0

CYC

SCK low time

CYC

238

SDO data valid time

200

SDO hold time

SDI setup time

100

SDI hold time

100

1. V

= 5.0 Vdc

�

10%, V

= 0 Vdc,

�

C to +125

�

C, unless otherwise noted

2. f

= f

OSC

�

2; t

CYC

= 1

�

Electrical Specifications

Control Timing

MC68HC05P18A

Technical Data

MOTOROLA

Electrical Specifications

123

NON-DISCLOSURE AGREEMENT REQUIRED

13.11 Control Timing

Characteristic

(1)

1. V

= 5.0 Vdc, V

= 0 Vdc, T

= �40

�

C to +125

�

C, unless otherwise noted

Symbol

Min

Max

Unit

Frequency of operation

Crystal option
External clock source

OSC

4.2
4.2

MHz

Internal operating frequency

Crystal (f

OSC

�

External clock (f

OSC

�

2.1
2.1

MHz

Cycle time

Low speed
High speed

CYC

476
238

Crystal oscillator startup time

OXON

100

Stop recovery startup time (crystal oscillator)

ILCH

100

RESET pulse width

1.5

CYC

Interrupt pulse width low (edge-triggered)

ILIH

125

Interrupt pulse period

(2)

2. The minimum period, t

ILIL

, should not be less than the number of cycles it takes to execute the interrupt service routine

plus 19 t

CYC

ILIL

Note 2

CYC

OSC1 pulse width

Low speed
High speed

, t

200
100

A/D on current stabilization time

ADON

100

�

RC oscillator stabilization time

RCON

5.0

�

MC68HC05P18A

Technical Data

MOTOROLA

Mechanical Specifications

125

NON-DISCLOSURE AGREEMENT REQUIRED

Technical Data -- MC68HC05P18A

Section 14. Mechanical Specifications

14.1 Contents

14.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

14.3

28-Pin Plastic Dual In-Line Package (Case #710) . . . . . . . . .126

14.4

28-Pin Small Outline Package (Case #751F) . . . . . . . . . . . . .126

14.2 Introduction

This section provides package dimension drawings for the 28-pin plastic
dual in-line (PDIP) or 28-pin small outline (SOIC) packages.

To make sure that you have the latest case outline specifications,
contact:

�

Local Motorola Sales Office

�

Motorola Mfax

�

Phone 602-244-6609

�

EMAIL rmfax0@email.sps.mot.com

�

Worldwide Web (wwweb) at http://design-net.com

Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.

NON-DISCLOSURE AGREEMENT REQUIRED

Mechanical Specifications

Technical Data

MC68HC05P18A

126

Mechanical Specifications

MOTOROLA

14.3 28-Pin Plastic Dual In-Line Package (Case #710)

14.4 28-Pin Small Outline Package (Case #751F)

0.100 BSC

0.600 BSC

2.54 BSC

15.24 BSC

MIN

MAX

MILLIMETERS

INCHES

DIM

36.45

13.72

3.94

0.36

1.02

1.65

0.20

2.92

�

0.51

37.21

14.22

5.08

0.56

1.52

2.16

0.38

3.43

�

1.02

1.435

0.540

0.155

0.014

0.040

0.065

0.008

0.115

�

0.020

1.465

0.560

0.200

0.022

0.060

0.085

0.015

0.135

�

0.040

NOTES:

1. POSITIONAL TOLERANCE OF LEADS (D),

SHALL BE WITHIN 0.25mm (0.010) AT

MAXIMUM MATERIAL CONDITION, IN

RELATION TO SEATING PLANE AND

EACH OTHER.

2. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

SEATING

PLANE

MIN

MAX

MILLIMETERS

INCHES

DIM

17.80

7.40

2.35

0.35

0.41

0.23

0.13

�

10.05

0.25

18.05

7.60

2.65

0.49

0.90

0.32

0.29

�

10.55

0.75

0.701

0.292

0.093

0.014

0.016

0.009

0.005

�

0.395

0.010

0.711

0.299

0.104

0.019

0.035

0.013

0.011

�

0.415

0.029

1.27 BSC

0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15

(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION.

ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.13

(0.005) TOTAL IN EXCESS OF D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

-A-

-B-

-T-

SEATING

PLANE

0.010 (0.25)

-T-

26X

28X

14X

X 45

�

0.010 (0.25)

T A

MC68HC05P18A

Technical Data

MOTOROLA

Ordering Information

127

NON-DISCLOSURE AGREEMENT REQUIRED

Technical Data -- MC68HC05P18A

Section 15. Ordering Information

15.1 Contents

15.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

15.3

MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

15.2 Introduction

This section contains instructions for ordering the MC68HC05P18A.

15.3 MC Order Numbers

Table 15-1

shows the MC order numbers for the available package

types.

Table 15-1. MC Order Numbers

MC Order Number

(1)

1. P = Plastic dual in-line package

DW = Small outline (wide body) package

Operating

Temperature Range

MC68HC05P18AP (standard)

�

C to 70

�

MC68HC05P18ADW (standard)

�

C to 70

�

MC68HC05P18ACP (extended)

�40

�

C to +85

�

MC68HC05P18ACDW (extended)

�40

�

C to +85

�

MC68HC05P18AMP (automotive)

�40

�

C to +125

�

MC68HC05P18AMDW (automotive)

�40

�

C to +125

�

MC68HC05P18A/D

� Motorola, Inc., 1999

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts.
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intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the
design or manufacture of the part. Motorola and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution, P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140

or 1-800-441-2447. Customer Focus Center, 1-800-521-6274

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协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: MC68HC05P18A

Document Outline

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: MC68HC05P18A

Document Outline

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: MC68HC05P18A