MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

REV 2

Motorola, Inc. 1997

1/97

Low Voltage Low Skew

CMOS PLL Clock Driver,

3-State

The MC88LV915T Clock Driver utilizes phaselocked loop technology

to lock its low skew outputs' frequency and phase onto an input reference
clock. It is designed to provide clock distribution for high performance
PC's and workstations.

The PLL allows the high current, low skew outputs to lock onto a single

clock input and distribute it with essentially zero delay to multiple
components on a board. The PLL also allows the MC88LV915T to
multiply a low frequency input clock and distribute it locally at a higher
(2X) system frequency. Multiple 88LV915's can lock onto a single
reference clock, which is ideal for applications when a central system
clock must be distributed synchronously to multiple boards (see Figure 4
on Page 9).

Five "Q" outputs (Q0Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180

phase shift) from the "Q" outputs. The 2X_Q output runs at twice the "Q" output frequency, while the Q/2 runs at 1/2 the "Q"
frequency.

The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 2 detail

the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the
"Q" outputs to the SYNC input are 2:1, 1:1, and 1:2.

The FREQ_SEL pin provides one bit programmable divideby in the feedback path of the PLL. It selects between divideby1

and divideby2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on
page 2). In most applications FREQ_SEL should be held high (

1). If a low frequency reference clock input is used, holding

FREQ_SEL low (

2) will allow the VCO to run in its optimal range (>20MHz).

In normal phaselocked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the

88LV915T in a static "test mode". In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment. The second SYNC input can be used as a test clock input to further simplify boardlevel testing
(see detailed description on page 11).

Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0Q4, Q5 and Q/2 into a high impedance state (3state). After the

OE/RST pin goes back high Q0Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC
input. Assuming PLL_EN is low, the outputs will remain reset until the 88LV915 sees a SYNC input pulse.

A lock indicator output (LOCK) will go high when the loop is in steadystate phase and frequency lock. The LOCK output will go

low if phaselock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88LV915 sees a
SYNC signal and full 5V VCC.

Features

Five Outputs (Q0Q4) with OutputOutput Skew < 500 ps each being phase and frequency locked to the SYNC input

The phase variation from parttopart between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD

specification, which defines the parttopart skew)

Input/Output phaselocked frequency ratios of 1:2, 1:1, and 2:1 are available

Input frequency range from 5MHz 2X_Q FMAX spec.

Additional outputs available at 2X and +2 the system "Q" frequency. Also a Q (180

phase shift) output available

All outputs have

36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs

are TTLlevel compatible.

88mA IOL/IOH specifications guarantee 50

transmission line switching on the incident edge

Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.

All outputs can go into high impedance (3state) for board test purposes

Lock Indicator (LOCK) accuracy indicates a phaselocked state

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.

MC88LV915T

LOW SKEW CMOS

PLL CLOCK DRIVER

MC88LV915T

MOTOROLA

TIMING SOLUTIONS

BR1333 -- Rev 6

PLL_EN

GND

VCC

GND

FREQ_SEL

LOCK

GND

VCC

GND

Q/2

RC1

GND(AN)

VCC(AN)

SYNC[1]

SYNC[0]

REF_SEL

FEEDBACK

2X_Q

OE/RST VCC

VCC

GND

Pinout: 28Lead PLCC (Top View)

Reference clock input
Reference clock input
Chooses reference between sync[0] & Sync[1]
Doubles VCO Internal Frequency (low)
Feedback input to phase detector
Input for external RC network
Clock output (locked to sync)
Inverse of clock output
2 x clock output (Q) frequency (synchronous)
Clock output(Q) frequency

2 (synchronous)

Indicates phase lock has been achieved (high when locked)
Output Enable/Asynchronous reset (active low)
Disables phaselock for low freq. testing
Power and ground pins (note pins 8, 10 are
"analog" supply pins for internal PLL only)

Input
Input
Input
Input
Input
Input

Output
Output
Output
Output
Output

Input
Input

1
1
1
1
1
1
5
1
1
1
1
1
1

PIN SUMMARY

SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Q(04)
Q5
2x_Q
Q/2
LOCK
OE/RST
PLL_EN
VCC,GND

Pin Name

Num

I/O

Function

FN SUFFIX

PLASTIC PLCC

CASE 77602

MC88LV915T

MOTOROLA

TIMING SOLUTIONS

BR1333 -- Rev 6

MAXIMUM RATINGS*

Symbol

Parameter

Limits

Unit

VCC, AVCC

DC Supply Voltage Referenced to GND

0.5 to 7.0

Vin

DC Input Voltage (Referenced to GND)

0.5 to VCC +0.5

Vout

DC Output Voltage (Referenced to GND)

0.5 to VCC +0.5

Iin

DC Input Current, Per Pin

Iout

DC Output Sink/Source Current, Per Pin

ICC

DC VCC or GND Current Per Output Pin

Tstg

Storage Temperature

65 to +150

* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating
Conditions.

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Limits

Unit

VCC

Supply Voltage

3.3

0.3

Vin

DC Input Voltage

0 to VCC

Vout

DC Output Voltage

0 to VCC

Ambient Operating Temperature

0 to 70

ESD

Static Discharge Voltage

> 1000

DC CHARACTERISTICS (TA = 0

C to 70

C; VCC = 3.3V

0.3V)

Symbol

Parameter

VCC

Guaranteed Limits

Unit

Condition

VIH

Minimum High Level Input Voltage

3.0
3.3

2.0
2.0

VOUT = 0.1V or
VCC 0.1V

VIL

Minimum Low Level Input Voltage

3.0
3.3

0.8
0.8

VOUT = 0.1V or
VCC 0.1V

VOH

Minimum High Level Output Voltage

3.0
3.3

2.4
2.7

VIN = VIH or VIL
IOH= 24mA

VOL

Minimum Low Level Output Voltage

3.0
3.3

0.44
0.44

VIN = VIH or VIL
IOH= 24mA

IIN

Maximum Input Leakage Current

3.6

1.0

VI = VCC, GND

ICCT

Maximum ICC/Input

3.6

2.0

VI = VCC 2.1V

IOLD

Minimum Dynamic3 Output Current

3.6

+50

VOLD = 1.25V

IOHD

3.6

VOHD =2.35V

ICC

Maximum Quiescent Supply Current

3.6

TBD

VI = VCC, GND

1. IOL is +12mA for the RST_OUT output.

2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration 2.0ms, one output loaded at a time.

SYNC INPUT TIMING REQUIREMENTS

Symbol

Parameter

Minimum

Maximum

Unit

tRISE/FALL
SYNC Input

Rise/Fall Time, SYNC Input
From 0.8V to 2.0V

5.0

tCYCLE,
SYNC Input

Input Clock Period
SYNC Input

f2X_Q 4

100

Duty Cycle

Duty Cycle, SYNC Input

50%

25%

MC88LV915T

TIMING SOLUTIONS
BR1333 -- Rev 6

MOTOROLA

FREQUENCY SPECIFICATIONS (TA = 0

C to 70

C; VCC = 3.3V

0.3V)

Symbol

Parameter

Guaranteed Minimum

Unit

Fmax (2X_Q)

Maximum Operating Frequency, 2X_Q Output

100

MHz

Fmax (`Q')

Maximum Operating Frequency,
Q0Q3 Outputs

MHz

NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phaselocked condition.

AC CHARACTERISTICS

(TA =0

C to +70

C, VCC = 3.3V

0.3V, Load = 50

Terminated to VCC/2)

Symbol

Parameter

Min

Max

Unit

Condition

tRISE/FALL
Outputs

Rise/Fall Time, All Outputs
(Between 0.8 to 2.0V)

0.5

2.0

Into a 50

Load

Terminated to VCC/2

tPULSE WIDTH
(Q0Q4, Q5, Q/2)

Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ VCC/2

0.5tCYCLE 0.5 1

0.5tCYCLE + 0.5 1

Into a 50

Load

Terminated to VCC/2

tPULSE WIDTH
(2X_Q Output)

Output Pulse Width:

40MHz

2X_Q @ 1.5V

66MHz
80MHz

100MHz

0.5tCYCLE 1.5
0.5tCYCLE 1.0
0.5tCYCLE 1.0
0.5tCYCLE 1.0

0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5

Into a 50

Load

Terminated to VCC/2

tCYCLE
(2x_Q Output)

CycletoCycle Variation

40MHz

2x_Q @ VCC/2

66MHz
80MHz

100MHz

tCYCLE 600ps
tCYCLE 300ps
tCYCLE 300ps
tCYCLE 400ps

tCYCLE + 600ps
tCYCLE + 300ps
tCYCLE + 300ps
tCYCLE + 400ps

tPD2
SYNC Feedback

(With 1M

from RC1 to An VCC)

SYNC Feedback

SYNC Input to Feedback Delay 66MHz
(Measured at SYNC0 or 1 and 80MHz
FEEDBACK Input Pins)

100MHz

1.65
1.45
1.25

1.05
0.85
0.65

tSKEWr3
(Rising) See Note 4

OutputtoOutput Skew Between Out-
puts Q0Q4, Q/2 (Rising Edges Only)

500

All Outputs Into a
Matched 50

Load

Terminated to VCC/2

tSKEWf3
(Falling)

OutputtoOutput Skew Between Out-
puts Q0Q4 (Falling Edges Only)

750

All Outputs Into a
Matched 50

Load

Terminated to VCC/2

tSKEWall3

OutputtoOutput Skew 2X_Q, Q/2,
Q0Q4 Rising, Q5 Falling

750

All Outputs Into a
Matched 50

Load

Terminated to VCC/2

tLOCK4

Time Required to Acquire PhaseLock
From Time SYNC Input Signal is
Received

1.0

Also Time to LOCK
Indicator High

tPZL5

Output Enable Time OE/RST to 2X_Q,
Q0Q4, Q5, and Q/2

3.0

Measured With the
PLL_EN Pin Low

tPHZ,tPLZ5

Output Disable Time OE/RST to 2X_Q,
Q0Q4, Q5, and Q/2

3.0

Measured With the
PLL_EN Pin Low

1. TCYCLE in this spec is 1/Frequency at which the particular output is running.

2. The TPD specification's min/max values may shift closer to zero if a larger pullup resistor is used.

3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With VCC fully poweredon, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1

F, tLOCK minimum is

with C1 = 0.01

5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when `MC' status is

reached.

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