TL F 5861
DP8480A
10k
ECL
to
TTL
Level
Translator
with
Latch
April 1990
DP8480A 10k ECL to TTL Level Translator with Latch
General Description
This circuit translates ECL input levels to TTL output levels
and provides a fall-through latch The TRI-STATE
outputs
are designed to drive standard 50 pF loads The strobe and
chip select inputs operate at ECL levels
Features
Y
16-pin DIP
Y
TRI-STATE outputs
Y
ECL control inputs
Y
8 ns typical propagation delay with 50 pF load
Y
Outputs are TRI-STATE during power up down for
glitch free operation
Y
10k ECL input compatible
Logic and Connection Diagram
Dual-In-Line Package
TL F 5861 1
Top View
Truth Table
D
Q
STR
CS
H
L
L
L
L
H
L
L
X
Q
H
L
X
Hi-Z
X
H
H
e
high level (most positive)
L
e
low level (most negative)
X
e
don't care
Order Number DP8480AJ or DP8480AN
See NS Package Number J16A or N16A
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
V
EE
Supply Voltage
b
8V
V
CC
Supply Voltage
7V
Input Voltage
GND to V
EE
Output Voltage
5 5V
Maximum Power Dissipation at 25 C
Molded Package
1476 mW
Storage Temperature
b
65 C to
a
150 C
Derate molded package 11 8 mW C above 25 C
Recommended Operating
Conditions
V
EE
Supply Voltage
b
5 2V
g
10%
V
CC
Supply Voltage
5 0V
g
10%
T
A
Ambient Temperature
0 C to 75 C
Electrical Characteristics
(TTL Logic) Notes 2 3 and 4
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
OL
Output Low Voltage
I
OL
e
12 mA
0 5
V
V
OH
Output High Voltage
I
OH
e b
10 mA
V
CC
b
2V
V
I
AV
Output Low Drive Current
Force 2 5V
70
150
mA
I
OS
Output High Drive Current
Force 0V
b
70
b
150
b
350
mA
I
OZ
TRI STATE Output Current
b
50
1
a
50
m
A
I
CC
Supply Current
35
mA
Electrical Characteristics
(ECL Logic) Notes 2 and 3
Symbol
Parameter
Conditions
T
A
Min
Typ
Max
Units
V
IL
Input Low Voltage
V
EE
e b
5 2V
0 C
b
1870
b
1490
25 C
b
1850
b
1475
mV
75 C
b
1830
b
1450
V
IH
Input High Voltage
V
EE
e b
5 2V
0 C
b
1145
b
840
25 C
b
1105
b
810
mV
75 C
b
1045
b
720
I
IL
Input Low Current
V
IN
e
V
IL
Max
50
125
m
A
I
IH
Input High Current
V
IN
e
V
IH
Max
75
750
m
A
I
EE
Supply Current
b
55
mA
Switching Characteristics
Notes 2 and 5
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PD1
Strobe to Output Delay
C
L
e
50 pF
4
9
15
ns
t
PD2
Data to Output Delay
C
L
e
50 pF
3 5
8
15
ns
t
S
Data Set-Up Time
(Note 6)
3 0
1 0
ns
t
H
Data Hold Time
(Note 6)
3 0
1 0
ns
t
PW
Strobe Pulse Width
(Note 6)
5 0
3 0
ns
t
ZE
Delay from Chip Select to
C
L
e
50 pF
6
15
25
ns
Active State from Hi Z State
t
EZ
Delay from Chip Select to Hi Z
C
L
e
50 pF
4 5
12
22
ns
State from Active State
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the device
should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device operation
Note 2
Unless otherwise specified min max limits apply across the 0 C to 75 C ambient temperature range in still air and across the specified supply variations
All typical values are for T
A
e
25 C and nominal supply Maximum propagation delays are specified with all outputs switching simultaneously
Note 3
All currents into device pins are shown as positive all currents out of device pins are shown as negative All voltages are referenced to ground unless
otherwise specified
Note 4
When DC testing I
AV
or I
OS
only one output should be tested at a time and the current limited to 120 MA max
Note 5
Unless otherwise specified all AC measurements are referenced from the 50% level of the ECL input to the 0 8V level on negative transitions or the 2 4V
level on positive transitions of the output ECL input rise and fall times are 2 0 ns
g
0 2 ns from 20% to 80%
Note 6
Caution should be used when latching data while the outputs are switching TTL outputs generate severe ground noise when switching This noise can be
sufficient to cause the ECL latch to loose data Board mounting and good supply decoupling are desirable The worst case conductions are with all outputs
switching low simultaneously the maximum capacitive loading on the outputs and the maximum V
CC
supply voltage applied
2
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