LM5035
PWM Controller with Integrated Half-Bridge and
SyncFET Drivers
General Description
The LM5035 Half-Bridge Controller/Gate Driver contains all
of the features necessary to implement half-bridge topology
power converters using voltage mode control with line volt-
age feed-forward. The floating high-side gate driver is ca-
pable of operating with supply voltages up to 105V. Both the
high-side and low-side gate drivers are capable of 2A peak.
An internal high voltage startup regulator is included, along
with programmable line undervoltage lockout (UVLO) and
overvoltage protection (OVP). The oscillator is programmed
with a single resistor to frequencies up to 2MHz. The oscil-
lator can also be synchronized to an external clock. A current
sense input and a programmable timer provide cycle-by-
cycle current limit and adjustable hiccup mode overload
protection.
Features
n
105V / 2A Half-Bridge Gate Drivers
n
Synchronous Rectifier Control Outputs with
Programmable Delays
n
High Voltage (105V) Start-up Regulator
n
Voltage mode Control with Line Feed-Forward and Volt
Second Limiting
n
Resistor Programmed, 2MHz Capable Oscillator
n
Patent Pending Oscillator Synchronization
n
Programmable Line Under-Voltage Lockout
n
Line Over-Voltage Protection
n
Internal Thermal Shutdown Protection
n
Adjustable Soft-Start
n
Versatile Dual Mode Over-Current Protection with
Hiccup Delay Timer
n
Cycle-by-Cycle Over-Current Protection
n
Direct Opto-coupler Interface
n
5V Reference Output
Packages
n
TSSOP-20EP (Thermally enhanced)
n
LLP-24 (4mm x 5mm)
Simplified Application Diagram
20177501
January 2006
LM5035
PWM
Controller
with
Integrated
Half-Bridge
and
SyncFET
Drivers
2006 National Semiconductor Corporation
DS201775
www.national.com
Connection Diagrams
Top View
20177502
20-Lead TSSOP EP
Top View
20177503
LLP-24 Package
LM5035
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Ordering Information
Order Number
Package Type
NSC Package Drawing
Supplied As
LM5035MH
TSSOP-20EP
MXA20A
73 Units per Rail
LM5035MHX
TSSOP-20EP
MXA20A
2500 Units on Tape and Reel
LM5035SQ
LLP-24
SQA24B
Available Soon
LM5035SQX
LLP-24
SQA24B
Available Soon
Pin Descriptions
TSSOP
PIN
LLP
PIN
Name
Description
Application Information
1
23
RAMP
Modulator ramp signal
An external RC circuit from VIN sets the ramp slope. This pin
is discharged at the conclusion of every cycle by an internal
FET. Discharge is initiated by either the internal clock or the
Volt
Second clamp comparator.
2
24
UVLO
Line Under-Voltage Lockout
An external voltage divider from the power source sets the
shutdown and standby comparator levels. When UVLO
reaches the 0.4V threshold the VCC and REF regulators are
enabled. When UVLO reaches the 1.25V threshold, the SS pin
is released and the device enters the active mode. Hysteresis
is set by an internal current sink that pulls 23A from the
external resistor divider.
3
2
OVP
Line Over-Voltage Protection
An external voltage divider from the power source sets the
shutdown levels. The threshold is 1.25V. Hysteresis is set by
an internal current source that sources 23A into the external
resistor divider.
4
3
COMP
Input to the Pulse Width
Modulator
An external opto-coupler connected to the COMP pin sources
current into an internal NPN current mirror. The PWM duty
cycle is maximum with zero input current, while 1mA reduces
the duty cycle to zero. The current mirror improves the
frequency response by reducing the AC voltage across the
opto-coupler detector.
5
4
RT
Oscillator Frequency Control and
Sync Clock Input.
Normally biased at 2V. An external resistor connected between
RT and AGND sets the internal oscillator frequency. The
internal oscillator can be synchronized to an external clock with
a frequency higher than the free running frequency set by the
RT resistor.
6
5
AGND
Analog Ground
Connect directly to Power Ground.
7
6
CS
Current Sense input for current
limit
If CS exceeds 0.25V the output pulse will be terminated,
entering cycle-by-cycle current limit. An internal switch holds
CS low for 50ns after HO or LO switches high to blank leading
edge transients.
8
7
SS
Soft-start Input
An internal 55 A current source charges an external capacitor
to set the soft-start rate. During a current limit restart
sequence, the internal current source is reduced to 1.2A to
increase the delay before retry.
9
8
DLY
Timing programming pin for the
LO and HO to SR1 and SR2
outputs.
An external resistor to ground sets the timing for the
non-overlap time of HO to SR1 and LO to SR2.
LM5035
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Pin Descriptions
(Continued)
TSSOP
PIN
LLP
PIN
Name
Description
Application Information
10
9
RES
Restart Timer
If cycle-by-cycle current limit is exceeded during any cycle, a
22A current is sourced to the RES pin capacitor. If the RES
capacitor voltage reaches 2.5V, the soft-start capacitor will be
fully discharged and then released with a pull-up current of
1.2A. After the first output pulse at LO (when SS
>
COMP
offset, typically 1V), the SS pin charging current will revert to
55A.
11
11
HB
Boost voltage for the HO driver
An external diode is required from VCC to HB and an external
capacitor is required from HS to HB to power the HO gate
driver.
12
12
HS
Switch node
Connection common to the transformer and both power
switches. Provides a return path for the HO gate driver.
13
13
HO
High side gate drive output.
Output of the high side PWM gate driver. Capable of sinking
2A peak current.
14
14
LO
Low side gate drive output.
Output of the low side PWM gate driver. Capable of sinking 2A
peak current.
15
15
PGND
Power Ground
Connect directly to Analog Ground.
16
16
VCC
Output of the high voltage
start-up regulator. The VCC
voltage is regulated to 7.6V.
If an auxiliary winding raises the voltage on this pin above the
regulation setpoint, the Start-up Regulator will shutdown, thus
reducing the internal power dissipation.
17
17
SR2
Synchronous rectifier driver
output.
Control output of the synchronous FET gate. Capable of 0.5A
peak current.
18
18
SR1
Synchronous rectifier driver
output.
Control output of the synchronous FET gate. Capable of 0.5A
peak current.
19
19
REF
Output of 5V Reference
Maximum output current is 20mA. Locally decoupled with a
0.1F capacitor.
20
21
VIN
Input voltage source
Input to the Start-up Regulator. Operating input range is 13V to
100V with transient capability to 105V. For power sources
outside of this range, the LM5035 can be biased directly at
VCC by an external regulator.
EP
EP
EP
Exposed Pad, underside of
package
No electrical contact. Connect to system ground plane for
reduced thermal resistance.
1
NC
No connection
No electrical contact.
10
NC
No connection
No electrical contact.
20
NC
No connection
No electrical contact.
22
NC
No connection
No electrical contact.
LM5035
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN to GND
-0.3V to 105V
HS to GND
-1V to 105V
HB to GND
-0.3V to 118V
HB to HS
-0.3V to 18V
VCC to GND
-0.3V to 16V
CS, RT, DLY to GND
-0.3V to 5.5V
COMP Input Current
10mA
All other inputs to GND
-0.3V to 7V
ESD Rating (Note 4)
Human Body Model
2kV
Storage Temperature Range
-65C to 150C
Junction Temperature
150C
Operating Ratings
(Note 1)
VIN Voltage
13V to 105V
External Voltage Applied to VCC
8V to 15V
Operating Junction Temperature
-40C to +125C
Electrical Characteristics
Specifications with standard typeface are for T
J
= 25C, and those with boldface
type apply over full Operating Junction Temperature range. V
VIN
= 48V, V
VCC
= 10V externally applied, R
RT
= 15.0 k
,
R
DLY
= 27.4k
, V
UVLO
= 3V, V
OVP
= 0V unless otherwise stated. See (Note 2) and (Note 3).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Startup Regulator (VCC pin)
V
VCC
VCC voltage
I
VCC
= 10mA
7.3
7.6
7.9
V
I
VCC(LIM)
VCC current limit
V
VCC
= 7V
20
25
mA
V
VCCUV
VCC Under-voltage threshold
(VCC increasing)
VIN = VCC,
V
VCC
from the regulation
setpoint
0.2
0.1
V
VCC decreasing
VCC PGND
5.5
6.2
6.9
V
I
VIN
Startup regulator current
VIN = 90V, UVLO = 0V
30
70
A
Supply current into VCC from
external source
Outputs & COMP open, V
VCC
= 10V,
Outputs Switching
4
6
mA
Voltage Reference Regulator (REF pin)
V
REF
REF Voltage
I
REF
= 0mA
4.85
5
5.15
V
REF Voltage Regulation
I
REF
= 0 to 10mA
25
50
mV
REF Current Limit
REF = 4.5V
15
20
mA
Under-Voltage Lock Out and shutdown (UVLO pin)
V
UVLO
Under-voltage threshold
1.212
1.25
1.288
V
I
UVLO
Hysteresis current
UVLO pin sinking
19
23
27
A
Under-voltage Shutdown Threshold UVLO voltage falling
0.3
V
Under-voltage Standby Enable
Threshold
UVLO voltage rising
0.4
V
Over-Voltage Protection (OVP pin)
V
OVP
Over-Voltage threshold
1.212
1.25
1.288
V
I
OVP
Hysteresis current
OVP pin sourcing
19
23
27
A
Current Sense Input (CS Pin)
V
CS
Current Limit Threshold
0.228
0.25
0.272
V
CS delay to output
CS from zero to 1V. Time for HO and LO
to fall to 90% of VCC. Output load = 0
pF.
80
ns
Leading edge blanking time at CS
50
ns
CS sink impedance (clocked)
Internal FET sink impedance
32
60
Current Limit Restart (RES Pin)
V
RES
RES Threshold
2.4
2.5
2.6
V
Charge source current
V
RES
= 1.5V
16
22
28
A
Discharge sink current
V
RES
= 1V
8
12
16
A
LM5035
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