ML674K Series
ML674001/ML67Q4002/ML67Q4003
32-Bit ARM
-Based General Purpose Microcontrollers
Description
Oki Semiconductor's ML674001, ML67Q4002, and ML67Q4003 standard microcontrollers (MCUs) are the newest
members of an extensive and growing family of ARM
architecture 32-bit MCUs for general-purpose applications that
can utilize 32-bit CPU performance and the low cost afforded by the integrated features of an MCU.
Oki's newest Family members provide on-board SRAM (32 kBytes), boot ROM (4 kBytes) and a host of other useful
peripherals such as timers, watchdog timer, pulse-width modulators, AD converter, UARTs, I2C serial interface, GPIO
pins, external memory controller, and boundary scan capability. In addition, the ML67Q4002 and ML67Q4003 offer
256 kBytes and 512 kBytes of built-in Flash ROM, respectively. The ML674001, ML67Q4002, and ML67Q4003 are
pin-to-pin compatible with each other for easy performance upgrades.
The ARM7TDMI
Advantage
Oki Semiconductor's Family of low-cost ARM-based MCUs offers system designers a bridge from 8- and 16-bit propri-
etary MCU architectures to ARM's 32-bit industry standard architecture with no price premium. The ARM industry-wide
support infrastructure offers system developers many advantages including software compatibility, many ready-to-use
software applications, and a large choice among hardware and software development tools to better leverage engi-
neering resources, lower development costs, minimize project risks, and reduce their product time to market.
In addition, migration of a design with an Oki standard MCU to an Oki custom solution is easily facilitated with its
award-winning PLATTM product development architecture.
Features
ARM7TDMI 32-bit RISC CPU
- 16-bit ThumbTM instruction set for power efficiency
applications
32-bit mode (ARM) and/or 16-bit mode (Thumb)
Built-in external memory controller supports glue-
less connectivity to memory (including SDRAM and
EDO DRAM) and I/O
Built in Flash ROM
- 256 KB (ML67Q4002)
- 512 KB (ML67Q4003)
32-KBytes built in zero-wait-state SRAM
28 interrupt sources
DMA: 2 channels with external access
Timers: 7 16-bit timers
Watch-Dog Timer: dual stage 16 bit
PWM: Two 16-bit channels
Serial Interfaces: SIO, UART, USART, I2C
GPIO: 42 bits
A/D Converter: Four 10-bit channels
Built-in boot ROM accommodates in-circuit Flash
ROM re-programming and field-updates
Package
- 144-pin plastic LQFP
- 144-pin plastic LFBGA
Applications
Flexible solution for various cost-effective, power-
sensitive embedded real-time control applications
Security / Surveillance, Telecom, Industrial Control,
Electronic Peripherals, and Consumers Electronics
embedded applications
ML674001/Q4002/Q4003 MCUs
Part Number
Clock Frequency
Built-in Flash Size
Packages
ML674001
33 MHz
n/a
144-pin plastic LQFP (ML674001TC)
144-pin plastic LFBGA (ML674001LA)
ML67Q4002
33 MHz
256 KB
144-pin plastic LQFP (ML67Q4002TC)
144-pin plastic LFBGA (ML67Q4002LA)
ML67Q4003
33 MHz
512 KB
144-pin plastic LQFP (ML67Q4003TC)
144-pin plastic LFBGA (ML67Q4003LA)
ML674001/ML67Q4002/ML67Q4003
2
Oki Semiconductor
Block Diagram
ARM7TDMI
AHB Bridge
APB Bridge
Internal & External
Memory Controller
TIC
System
TIMER
UART
System
Controller
IRC
AMBA
AHB Bus
AMBA
APB Bus
PLAT-7B
Internal RAM
32KB
DRAMC
Exp. IRC
Internal (MCP)
FLASH ROM
ML67Q4002: 256KB
ML67Q4003: 512KB
Boot ROM
4KB
DMAC
TIMER
16 bit x 6ch
PWM
16 bit x 2ch
WDT
UART
(16550)
SSIO
I2C
A/D
GPIO
APB Bridge
RESET_N
PIOB[6] / STXD
PIOB[7] / SRXD
OSC0
OSC1_N
CKOE_N
CKO
PIOE[8:5] / EXINT[3:0]
PIOE[9] / EFIQ_N
CGB
VDD_CORE
VDD_IO
GND
AVDD
AGND
DRAME_N
TEST
BSEL[1:0]
FWR
JSEL
PIOA[7:0]
PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
PIOE[9:0]
AIN[3:0]
VREF
PIOE[3] / SDA
PIOE[4] / SCL
PIOE[0] / SDO
PIOE[1] / SDI
PIOE[2] / SCLK
PIOA[0] / SIN
PIOA[1] / SOUT
PIOA[2] / CTS
PIOA[3] / DSR
PIOA[4] / DCD
PIOA[5] / DTR
PIOA[6] / RTS
PIOA[7] / RI
PIOC[1:0] / PWMOUT[1:0]
PIOB[5:4] / TCOUT[1:0]
PIOB[1] / DREQCLR[0]
PIOB[3] / DREQCLR[1]
PIOB[0] / DREQ[0]
PIOB[2] / DREQ[1]
PIOC[6:2] / XA[23:19]
XA[18:0]
XD[15:0]
PIOC[7] / XWR
XOE_N
XWE_N
XBWE_N[1:0]
XROMCS_N
XRAMCS_N
XIOCS_N[3:0]
XBS_N[1:0]
PIOD[0] / XWAIT
PIOD[1] / XCAS_N
PIOD[2] / XRAS_N
PIOD[3] / XSDCLK
PIOD[4] / XSDCS_N
PIOD[5] / XSDCKE
PIOD[6] / XDQM[1] / XCAS_N[1]
PIOD[7] / XDQM[0] / XCAS_N[0]
TDI
TDO
nTRST
TMS
TCK
5
5
8
5
2
3
42
2
2
2
2
APB Bus
Flash Control
Oki Semiconductor 3
ML674001/ML67Q4002/ML67Q4003
Functional Description
CPU
Built-in Memory
Interrupt Controller
Fast interrupt request (FIQ) and interrupt request (IRQ) are employed as inter-
rupt input signals. The interrupt controller controls these interrupt signals
going to ARM core.
1. Interrupt sources
- FIQ: 1 external source (external pin: EFIQ_N)
- IRQ: Total of 27 sources. 23 internal sources, and 4 external sources
(EXINT[3:0])
2. Interrupt priority level
- Configurable, 8-level priority for each source
3. External interrupt pin input
- Can be set as Level or Edge sensing
- Configurable as Rising or Falling edge triggering when set to Edge
sensitive
Timer
Seven channels of 16-bit reload timers are employed. Of these, 1 channel is
used as system timer for OS.
The timers of other 6 channels are used in application software.
1. System timer: 1 channel
- 16-bit auto reload timer: Used as system timer for OS
2. Application timer: 6 channels
- 16-bit auto reload timer
- One shot, interval
- Clock can be independently set for each channel
Watch Dog Timer
Functions as an interval timer or a watch dog timer.
16-bit timer
Watch dog timer or interval timer mode can be selected
Interrupt reset generation
Maximum period: longer than 200 msec
Serial Interface
This MCU contains four serial interfaces.
1. UART without FIFO: 1 channel
This is the serial port which performs data transmission, taking a synchro-
nization per character.
Selection of various parameters, such as addition of data length, a stop
bit, and a parity bit, is possible.
- Asynchronous full duplex operation
- Sampling Rate = Baud rate x 16 samples
- Character Length: 7, 8 bit
- Stop Bit Length: 1, 2 bit
- Parity: Even, Odd, none
- Error Detection: Parity, Framing, Over run
- Loop Back Function: ON/OFF, Parity, framing, Over run Compulsive
addition
- Built-in Baud Rate Generator (8-bit counter) - Independent from a bus
clock
- Internal-Baud-Rate-Clock-Stop at the Time of HALT Mode.
2. UART with 16byte FIFO: 1 channel
Features 16 byte FIFO in both send and receive. Uses the industry standard
16550A ACE (Asynchronous Communication Element).
- Asynchronous full duplex operation
- Reporting function for all status
- 16 Byte Transmit FIFO
- 16 Byte Receive FIFO
- Transmission, reception, interrupt of line status Data set and Indepen-
dent FIFO control.
- Modem control signals: CTS, DCD, DSR, DTR, RI and RTS
- Data length: 5, 6, 7, or 8 bits
- Stop bit length: 1, 1.5, or 2 bits
- parity: Even, Odd, or none
- Error Detection: Parity, Framing, Overrun
- Built-in Baud Rate Generation
3. Synchronous serial interface: 1 channel
Clock-synchronous 8 bit serial port
- selectable 1/8, 1/16 or 1/32 of the system clock frequency.
- LSB First or MSB First.
- Master / Slave Mode
- Transceiver buffer empty interrupt
- Loopback Test Function
4. I2C: 1channel
Based on the I2C Bus specification. Operates as a single master device.
- Communication mode: Master transmitter /master receiver
- Transmission Speed: 100 kbps (Standard mode) / 400 kbps (Fast mode)
- Addressing format: 7 bit / 10 bit
- Data buffer: 1 Byte (1step)
- Communication Voltage: 2.7V to 3.3V
CPU core:
ARM7TDMI
Operating
frequency:
1 MHz to 33 MHz (max)
Instructions:
ARM instruction (32-bit length) and Thumb instruction
(16-bit length) can be mixed
General register
bank:
31 x 32 bits
Built-in barrel
shifter:
ALU and barrel shift operations can be executed by one
instruction.
Multiplier:
32 bits x 8 bits (Modified Booth Algorithm)
Built-in debug
function:
JTAG interface, break point register
Addressing:
Little Endian
FLASH ROM:
ML674001 is the ROM-less version
ML67Q4002: 256Kbytes (128K x 16 bits)
ML67Q4003: 512Kbytes (256K x 16 bits)
SRAM:
32KB (8K x 32bits)
Connected to processor bus (single cycle read)
Boot ROM
4KB (1K x 32 bits)
Used for programming internal flash.
ML674001/ML67Q4002/ML67Q4003
4
Oki Semiconductor
GPIO
42-bit parallel port (four 8-bit ports and one 10-bit port).
Direct Memory Access Controller
Two-channel direct memory access controller (DMAC) which transfers data
between memory and memory, between I/O and memory, and between I/O
and I/O.
Pulse Width Modulation
This MCU contains two channels of Pulse Width Modulation (PWM) function
which can change the duty cycle of a waveform with a constant period. The
PWM output resolution is 16 bits for each channel.
A/D Converter
Successive approximation type A/D converter.
1. 10 bits x 4 channels
2. Sample and hold function
3. Scan mode and select mode are supported
4. Interrupt is generated after completion of conversion.
5. Conversion time: 5 s (min).
External Memory Controller
Controls access of externally connected devices such as ROM (FLASH), SRAM,
SDRAM (EDO DRAM) and I/O devices.
1. ROM (FLASH) access function: 1 bank (supports up to 16 MBytes)
Supports 16-bit devices
Supports FLASH memory: Byte write (can be written only by IF equivalent
to SRAM).
Configurable access timing.
2. SRAM access function : 1 bank (supports up to 16 MBytes)
Supports 16-bit devices
Supports asynchronous SRAM
Configurable access timing.
3. DRAM access function : 1 bank (supports up to 64 MBytes)
Supports 16-bit devices
Supports EDO-DRAM/SDRAM: Simultaneous connections to EDO-DRAM
and SDRAM cannot be made.
Configurable access timing.
4. External I/O access function: 4 banks
Supports 8-bit/16-bit access: Independent configuration for each pair of
banks. Each bank has its own chip select: XIOCS_N[3:0].
Supports external wait input: XWAIT (XIOCS_N[1:0] only)
Access timing configurable for each pair of banks independently.
Power Management
HALT and STANDBY functions are supported as power save functions.
1. HALT mode (Clock stop by each function block)
HALT object
- CPU, internal RAM, AHB bus control
HALT mode setting: Set by the system control register.
Exit HALT mode due to: Reset, interrupt
2. STANDBY mode
Stops the clock for the entire device.
STANDBY mode setting: Specified by the system control register.
Exit STANDBY mode due to: Reset, external interrupt (other than EFIQ_N)
3. Clock gear (selectable 1/1, 1/2, 1/4, 1/8, 1/16 input clock frequency)
PIOA[7:0]
PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
PIOE[9:0]
Combination port
Combination port
Combination port
Combination port
Combination port
UART
DMAC, UART
PWM, XA[23:19], XWR
DRAM control signals etc.
SSIO, I2C, External interrupt signal
1. Input/output selectable at bit level.
2. Each bit can be used as an interrupt source.
3. Interrupt mask and interrupt priority can be set for all bits.
4. The ports are configured as input, immediately after reset.
5. Primary/secondary function of each port can be set independently.
1. Number of
channels:
2 channels
2. Channel priority
level:
Fixed mode:
Channel priority level is always
fixed (channel 0 >1).
Roundrobin:
Priority level of the channel
requested for transfer is kept
lowest.
3. Maximum number
of transfers:
65,536 per DMA operation.
4. Data transfer size: Byte (8 bits), Half-word (16 bits), Word (32 bits)
5. Bus request
system:
Cycle steal
mode:
Bus request signal is asserted for
each DMA transfer cycle.
Burst mode:
Bus request signal is asserted until
all transfers of transfer cycles are
complete.
6. DMA transfer
request:
Software
request:
By setting the software transfer
request bit inside the DMAC, the
CPU starts DMA transfer.
External
request:
DMA transfer is started by exter-
nal request allocated to each
channel.
7. Interrupt request:
Interrupt request is generated in CPU after the end
of DMA transfer for the set number of transfer
cycles, or after the occurrence of an error.
Interrupt request signal is output separately for
each channel.
Interrupt request signal output can be masked for
each channel.
Oki Semiconductor 5
ML674001/ML67Q4002/ML67Q4003
Built-In Flash ROM Programming
The robust features of the flash permit simple and optimized programming of
the flash-ROM.
1. There are three methods for programming the FLASH-ROM
- Programming via the JTAG interface
- Programming using boot mode
Boot mode is used by the host to download data to the FLASH ROM via
the UART interface.
A program stored in the on-chip boot ROM is used to transfer the
incoming serial data on the UART interface to the internal Flash ROM.
- Programming via a user application running from external memory
Internal flash can be programmed by executing a user flash program-
ming application from external memory.
2. Single power source for reading and programming of FLASH: 3.0V to
3.6V
3. Programming units: 2 bytes
4. Selectable erasing size
- Sector erase: 2 Kbytes/sector
- Block erase: 64 Kbytes/block
- Chip erase: All memory cell
5. Word program time: 30 sec
6. Sector/block erase time: 25 msec
7. Chip erase time: 100 msec
8. Write protection
- Block protect: top address 8Kwords can be protected
- Chip protect: all words can be protected
9. Number of commands: 9
10. Highly reliable read/program
- Sector programming: 10000 times
- Data hold period: 10 years
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