Semiconductor Components Industries, LLC, 2003
March, 2003 - Rev. 3
1
Publication Order Number:
MC74HC4060A/D
MC74HC4060A
14-Stage Binary Ripple
Counter With Oscillator
High-Performance Silicon-Gate CMOS
The MC74C4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 14 master-slave flip-flops and an oscillator
with a frequency that is controlled either by a crystal or by an RC
circuit connected externally. The output of each flip-flop feeds the
next and the frequency at each output is half of that of the preceding
one. The state of the counter advances on the negative-going edge of
the Osc In. The active-high Reset is asynchronous and disables the
oscillator to allow very low power consumption during stand-by
operation.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With JEDEC Standard No. 7A Requirements
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
15
16
14
13
12
11
10
2
1
3
4
5
6
7
V
CC
9
8
Q10
Q8
Q9
Reset Osc In
Osc
Out 1
Osc
Out 2
Q12
Q13
Q14
Q6
Q5
Q7
Q4
GND
Pinout: 16-Lead Plastic Package (Top View)
FUNCTION TABLE
Clock
Reset
Output State
X
L
L
H
No Change
Advance to Next State
All Outputs Are Low
SO-16
D SUFFIX
CASE 751B
TSSOP-16
DT SUFFIX
CASE 948F
1
16
PDIP-16
N SUFFIX
CASE 648
1
16
1
16
MARKING
DIAGRAMS
1
16
MC74HC4060AN
AWLYYWW
1
16
HC4060A
AWLYWW
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
HC40
60A
ALYW
1
16
Device
Package
Shipping
ORDERING INFORMATION
MC74HC4060AN
PDIP-16
2000 / Box
MC74HC4060AD
SOIC-16
48 / Rail
MC74HC4060ADR2
SOIC-16
2500 / Reel
MC74HC4060ADT
TSSOP-16
96 / Rail
MC74HC4060ADTR2
TSSOP-16
2500 / Reel
LOGIC DIAGRAM
Q4
7
Q5
5
Q6
4
Q7
6
Q8
14
Q9
13
Q10
15
Q12
1
Q13
2
Q14
3
Osc In
11
Reset
12
Pin 16 = V
CC
Pin 8 = GND
Osc Out 1 Osc Out 2
9
10
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MC74HC4060A
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2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
0.5 to V
CC
+ 0.5
V
V
out
DC Output Voltage (Referenced to GND)
0.5 to V
CC
+ 0.5
V
I
in
DC Input Current, per Pin
20
mA
I
out
DC Output Current, per Pin
25
mA
I
CC
DC Supply Current, V
CC
and GND Pins
50
mA
P
D
Power Dissipation in Still Air,
Plastic DIP
SOIC Package
TSSOP Package
750
500
450
mW
T
stg
Storage Temperature Range
65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: - 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High- Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.5*
6.0
V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature Range, All Package Types
55
+ 125
_
C
t
r
, t
f
Input Rise/Fall Time
V
CC
= 2.0 V
(Figure 1)
V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
*The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested
at 2.0 V by driving Pin 11 with an external clock source.
DC CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Condition
V
CC
V
-55 to 25
C
85
C
125
C
Unit
V
IH
Minimum High-Level Input
Voltage
V
out
= 0.1V or V
CC
-0.1V
|I
out
|
20
A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
V
IL
Maximum Low-Level Input
Voltage
V
out
= 0.1V or V
CC
- 0.1V
|I
out
|
20
A
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
OH
Minimum High-Level Output
Voltage (Q4-Q10, Q12-Q14)
V
in
= V
IH
or V
IL
|I
out
|
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
=V
IH
or V
IL
|I
out
|
2.4mA
|I
out
|
4.0mA
|I
out
|
5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HC4060A
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3
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
Unit
Guaranteed Limit
V
CC
V
Condition
Parameter
Symbol
Unit
125
C
85
C
-55 to 25
C
V
CC
V
Condition
Parameter
V
OL
Maximum Low-Level Output
Voltage (Q4-Q10, Q12-Q14)
V
in
= V
IH
or V
IL
|I
out
|
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
|
2.4mA
|I
out
|
4.0mA
|I
out
|
5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
V
OH
Minimum High-Level Output
Voltage (Osc Out 1, Osc Out 2)
V
in
= V
CC
or GND
|I
out
|
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
=V
CC
or GND
|I
out
|
0.7mA
|I
out
|
1.0mA
|I
out
|
1.3mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low-Level Output
Voltage (Osc Out 1, Osc Out 2)
V
in
= V
CC
or GND
|I
out
|
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
=V
CC
or GND
|I
out
|
0.7mA
|I
out
|
1.0mA
|I
out
|
1.3mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current
V
in
= V
CC
or GND
6.0
0.1
1.0
1.0
A
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0
A
6.0
4
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High- Speed CMOS Data Book
(DL129/D).
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
CC
V
-55 to 25
C
85
C
125
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
10
30
50
9.0
14
28
45
8.0
12
25
40
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)
2.0
3.0
4.5
6.0
300
180
60
51
375
200
75
64
450
250
90
75
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)
2.0
3.0
4.5
6.0
500
350
250
200
750
450
275
220
1000
600
300
250
ns
t
PHL
Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
195
75
39
33
245
100
49
42
300
125
61
53
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)
2.0
3.0
4.5
6.0
75
60
15
13
95
75
19
16
125
95
24
20
ns
MC74HC4060A
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4
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns) - continued
V
CC
Guaranteed Limit
Symbol
Parameter
V
CC
V
-55 to 25
C
85
C
125
C
Unit
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High- Speed CMOS Data Book (DL129/D).
* For T
A
= 25
C and C
L
= 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
V
CC
= 2.0 V: t
P
= [93.7 + 59.3 (n-1)] ns
V
CC
= 4.5 V: t
P
= [30.25 + 14.6 (n-1)] ns
V
CC
= 3.0 V: t
P
= [61.5+ 34.4 (n-1)] ns
V
CC
= 6.0 V: t
P
= [24.4 + 12 (n-1)] ns
Typical @ 25
C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
35
pF
* Used to determine the no- load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High- Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS
(Input t
r
= t
f
= 6 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
CC
V
-55 to 25
C
85
C
125
C
Unit
t
rec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
100
75
20
17
125
100
25
21
150
120
30
25
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
23
19
ns
t
w
Minimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
23
19
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High- Speed CMOS Data Book
(DL129/D).
MC74HC4060A
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5
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
Negative-edge triggering clock input. A high-to-low
transition on this input advances the state of the counter. Osc
In may be driven by an external clock source.
Reset (Pin 12)
Active-high reset. A high level applied to this input
asynchronously resets the counter to its zero state (forcing
all Q outputs low) and disables the oscillator.
OUTPUTS
Q4--Q10, Q12-Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)
Active-high outputs. Each Qn output divides the Clock
input frequency by 2
N
. The user should note the Q1, Q2, Q3
and Q11 are not available as outputs.
Osc Out 1, Osc Out 2 (Pins 9, 10)
Oscillator outputs. These pins are used in conjunction
with Osc In and the external components to form an
oscillator. When Osc In is being driven with an external
clock source, Osc Out 1 and Osc Out 2 must be left open
circuited. With the crystal oscillator configuration in Figure
6, Osc Out 2 must be left open circuited.
SWITCHING WAVEFORMS
t
w
t
f
Osc In
Q
V
CC
GND
90%
50%
10%
t
r
t
w
90%
50%
10%
t
PHL
1/f
MAX
t
PLH
t
TLH
t
THL
Reset
V
CC
GND
t
PHL
50%
Figure 1.
Figure 2.
Q
V
CC
GND
50%
Osc In
50%
t
rec
50%
Qn
V
CC
GND
50%
Qn+1
C
L
*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3.
Figure 4. Test Circuit
t
PLH
t
PHL
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