Current Regulation and DC Sequencing Circuits for
Dual Supply GaAs Power Amplifiers
Introduction
The purpose of this application note is to address the issue of DC operation for Pacific Monolithics'
dual supply GaAs power amplifiers. The PM2107 is used in this application note as the example. A
critical issue in the operation of GaAs amplifiers is the control of the DC biasing point. GaAs
MESFET devices inherently have variation in gate pinch off voltage and saturated drain current due
to gate recessing and channel implant techniques. Additionally, temperature variations can cause
shifts in drain current. Due to these variations the drain current of the PM2107, under fixed negative
gate voltage bias, can vary up to +/- 90mA under quiescent operation (no RF applied) or backed off
linear modes of operation. The variation is larger in linear applications as compared to saturated
applications because of the large signal self-biasing effect in the amplifier. Current variation leads to
difficulty in current budgeting and thermal management, especially in battery applications, thereby
making current regulation often necessary.
Most dual supply amplifiers require that the negative bias be turned on before applying the positive
drain voltage to the amplifier to avoid the surge in drain current and the associated thermal or metal
migration degradation. Typically the negative bias is generated by a charge pump plus filtering
thereby possibly causing a momentary delay in the negative supply which in turn may create a
momentary surge in the drain current. Experiments at 5V Vds have shown that Pacific Monolithics'
dual supply GaAs amplifiers can withstand a power up (Vds=5V, Vgs=0V) current surge of 500Ms
or less before the maximum allowable junction temperature is reached. Any longer delay in the
ramping of the negative supply or continuous repetition of such incidents may damage the amplifiers
and cause long term reliability issues. A DC sequencing circuit can be used to prevent the problem.
The DC sequencing and current regulation circuits on page 3 were developed to operate with Pacific
Monolithics' dual supply power amplifiers. They are presented here to operate together as one
circuit but they may be used independently of each other if only one of the functions is desired.
Principles of Operation
DC Sequencing Circuit
The purpose of the DC sequencing circuit is to ensure that a negative bias voltage is present before
switching power to the amplifier. When a negative voltage of more than -0.7V is present on the
emitter terminal of Q1, the transistor turns on and sinks current through R3. The collector voltage of
Q1 will drop relative to the supply voltage and turns on M1, switching power to the amplifier. D1
and D2 are used for offsetting the trigger level of the negative bias voltage. R2 feeds the emitter of
Q1 to guarantee the transistor is off in the event that the bias supply is floating.
Application Note
2798
Current Regulation Circuit
The purpose of the current regulation circuit is to automatically set the bias level of the amplifier and
maintain constant quiescent current over temperature. A reference voltage at the emitter terminal of
Q3 is set by a resistive voltage divider network, R4 and R5, and the Vbe drop of Q2. The voltage
drop across R6 sets a limited current flow to supply the drain of the second stage of the amplifier,
which with the recommended configuration is about 200mA quiescent current. This resistor can be
changed to set the desired current level for regulation. Vgg1 is tapped off the regulated Vgg2 by the
resistive voltage divider network, R7 and R8. Thus it can be adjusted from 0V to Vgg2, offering the
flexibility of biasing the 1st stage independently yet still regulated proportionally to Vgg2. The
recommended resistor values bias the 1st stage of the amplifier at about 75mA quiescent drain
current. Q2 and Q3 are configured as a current mirror, so the circuit tracks over temperature as well.
Under large signal operation, the AC voltage self biases the 2nd stage and overcomes the current
regulator.
Design Equations:
V
V
R
R
R
dd
s
2
4
5
5
0 7
0 7
=
-
+
+
.
.
*
*
I
V
V
R
ds
s
dd
2
2
6
-
*Assuming Vbe of Q2 is 0.7V.
**Ids2 is slightly less then the expression due to some current flowing into Q3.
Design Considerations
The 1% tolerance of the resistors used in critical areas of the current regulation circuit must be
observed for minimum current variation. A power MOS switch with least "on" channel resistance
for the same current handling capability is recommended. See the parts list on page 3 for suggested
manufacturers. This design condition is for 5V supply. Operation at other supply voltages may
require adjustments to R6 to obtain the desired current. A negative 3V supply of 3mA is required to
set the bias condition. Page 4 presents some performance curves of the PM2107 using both the
sequencing and current regulation circuit.
PM2104 and PM2105 Application
The above discussions can be equally well applied to other Pacific Monolithics' dual supply
amplifiers, the PM2104 and PM2105.
For further information, please call
Pacific Monolithics, Inc.
RF Products
408-745-2700
Page 2
AP2798
M1
P_MOS
IRFD9120
Q1
NPN
BCW60D
Q3
PNP
BCW61D
Q2
PNP
BCW61D
R1
1.5K
R2
20K
R4
105
1%
R6
0.47
5%
R5
5.11K
1%
R9
510
R3
20K
Vsupply
+5V
275mA
Vbias
-3V
3mA
Vdd1
Vdd2
Vgg2
Vgg1
PM2107
PM2105
RFin
RFout
`
D2
D1
R7
4.7K
R8
3.3K
DC Sequencing Circuit
Current Regulation Circuit
Dual Supply Ampfiliers
PM2107, PM2105
Ids2 = 200mA
Vdd2
Vs
Ids1 = 75mA
DC Sequencing and Current Regulation Circuit Parts List
DC Sequencing Circuit:
Part#
Value
Type/Size
Descriptions/Suggested Manufacturers
R1
1.5K
SM 0603
Surface Mount Resistor
R2, R3
20K
SM 0603
Surface Mount Resistor
D1, D2
Diode
SOT23
PN Diode, Zetex: (Digi-key PN: BAV99ZXCT-ND)
Q1
High
NPN
SOT23
NPN Bipolar Transistor, High Beta
Zetex: BCW60D, BCX70K; Diodes Inc.: BC847C
M1
PMOS Switch
SOT6
Power MOS Switch
Fairchild Semi. (Digi-key PN: NDC652PCT-ND)
National Semi. PN: NDS332P
Current Regulation Circuit:
Part#
Value
Type/Size
Descriptions/Suggested Manufacturers
R4
105 1%
SM 0603
1% Surface Mount Resistor
R5
5.11K 1%
SM 0603
1% Surface Mount Resistor
R6
0.47
SM 2512
Surface Mount Resistor
R7
4.7K
SM 0603
Surface Mount Resistor
R8
3.3K
SM 0603
Surface Mount Resistor
R9
510
SM 0603
Surface Mount Resistor
Q2, Q3
High
PNP
SOT23
PNP Bipolar Transistor, High Beta
Zetex: BCW61D, BCX71K; Philips: BC857C
*Note: All resistor value tolerances are 5% unless specified.
Page 3
AP2798
RF Performances with Current Regulation Bias
P o u t, P A E v s P in
19
20
21
22
23
24
25
26
27
28
29
30
31
-5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
8
9 10
P in (dBm )
Pout
(
d
Bm)
5
12
19
26
33
40
47
54
61
68
75
82
89
PAE (
%
)
25 C
85C
-4 0C
85 C
-40 C
25C
P out, Ids vs P in
19
20
21
22
23
24
25
26
27
28
29
30
31
-5 -4 -3 -2 -1 0
1
2
3
4
5
6
7
8
9 10
Pin (dBm)
Pout
(
d
Bm)
260
290
320
350
380
410
440
470
500
530
560
590
620
I
ds (
m
A)
85C
-40C
85C
-40C
25C
25C
S a tu rate d R F P o w er, Id s
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
-4 0
-2 0
0
2 0
4 0
6 0
7 5
8 5
T em p eratu re (D eg .C )
Pout
(
d
Bm)
2 5 0
2 7 5
3 0 0
3 2 5
3 5 0
3 7 5
4 0 0
4 2 5
4 5 0
4 7 5
5 0 0
O ver T em p e ratu re
Id
s
(mA
)
P o u t
Id s _ R F
Id s_ Q u ie s c e n t
S a tu ra te d R F P o w e r, Id s v s . V g g
29 .0
29 .2
29 .4
29 .6
29 .8
30 .0
30 .2
30 .4
-3.6
-3.4
-3 .2
-3 .0
-2.8
-2.6
V g g (V )
Pout (dBm
)
100
200
300
400
500
600
700
800
Ids
(m
A)
Pout
Id s_R F
Id s_Q u iescent
S a tu ra te d R F P o w e r, Ig g v s . V g g
2 9 .0
2 9 .2
2 9 .4
2 9 .6
2 9 .8
3 0 .0
3 0 .2
3 0 .4
-3 .6
-3 .4
-3 .2
-3 .0
-2 .8
-2 .6
V g g (V )
Pout (dBm)
2 .0
2 .6
3 .2
3 .8
4 .4
5 .0
5 .6
6 .2
Igg (mA)
Ig g _ R F
Ig g _ Q u ie s c e n t
P o u t
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
-4 0
-2 0
0
2 0
4 0
6 0
7 5
8 5
Te m p e ra tu re (D e g .C )
P
out (dB
m)
40
42
44
46
48
50
52
54
56
58
60
S a tu ra te d R F Po w er, PA E
O v e r T em p e ra tu re
PAE (
%
)
Pacific Monolithics, Inc. 1998 - Specifications subject to change without notice. AP2798 - 7/17/98
Page 4
AP2798
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