For Communications Equipment
Overview
The MN6152U is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.8 to 2.5 V) and low power consumption (5 mW
for V
DD
=2.0 V, F
IN
=100 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
Features
Low power supply voltage: V
DD
=1.8 to 2.5V
Low power consumption:
5mW (V
DD
=2.0V,
F
IN
=100MHz)
High-speed operation:
F
IN
=175MHz
Frequency dividing ratios in reference frequency
dividing stage: 5 to 131,071
Frequency dividing ratios in comparator stage: 272 to
262,143
Lock detector output pin
Two types of phase comparator output
- Internal charge pump output
- Output for external charge pump
Output monitor pins for both comparator and refer-
ence frequency dividing stages
MN6152U
PLL LSI with Built-In Prescaler
Pin Assignment
SSOP016-P-0225
(TOP VIEW)
X
IN
X
OUT
FV
V
DD
D
OP
V
SS
LD
F
IN
OR
OV
LC
FR
PS
LE
DATA
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MN6152U
For Communications Equipment
Block Diagram
Amplifier
Amplifier
Phase
matching
17-bit programmable counter
14-bit programmable
counter
18-bit shift register
17-bit latch
18-bit latch
Swallow
counter
Data control
Prescaler and
phase matching
Phase comparator
Control
1
2
9
10
11
12
8
13
14
7
15
16
5
3
FR
LC
LD
OV
OR
D
OP
FV
X
IN
F
IN
X
OUT
CLK
DATA
LE
PS
For Communications Equipment
MN6152U
Pin Descriptions
Pin No.
Symbol
Function Description
1
X
IN
Crystal oscillator connection pins:
2
X
OUT
X
IN
=Oscillator circuit input pin;
X
OUT
=Oscillator circuit output pin.
3
FV
Frequency divider output signal in comparator stage.
Phase comparator input monitor.
4
V
DD
Power supply
5
D
OP
Low-pass filter connection pin. Use a passive filter.
6
V
SS
Ground
7
LD
Phase comparator output pin:
"H" level for locked; "L"level for unlocked.
8
F
IN
Frequency divider input pin in comparating stage.
9
CLK
Shift register clock input pin.
The chip latches data at the rising edge of the CLK signal.
10
DATA
Shift register data input pin.
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
11
LE
Load enable signal input pin.
This is the latch-write-enable signal. It is at "H" level for write.
12
PS
Power save control signal input pin.
"H" level input starts the frequency divider and places the chip in operational mode.
"L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
13
FR
Reference frequency divider output signal.
Phase comparator input monitor.
14
LC
Charge pump control signal output pin.
When frequency divider operation is stopped, this pin is at "L" level, the
internal charge pump output is in the high-impedance state, and the loop is opened.
15
OV
Phase comparator output pin for external charge pump.
16
OR
MN6152U
For Communications Equipment
The following formula shows frequency divider operation.
F
IN
={ (16
N) + A}
(X
IN
R)
where
F
IN
: VCO output frequency
N
: Setting for 14-bit programmable counter on comparator side
A
: Setting for 4-bit swallow counter on comparator side
X
IN
: Reference oscillator frequency
R
: Setting for 17-bit programmable counter on reference side
Note that N should be greater than A.
N-Side Latch Data
MSB 14 bits
4 bits
LSB
Programmable counter setting (N)
Swallow counter setting (A)
MN6152 Frequency Dividing Data Settings
For Communications Equipment
MN6152U
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Power supply voltage
V
DD
0.3 to +3.5
Input pin voltage
V
I
V
SS
0.3 to V
DD
+0.3
V
Output pin voltage
V
O
V
SS
0.3 to V
DD
+0.3
Power dissipation
P
D
20
mW
Operating ambient temperature
T
opr
20 to +60
C
Storage temperature
T
stg
55 to +125
Operating Conditions
V
SS
=0V, Ta=20
to
+60C
Parameter
Symbol
Test Conditions
min
typ
max
Unit
Power supply voltage
V
DD
1.8
2.0
2.5
V
Electric Characteristics
V
DD
=2V, Ta=20
to
+60C
Parameter
Symbol
Test Conditions
min
typ
max
Unit
Power supply voltage
I
DD
F
IN
=100MHz, X
IN
=20MHz,
2.5
mA
PS="H"
I
Dstop
PS ="L" (at power save operation)
10
A
Input Pins CLK, DATA, LE, and PS
V
DD
=1.8
to
2.5V
"H" level input voltage
V
IH
V
DD
0.2
V
DD
V
"L" level input voltage
V
IL
V
SS
0.2
Input leakage current
I
LI
1.0
A
Input Pin F
IN
V
DD
=1.8
to
2.5V
Input voltage
V
IN
0.4
V
p-p
Input current
I
IF
Pull-up resistor present
100
A
(PS="L")
Input leakage current
I
LIF
V
IN
=0 or 2V (PS="H")
20
A
Maximum operating frequency
F
INMAX
V
IN
=0.4 V
p-p
175
MHz
Minimum operating frequency
F
INMIN
V
IN
=0.4 V
p-p
10
MHz
Input Pin
X
IN
V
DD
=1.8
to
2.5V
Input voltage
V
IN
0.4
V
p-p
Input current
I
IX
Pull-up resistor present
2.5
mA
(PS="L")
Input leakage current
V
LIX
V
IN
=0 or 2V
5.0
A
Maximum operating frequency
X
INMAX
V
IN
=0.4 V
p-p
20
MHz
PDF 
ZIP