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Электронный компонент: BST74A

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DATA SHEET
Product specification
File under Discrete Semiconductors, SC13b
April 1995
DISCRETE SEMICONDUCTORS
BST74A
N-channel vertical D-MOS
transistor
April 1995
2
Philips Semiconductors
Product specification
N-channel vertical D-MOS transistor
BST74A
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in TO-92
variant envelope and designed for
use as line current interrupter in
telephone sets and for application in
relay, high-speed and
line-transformer drivers.
FEATURES
Direct interface to C-MOS, TTL,
etc.
High-speed switching
No second breakdown
QUICK REFERENCE DATA
PINNING - TO-92 VARIANT
Drain-source voltage
V
DS
max.
200 V
Gate-source voltage (open drain)
V
GSO
max.
20 V
Drain current (DC)
I
D
max.
250 mA
Total power dissipation up to T
amb
= 25
C
P
tot
max.
1 W
Drain-source ON-resistance
typ.
max.
6
12
I
D
= 250 mA; V
GS
= 10 V
R
DS(on)
Transfer admittance
I
D
= 250 mA; V
DS
= 15 V
Y
fs
typ.
250 mS
1
= source
2
= gate
3
= drain
PIN CONFIGURATION
Fig.1 Simplified outline and symbol.
Note: Various pinout configurations available.
handbook, halfpage
1
3
2
MAM146
s
d
g
April 1995
3
Philips Semiconductors
Product specification
N-channel vertical D-MOS transistor
BST74A
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
THERMAL RESISTANCE
Note
1. Transistor mounted on printed circuit board, max. lead length 4 mm, mounting pad for collector lead min.
10 mm
10 mm.
Drain-source voltage
V
DS
max.
200 V
Gate-source voltage (open drain)
V
GSO
max.
20 V
Drain current (DC)
I
D
max.
250 mA
Drain current (peak)
I
DM
max.
800 mA
Total power dissipation up to T
amb
= 25
C (note 1)
P
tot
max.
1 W
Storage temperature range
T
stg
-
65 to +150
C
Junction temperature
T
j
max.
150
C
From junction to ambient (note 1)
R
th j-a
=
125 K/W
April 1995
4
Philips Semiconductors
Product specification
N-channel vertical D-MOS transistor
BST74A
CHARACTERISTICS
T
j
= 25
C unless otherwise specified
Drain-source breakdown voltage
I
D
= 10
A; V
GS
= 0
V
(BR)DS
min.
200 V
Drain-source leakage current
V
DS
= 160 V; V
GS
= 0
I
DSS
max.
10
A
Gate-source leakage current
V
GS
= 20 V; V
DS
= 0
I
GSS
max.
100 nA
Gate threshold voltage
min.
max.
0.8
2.8
V
V
I
D
= 1 mA; V
DS
= V
GS
V
GS(th)
Drain-source ON-resistance (see Fig.4)
typ.
max.
6
12
I
D
= 250 mA; V
GS
= 10 V
R
DS(on)
Transfer admittance
I
D
= 250 mA; V
DS
= 15 V
Y
fs
typ.
250 mS
Input capacitance at f = 1 MHz
typ.
max.
70
90
pF
pF
V
DS
= 10 V; V
GS
= 0
C
iss
Output capacitance at f = 1 MHz
typ.
max.
20
30
pF
pF
V
DS
= 10 V; V
GS
= 0
C
oss
Feedback capacitance at f = 1 MHz
typ.
max.
5
10
pF
pF
V
DS
= 10 V; V
GS
= 0
C
rss
Switching times (see Figs 2 and 3)
I
D
= 250 mA; V
DS
= 50 V; V
GS
= 0 to 10 V
t
on
typ.
4 ns
max.
10 ns
t
off
typ.
15 ns
max.
25 ns
April 1995
5
Philips Semiconductors
Product specification
N-channel vertical D-MOS transistor
BST74A
Fig.2 Switching times test circuit.
handbook, halfpage
MSA631
50
VDD = 50 V
ID
10 V
0 V
Fig.3 Input and output waveforms.
handbook, halfpage
MBB692
10 %
90 %
90 %
10 %
ton
toff
OUTPUT
INPUT
Fig.4 T
j
= 25
C; typical values.
handbook, halfpage
14
4
6
ID
(mA)
RDSon (
)
8
10
12
10
3
10
2
10
MDA764
VGS = 10 V
5 V
4 V
Fig.5 T
j
= 25
C; V
DS
= 10 V; typical values.
handbook, halfpage
0
10
1
0
0.2
0.4
0.6
0.8
2
4
6
ID
(A)
8
MDA765
VGS (V)