GTL2010 10-bit bi-directional low voltage translator

Philips Semiconductors

Product data

GTL2010

10-bit bi-directional low voltage translator

2003 May 02

FEATURES

10-bit bi-directional low voltage translator

Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V, 3.3 V, and 5 V buses which allows direct interface with GTL,
GTL+, LVTTL/TTL and 5 V CMOS levels

Provides bi-directional voltage translation with no direction pin

Low 6.5

RDS

resistance between input and output pins

(Sn/Dn)

Supports hot insertion

No power supply required - Will not latch up

5 V tolerant inputs

Low stand-by current

Flow-through pinout for ease of printed circuit board trace routing

ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V per JESD22-C101

Packages offered: TSSOP24, HVQFN24

APPLICATIONS

Any application that requires bi-directional or unidirectional
voltage level translation from any voltage from 1.0 V to 5.0 V to
any voltage from 1.0 V to 5.0 V

The open drain construction with no direction pin is ideal for
bi-directional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V)
processor I

C port translation to the normal 3.3 V and/or 5.0 V I

bus signal levels or GTL/GTL+ translation to LVTTL/TTL signal
levels.

DESCRIPTION

The Gunning Transceiver Logic -- Transceiver Voltage Clamps
(GTL-TVC) provide high-speed voltage translation with low
ON-state resistance and minimal propagation delay. The GTL2010
provides 10 NMOS pass transistors (Sn and Dn) with a common
gate (G

REF

) and a reference transistor (S

REF

and D

REF

). The device

allows bi-directional voltage translations between 1.0 V and 5.0 V
without use of a direction pin.

When the Sn or Dn port is LOW the clamp is in the ON-state and a
low resistance connection exists between the Sn and Dn ports.
Assuming the higher voltage is on the Dn port, when the Dn port is
HIGH, the voltage on the Sn port is limited to the voltage set by the
reference transistor (S

REF

). When the Sn port is high, the Dn port is

pulled to V

by the pull up resistors. This functionality allows a

seamless translation between higher and lower voltages selected by
the user, without the need for directional control.

All transistors have the same electrical characteristics and there is
minimal deviation from one output to another in voltage or
propagation delay. This is a benefit over discrete transistor voltage
translation solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are identical,
S

REF

and D

REF

can be located on any of the other ten matched

Sn/Dn transistors, allowing for easier board layout. The translator's
transistors provides excellent ESD protection to lower voltage
devices and at the same time protect less ESD resistant devices.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DWG NUMBER

24-Pin Plastic TSSOP

-40 to +85

GTL2010PW

GTL2010

SOT355-1

24-Pin Plastic HVQFN

-40 to +85

GTL2010BS

2010

SOT616-1

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.

Philips Semiconductors

Product data

GTL2010

10-bit bi-directional low voltage translator

2003 May 02

PIN CONFIGURATION -- TSSOP

REF

GND

SA00641

Figure 1. Pin configuration -- TSSOP

PIN CONFIGURATION -- HVQFN

REF

TOP VIEW

SW02141

REF

GND

Figure 2. Pin configuration -- HVQFN

PIN DESCRIPTION

TSSOP

PIN

NUMBER

HVQFN

PIN

NUMBER

SYMBOL

NAME AND FUNCTION

GND

Ground (0 V)

REF

Source of reference
transistor

3 - 12

24, 1 - 9

Port S

to Port S

13 - 22

10 - 19

Port D

to Port D

REF

Drain of reference
transistor

REF

Gate of reference
transistor

FUNCTION TABLE

HIGH to LOW translation assuming Dn is at the higher voltage level

GREF

DREF

SREF

In-Dn

Out-Sn

Transistor

0 V

Off

0 - V

Off

H = HIGH voltage level
L

= LOW voltage level

X = Don't Care

NOTES:
1. Sn is not pulled up or pulled down.
2. Sn follows the Dn input low.
3. G

REF

should be at least 1.5 V higher than S

REF

for best

translator operation.

4. V

is equal to the S

REF

voltage.

FUNCTION TABLE

LOW to HIGH translation assuming Dn is at the higher voltage level

GREF

DREF

SREF

In-Sn

Out-Dn

Transistor

0 V

Off

nearly off

0 - V

Off

H = HIGH voltage level
L

= LOW voltage level

X = Don't Care

NOTES:
1. Dn is pulled up to V

through an external resistor.

2. Dn follows the Sn input LOW.
3. G

REF

should be at least 1.5 V higher than S

REF

for best

translator operation.

4. V

is equal to the S

REF

voltage.

CLAMP SCHEMATIC

SA00647

REF

Philips Semiconductors

Product data

GTL2010

10-bit bi-directional low voltage translator

2003 May 02

APPLICATIONS

Bi-directional translation

For the bi-directional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the G

REF

input must be

connected to D

REF

and both pins pulled to high side V

through a pull-up resistor (typically 200 k

). A filter capacitor on D

REF

recommended. The processor output can be totem pole or open drain (pull-up resistors may be required) and the chipset output can be totem
pole or open drain (pull-up resistors are required to pull the Dn outputs to V

). However, if either output is totem pole, data must be

uni-directional or the outputs must be 3-statable and the outputs must be controlled by some direction control mechanism to prevent high to low
contentions in either direction. If both outputs are open drain, no direction control is needed. The opposite side of the reference transistor (S

REF

)

is connected to the processor core power supply voltage. When D

REF

is connected through a 200 k

resistor to a 3.3 V to 5.5 V V

supply

and S

REF

is set between1.0 V to V

- 1.5 V, the output of each Sn has a maximum output voltage equal to S

REF

and the output of each Dn

has a maximum output voltage equal to V

1.8 V

GND

REF

1.5 V

1.2 V

1.0 V

SA00642

GTL2002

CORE

CPU I/O

CHIPSET I/O

TOTEM POLE OR
OPEN DRAIN I/O

TYPICAL BI-DIRECTIONAL VOLTAGE TRANSLATION

5 V

CHIPSET I/O

3.3 V

INCREASE BIT

SIZE BY USING

10-BIT GTL2010 OR

22-BIT GTL2000

REF

200 k

Figure 3. Bi-directional translation to multiple higher voltage levels such as an I

C-bus application

Philips Semiconductors

Product data

GTL2010

10-bit bi-directional low voltage translator

2003 May 02

Uni-directional down translation

For uni-directional clamping, higher voltage to lower voltage, the G

REF

input must be connected to D

REF

and both pins pulled to the higher side

through a pull-up resistor (typically 200 k

). A filter capacitor on D

REF

is recommended. Pull-up resistors are required if the chipset I/O are

open drain. The opposite side of the reference transistor (S

REF

) is connected to the processor core supply voltage. When D

REF

is connected

through a 200 k

resistor to a 3.3 V to 5.5 V V

supply and S

REF

is set between 1.0 V to V

- 1.5 V, the output of each Sn has a maximum

output voltage equal to S

REF

1.8 V

200 k

GND

REF

1.5 V

1.2 V

1.0 V

SA00643

GTL2002

CORE

CPU I/O

CHIPSET I/O

TOTEM POLE I/O

TYPICAL UNI-DIRECTIONAL - HIGH TO LOW VOLTAGE TRANSLATION

5 V

EASY MIGRATION TO
LOWER VOLTAGE AS

PROCESSOR GEOMETRY

SHRINKS.

Figure 4. Uni-directional down translation, to protect low voltage processor pins

Uni-directional up translation

For uni-directional up translation, lower voltage to higher voltage, the reference transistor is connected the same as for a down translation. A
pull-up resistor is required on the higher voltage side (Dn or Sn) to get the full high level, since the GTL-TVC device will only pass the reference
source (S

REF

) voltage as a high when doing an up translation. The driver on the lower voltage side only needs pull-up resistors if it is open

drain.

1.8 V

200 k

GND

REF

1.5 V

1.2 V

1.0 V

SA00644

GTL2002

CORE

CPU I/O

CHIPSET I/O

TOTEM POLE I/O
OR OPEN DRAIN

TYPICAL UNI-DIRECTIONAL - LOW TO HIGH VOLTAGE TRANSLATION

5 V

EASY MIGRATION TO
LOWER VOLTAGE AS

PROCESSOR GEOMETRY

SHRINKS.

Figure 5. Uni-directional up translation, to higher voltage chip sets

Philips Semiconductors

Product data

GTL2010

10-bit bi-directional low voltage translator

2003 May 02

Sizing pull-up resistor

The pull-up resistor value needs to limit the current through the pass transistor when it is in the "on" state to about 15 mA. This will guarantee a
pass voltage of 260 to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage will also be higher in the "on"
state. To set the current through each pass transistor at 15 mA, the pull-up resistor value is calculated as follows:

Resistor value (

W) +

Pull-u p voltage (V)

*0.35 V

0.015 A

The table below summarizes resistor values for various reference voltages and currents at 15 mA and also at 10 mA and 3 mA. The resistor
value shown in the +10% column or a larger value should be used to ensure that the pass voltage of the transistor would be 350 mV or less.
The external driver must be able to sink the total current from the resistors on both sides of the GTL-TVC device at 0.175 V, although the 15 mA
only applies to current flowing through the GTL-TVC device. See Application Note AN10145-01 Bi-Directional Voltage Translators for more
information.

PULL-UP RESISTOR VALUES

PULL-UP RESISTOR VALUE (OHMS)

15 mA

10 mA

3 mA

VOLTAGE

NOMINAL

+ 10 %

NOMINAL

+ 10 %

NOMINAL

+ 10 %

5.0 V

310

341

465

512

1550

1705

3.3 V

197

217

295

325

983

1082

2.5 V

143

158

215

237

717

788

1.8 V

106

145

160

483

532

1.5 V

115

127

383

422

1.2 V

283

312

NOTES:
1. Calculated for V

= 0.35 V

2. Assumes output driver V

= 0.175 V at stated current

3. +10% to compensate for V

range and resistor tolerance.

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

SYMBOL

PARAMETER

CONDITIONS

RATING

UNIT

SREF

DC source reference voltage

-0.5 to +7.0

DREF

DC drain reference voltage

-0.5 to +7.0

GREF

DC gate reference voltage

-0.5 to +7.0

DC voltage Port S

-0.5 to +7.0

DC voltage Port D

-0.5 to +7.0

REFK

DC diode current on reference pins

< 0

-50

DC diode current Port S

< 0

-50

DC diode current Port D

< 0

-50

MAX

DC clamp current per channel

Channel in ON-state

128

stg

Storage temperature range

-65 to +150

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

Philips Semiconductors

Product data

GTL2010

10-bit bi-directional low voltage translator

2003 May 02

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL

PARAMETER

CONDITIONS

Min

Max

UNIT

I/O

Input/output voltage (Sn, Dn)

5.5

SREF

DC source reference voltage

5.5

DREF

DC drain reference voltage

5.5

GREF

DC gate reference voltage

5.5

PASS

Pass transistor current

amb

Operating ambient temperature range

In free air

-40

+85

NOTE:
1. V

SREF

DREF

- 1.5 V for best results in level shifting applications.

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE
(unless otherwise noted)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Low level output voltage

= 3.0 V; V

SREF

= 1.365 V; V

or V

= 0.175 V;

clamp

= 15.2 mA

260

350

Input clamp voltage

= -18 mA

GREF

= 0 V

-1.2

Gate input leakage

= 5 V

GREF

= 0 V

I(GREF)

Gate capacitance

= 3 V or 0 V

IO(OFF)

Off capacitance

= 3 V or 0 V

GREF

= 0 V

7.4

IO(ON)

On capacitance

= 3 V or 0 V

GREF

= 3 V

18.6

GREF

= 4.5 V

3.5

GREF

= 3 V

4.4

= 0 V

GREF

= 2.3 V

= 64 mA

5.5

GREF

= 1.5 V

105

On-resistance

GREF

= 1.5 V

= 30 mA

GREF

= 4.5 V

= 2.4 V

GREF

= 3 V

= 15 mA

= 1.7 V

GREF

= 2.3 V

NOTES:
1. All typical values are measured at T

amb

= 25

2. Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch.

On-state resistance is determined by the lowest voltage of the two (Sn or Dn) terminals.

Philips Semiconductors

Product data

GTL2010

10-bit bi-directional low voltage translator

2003 May 02

AC CHARACTERISTICS FOR TRANSLATOR TYPE APPLICATIONS

REF

= 1.365 to 1.635 V; V

DD1

= 3.0 to 3.6 V; V

DD2

= 2.36 to 2.64 V; GND = 0 V; t

= t

3.0 ns. Refer to the Test Circuit diagram.

LIMITS

SYMBOL

PARAMETER

WAVEFORM

amb

= -40 to +85

UNIT

MIN

TYP

MAX

PLH

Propagation delay
Sn to Dn; Dn to Sn

0.5

1.5

5.5

NOTES:
1. All typical values are measured at V

DD1

= 3.3 V, V

DD2

= 2.5 V, V

REF

= 1.5 V and T

amb

= 25

2. Propagation delay guaranteed by characterization.
3. C

ON(max)

of 30 pF and a C

OFF(max)

of 15 pF is guaranteed by design.

AC WAVEFORMS

= 1.5 V; V

= GND to 3.0 V

INPUT

PHL

PLH

TEST JIG OUTPUT

HIGH-to-LOW
LOW-to-HIGH

DUT OUTPUT

HIGH-to-LOW
LOW-to-HIGH

GND

DD2

PHL1

PLH

PHL

PLH

SA00524

Waveform 1. The Input (S

) to Output (D

) Propagation Delays

TEST CIRCUIT

REF

SA00648

PULSE
GENERATOR

DUT

REF

DD1

DD2

200 k

150

TEST
JIG

Waveform 2. Load circuit

Philips Semiconductors

Product data

GTL2010

10-bit bi-directional low voltage translator

2003 May 02

AC CHARACTERISTICS FOR CBT TYPE APPLICATION

GND = 0 V; t

= 50 pF

SYMBOL

PARAMETER DESCRIPTION

LIMITS

-40

C to +85

REF

= 5 V

0.5 V

UNITS

Min

Mean

Max

Propagation delay

250

NOTES:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state

resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).

AC WAVEFORMS

= 1.5 V, V

= GND to 3.0 V

INPUT

1.5 V

OUTPUT

PLH

PHL

SA00639

2.5 V

1.5 V

3 V

0 V

Waveform 1. Input (Sn) to Output (Dn) Propagation Delays

TEST CIRCUIT AND WAVEFORMS

= 50 pF

500

Load Circuit

DEFINITIONS

Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.

TEST

open

PLZ

PZL

7 V

PHZ

PZH

open

SA00012

500

From Output
Under Test

7 V

Open

GND

Waveform 2. Load circuit

Philips Semiconductors

Product data

GTL2010

10-bit bi-directional low voltage translator

2003 May 02

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.

Koninklijke Philips Electronics N.V. 2003

Date of release: 05-03

Document order number:

9397 750 11458

Philips
Semiconductors

Data sheet status

[1]

Objective data

Preliminary data

Product data

Product
status

[2] [3]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Level

III

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Document Outline

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