Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

FEATURES

8 general purpose input/output expander/collector

Drop in replacement for PCF8574 with integrated 2-kbit EEPROM

Internal 256

8 EEPROM

Self timed write cycle

4 byte page write operation

C and SMBus interface logic

Internal power-on reset

Noise filter on SCL/SDA inputs

3 address pins allowing up to 8 devices on the I

C/SMBus

No glitch on power-up

Supports hot insertion

Power-up with all channels configured as inputs

Low standby current

Operating power supply voltage range of 2.5 V to 3.6 V

5 V tolerant inputs/outputs

0 kHz to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA

Package offerred: SO16, TSSOP16, HVQFN16

DESCRIPTION

The PCA9500 is an 8-bit I/O expander with an on-board 2-kbit
EEPROM.

The I/O expander's eight quasi bidirectional data pins can be
independently assigned as inputs or outputs to monitor board level
status or activate indicator devices such as LEDs. The system
master writes to the I/O configuation bits in the same way as for the
PCF8574. The data for each Input or Output is kept in the
corresponding Input or Output register. The system master can read
all registers.

The EEPROM can be used to store error codes or board
manufacturing data for read-back by application software for
diagnostic purposes and is included in the I/O expander package.

The PCA9500 has three address pins with internal pull-up resistors
allowing up to 8 devices to share the common two-wire I

C software

protocol serial data bus. The fixed GPIO I

C address is the same as

the PCF8574 and the fixed EEPROM I

C address is the same as

the PCF8582C-2, so the PCA9500 appears as two separate devices
to the bus master.

The PCA9500 supports hot insertion to facilitate usage in removable
cards on backplane systems.

The PCA9501 is an alternative to the functionally similar PCA9500
for systems where a higher number of devices are required to share
the same I

C-bus or an interrupt output is required.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

16-Pin Plastic SO (wide)

C to +85

PCA9500D

SOT162-1

16-Pin Plastic TSSOP

C to +85

PCA9500PW

PCA9500

SOT403-1

16-Pin Plastic HVQFN

C to +85

PCA9500BS

9500

SOT629-1

Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I

C patent.

C is a trademark of Philips Semiconductors Corporation.

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

PIN CONFIGURATION SO, TSSOP

SW00902

I/O0

I/O1

I/O2

I/O3

SDA

SCL

I/O7

I/O6

I/O5

I/O4

PCA9500

Figure 1. Pin configuration SO, TSSOP

PIN CONFIGURATION HVQFN

SW02004

TOP VIEW

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

SDA

SCL

Figure 2. Pin configuration HVQFN

PIN DESCRIPTION

SO, TSSOP

PIN NUMBER

HVQFN

PIN NUMBER

SYMBOL

NAME AND FUNCTION

1,2,3

15, 16, 1

A02

Address lines (internal pull-up)

4,5,6,7

2, 3, 4, 5

I/O0 to I/O3

Quasi-bidirectional I/O pins

Supply ground

9,10,11,12

7, 8, 9, 10

I/O4 to I/O7

Quasi-bidirectional I/O pins

Active LOW write control pin

SCL

C Serial Clock

SDA

C Serial Data

Supply Voltage

BLOCK DIAGRAM

POWER-ON

RESET

INPUT

FILTER

C/SMBus

CONTROL

INPUT/

OUTPUT

PORTS

WRITE pulse

READ pulse

SCL

SDA

8-BIT

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

SW01074

PCA9500

EEPROM

256 x 8

300 k

Figure 3. Block diagram

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

FUNCTIONAL DESCRIPTION

SW00546

WRITE PULSE

DATA FROM
SHIFT REGISTER

POWER-ON
RESET

READ PULSE

DATA TO
SHIFT REGISTER

I/O0 TO I/O7

100

Figure 4. Simplified schematic diagram of each I/O

DEVICE ADDRESSING

Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9500 is shown in
Figure 5. Internal pullup resistors are incorporated on the hardware selectable address pins.

R/W

(a) I/O EXPANDER

(b) MEMORY

SW01075

SLAVE ADDRESS

FIXED

HARDWARE

PROGRAMMABLE

R/W

FIXED

HARDWARE

PROGRAMMABLE

Figure 5. PCA9500 slave addresses

The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected while a logic 0 selects a write
operation.

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

CONTROL REGISTER

The PCA9500 contains a single 8-bit register called the Control Register, which can be written and read via the I

C-bus. This register is sent

after a successful acknowledgment of the slave address.

It contains the I/O operation information.

I/O OPERATIONS (see also Figure 4)

Each of the PCA9500's eight I/Os can be independently used as an input or output. Output data is transmitted to the port by the I/O WRITE
mode (see Figure 6). Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 7).

DATA 1

DATA 2

SDA

SCL

t pv

DATA 2 VALID

DATA 1 VALID

SW00548

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

ACKNOWLEDGE
FROM SLAVE

SLAVE ADDRESS (I/O EXPANDER)

DATA TO PORT

WRITE TO
PORT

DATA OUT
FROM PORT

Figure 6. I/O WRITE mode (output)

DATA 1

DATA 4

SDA

t ph

t ps

DATA 4

DATA 2

DATA 3

SW00549

SLAVE ADDRESS (I/O EXPANDER)

DATA FROM PORT

READ FROM
PORT

DATA INTO
PORT

START CONDITION

ACKNOWLEDGE
FROM SLAVE

R/W

ACKNOWLEDGE
FROM MASTER

STOP
CONDITION

DATA 1

Figure 7. I/O READ mode (input)

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

Quasi-bidirectional I/Os (see Figure 8)

A quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH.
In this mode, only a current source to V

is active. An additional strong pull-up to V

allows fast rising edges into heavily loaded outputs.

These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before
being used as inputs.

SDA

SCL

SW00905

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

ACKNOWLEDGE
FROM SLAVE

SLAVE ADDRESS (I/O EXPANDER)

DATA TO PORT

I/O3

I/O3
OUTPUT
VOLTAGE

I/O3
PULL-UP
OUTPUT
CURRENT

OHt

Figure 8. Transient pull-up current I

OHt

while I/O3 changes from LOW-to-HIGH and back to LOW

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

MEMORY OPERATIONS

Write operations

Write operations require an additional address field to indicate the
memory address location to be written. The address field is eight
bits long, providing access to any one of the 256 words of memory.
There are two types of write operations, byte write and page write.

Write operation is possible when WC control pin put at a low logic
level (0). When this control signal is set at 1, write operation is not
possible and data in the memory is protected.

Byte Write and Page Write explained below assume that Write
Control pin (WC) is set to 0.

Byte Write (see Figure 9)
To perform a byte write the start condition is followed by the memory
slave address and the R/W bit set to 0. The PCA9500 will respond
with an acknowledge and then consider the next eight bits sent as

the word address and the eight bits after the word address as the
data. The PCA9500 will issue an acknowledge after the receipt of
both the word address and the data. To terminate the data transfer
the master issues the stop condition, initiating the internal write cycle
to the non-volatile memory. Only write and read operations to the
Quasi-bidirectional I/O are allowed during the internal write cycle.

Page Write (see Figure 10)
A page write is initiated in the same way as the byte write. If after
sending the first word of data, the stop condition is not received the
PCA9500 considers subsequent words as data. After each data
word the PCA9500 responds with an acknowledge and the two least
significant bits of the memory address field are incremented. Should
the master not send a stop condition after four data words the
address counter will return to its initial value and overwrite the data
previously written. After the receipt of the stop condition the inputs
will behave as with the byte write during the internal write cycle.

SW02036

STOP CONDITION.
WRITE TO THE
MEMORY IS
PERFORMED

ACKNOWLEDGE

FROM SLAVE

SDA

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

ACKNOWLEDGE
FROM SLAVE

SLAVE ADDRESS (MEMORY)

WORD ADDRESS

DATA

Figure 9. Byte write

SW02037

ACKNOWLEDGE

FROM SLAVE

A2 A1 A0

SDA

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

ACKNOWLEDGE
FROM SLAVE

SLAVE ADDRESS (MEMORY)

WORD ADDRESS

DATA TO MEMORY

DATA n

DATA n + 3

STOP CONDITION.

WRITE TO THE MEMORY

IS PERFORMED

DATA TO MEMORY

Figure 10. Page Write

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

Read operations

PCA9500 read operations are initiated in an identical manner to
write operations with the exception that the memory slave address'
R/W bit is set to a one. There are three types of read operations;
current address, random and sequential.

Current Address Read (see Figure 11)
The PCA9500 contains an internal address counter that increments
after each read or write access, as a result if the last word accessed
was at address n then the address counter contains the address
n+1.

When the PCA9500 receives its memory slave address with the
R/W bit set to one it issues an acknowledge and uses the next eight
clocks to transmit the data contained at the address stored in the
address counter. The master ceases the transmission by issuing the
stop condition after the eighth bit. There is no ninth clock cycle for
the acknowledge.

Random Read (see Figure 12)
The PCA9500's random read mode allows the address to be read
from to be specified by the master. This is done by performing a
dummy write to set the address counter to the location to be read.

The master must perform a byte write to the address location to be
read, but instead of transmitting the data after receiving the
acknowledge from the PCA9500 the master reissues the start
condition and memory slave address with the R/W bit set to one.
The PCA9500 will then transmit an acknowledge and use the next
eight clock cycles to transmit the data contained in the addressed
location. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.

Sequential Read (see Figure 13)
The PCA9500 sequential read is an extension of either the current
address read or random read. If the master doesn't issue a stop
condition after it has received the eighth data bit, but instead issues
an acknowledge, the PCA9500 will increment the address counter
and use the next eight cycles to transmit the data from that location.
The master can continue this process to read the contents of the
entire memory. Upon reaching address 255 the counter will return to
address 0 and continue transmitting data until a stop condition is
received. The master ceases the transmission by issuing the stop
condition after the eighth bit, omitting the ninth clock cycle
acknowledge.

SW00556

SDA

ACKNOWLEDGE
FROM SLAVE

R/W

START CONDITION

STOP
CONDITION

SLAVE ADDRESS (MEMORY)

DATA FROM MEMORY

Figure 11. Current Address Read

SDA

SW00557

A2 A1 A0

START
CONDITION

R/W

ACKNOWLEDGE
FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE
FROM SLAVE

DATA FROM MEMORY

STOP
CONDITION

START
CONDITION

A2 A1 A0

R/W

SLAVE ADDRESS (MEMORY)

WORD ADDRESS

SLAVE ADDRESS (MEMORY)

Figure 12. Random Read

SDA

SW00558

SLAVE ADDRESS (MEMORY)

DATA FROM MEMORY

A2 A1 A0

START CONDITION

R/W

ACKNOWLEDGE
FROM SLAVE

ACKNOWLEDGE
FROM MASTER

DATA n

ACKNOWLEDGE
FROM MASTER

DATA n+X

STOP
CONDITION

DATA n+1

DATA FROM MEMORY

Figure 13. Sequential Read

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

CHARACTERISTICS OF THE I

C-BUS

The I

C-bus is for 2-way, 2-line communication between different ICs

or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.

Bit transfer

One data bit is transferred during each clock phase. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (See Figure 14).

Start and Stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the Start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the Stop condition (P)
(see Figure 15).

System configuration

A device generating a message is a "transmitter", a device receiving
is the "receiver". The device that controls the message is the
"master" and the devices which are controlled by the master are the
"slaves" (see Figure 16).

SDA

SCL

SW00542

DATA LINE

STABLE;

DATA VALID

CHANGE

OF DATA

ALLOWED

Figure 14. Bit transfer

SDA

SCL

SDA

SCL

SW00543

START CONDITION

STOP CONDITION

Figure 15. Definition of start and stop conditions

SDA

SCL

SW00544

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

Figure 16. System configuration

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

Acknowledge (see Figure 17)

The number of data bytes transferred between the start and the stop
conditions from transmitter to receiver is not limited. Each byte of
eight bits is followed by one acknowledge bit. The acknowledge bit
is a HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked

out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set-up and hold times must be
taken into account.

A master receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.

SW00545

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

ACKNOWLEDGE

NOT ACKNOWLEDGE

CLOCK PULSE FOR
ACKNOWLEDGEMENT

START
CONDITION

Figure 17. Acknowledgment on the I

C-bus

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

TYPICAL APPLICATION

Applications

Board version tracking and configuration

Board health monitoring and status reporting

Multi-card systems in Telecom, Networking, and Base Station
Infrastructure Equipment

Field recall and troubleshooting functions for installed boards

General-purpose integrated I/O with memory

Drop in replacement for PCF8574 with integrated 2-kbit EEPROM

Bus master sees GPIO and EEPROM as two separate devices

Three hardware address pins allow up to 8 PCA9500s to be
located in the same I

C/SMBus

CONTROL

EEPROM

GPIO

ASIC

BACKPLANE

CPU

MONITORING

AND

CONTROL

INPUTS

ALARM

LEDs

PCA9500

CARD ID, SUBROUTINES, CONFIGURATION DATA, OR REVISION HISTORY

SW02003

UP TO 8 CARDS

CONFIGURATION CONTROL

Figure 18. Typical application

A central processor/controller typically located on the system main
board can use the 400 kHz I

C/SMBus to poll the PCA9500 devices

located on the system cards for status or version control type of
information. The PCA9500 may be programmed at manufacturing to
store information regarding board build, firmware version,

manufacturer identification, configuration option data

...

Alternately,

these devices can be used as convenient interface for board
configuration, thereby utilizing the I

C/SMBus as an intra-system

communication bus.

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.

SYMBOL

PARAMETER

MIN

MAX

UNIT

Supply voltage

0.5

4.0

Input voltage

0.5

5.5

DC input current

DC output current

Supply current

100

Supply current

100

tot

Total power dissipation

400

Total power dissipation per output

100

stg

Storage temperature

+150

amb

Operating temperature

+85

DC ELECTRICAL CHARACTERISTICS

amb

= 40 to +85

C unless otherwise specified; V

= 3.3 V

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supply

Supply voltage

2.5

3.3

3.6

DDQ

Standby current

A0, A1, A2, WC = HIGH

DD1

Supply current read

DD2

Supply current write

POR

Power-on reset voltage

2.4

Input SCL; input, output SDA

LOW-level input voltage

0.5

0.3V

HIGH-level input voltage

0.7V

5.5

LOW-level output current

= 0.4 V

Input leakage current

= V

or V

Input capacitance

= V

I/O Expander Port

LOW-level input voltage

0.5

0.3V

HIGH-level input voltage

0.7V

5.5

IHL(max)

Input current through protection diodes

400

LOW-level output current

= 1 V

HIGH-level output current

= V

100

300

OHt

Transient pull-up current

Input capacitance

Output capacitance

Address Inputs (A0, A1, A2), WC input

LOW-level input voltage

0.5

0.3V

HIGH-level input voltage

0.7V

5.5

Input leakage current

= V

Input leakage (pull-up) current

= V

100

NOTES:
1. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

NON-VOLATILE STORAGE SPECIFICATIONS

PARAMETER

SPECIFICATION

Memory cell data retention

10 years minimum

Number of memory cell write cycles

100,000 cycles minimum

C-BUS TIMING CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

C-bus timing (see Figure 20; Note 2)

SCL

SCL clock frequency

400

kHz

tolerable spike width on bus

BUF

bus free time

1.3

SU;STA

START condition set-up time

0.6

HD;STA

START condition hold time

0.6

SCL and SDA rise time

0.3

SCL and SDA fall time

0.3

SU;DAT

data set-up time

250

HD;DAT

data hold time

VD;DAT

SCL LOW to data out valid

1.0

SU;STO

STOP condition set-up time

0.6

NOTE:
2. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to V

and V

with an input

voltage swing of V

to V

PORT TIMING CHARACTERISTICS

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Output data valid; C

100 pF

Input data setup time; C

100 pF

Input data hold time; C

100 pF

handbook, full pagewidth

SCL

SDA

MBD820

BIT 0

LSB

(R/W)

HD;STA

SU;DAT

HD;DAT

VD;DAT

SU;STO

BUF

SU;STA

1 / f

SCL

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6)

ACKNOWLEDGE

(A)

STOP

CONDITION

(P)

SW00561

PROTOCOL

Figure 20.

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

SOLDERING

Introduction

There is no soldering method that is ideal for all IC packages. Wave
soldering is often preferred when through-hole and surface mounted
components are mixed on one printed-circuit board. However, wave
soldering is not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these situations
reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more
in-depth account of soldering ICs can be found in our

IC Package

Databook (order code 9398 652 90011).

DIP

Soldering by dipping or by wave
The maximum permissible temperature of the solder is 260

solder at this temperature must not be in contact with the joint for
more than 5 seconds. The total contact time of successive solder
waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the
temperature of the plastic body must not exceed the specified
maximum storage temperature (T

stg

max). If the printed-circuit board

has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.

Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of
the package, below the seating plane or not more than 2 mm above
it. If the temperature of the soldering iron bit is less than 300

C it

may remain in contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

SO and SSOP

Reflow soldering
Reflow soldering techniques are suitable for all SO and SSOP
packages.

Reflow soldering requires solder paste (a suspension of fine solder
particles, flux and binding agent) to be applied to the printed-circuit
board by screen printing, stencilling or pressure-syringe dispensing
before package placement.

Several techniques exist for reflowing; for example, thermal
conduction by heated belt. Dwell times vary between 50 and 300
seconds depending on heating method. Typical reflow temperatures
range from 215 to 250

Preheating is necessary to dry the paste and evaporate the binding
agent. Preheating duration: 45 minutes at 45

Wave soldering
Wave soldering is not recommended for SSOP packages. This is
because of the likelihood of solder bridging due to closely-spaced
leads and the possibility of incomplete solder penetration in
multi-lead devices.

If wave soldering cannot be avoided, the following conditions
must be observed:

A double-wave (a turbulent wave with high upward pressure
followed by a smooth laminar wave) soldering technique
should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.

Even with these conditions, only consider wave soldering
SSOP packages that have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).

During placement and before soldering, the package must be fixed
with a droplet of adhesive. The adhesive can be applied by screen
printing, pin transfer or syringe dispensing. The package can be
soldered after the adhesive is cured.

Maximum permissible solder temperature is 260

C, and maximum

duration of package immersion in solder is 10 seconds, if cooled to
less than 150

C within 6 seconds. Typical dwell time is 4 seconds

at 250

A mildly-activated flux will eliminate the need for removal of
corrosive residues in most applications.

Repairing soldered joints
Fix the component by first soldering two diagonally opposite end
leads. Use only a low voltage soldering iron (less than 24 V) applied
to the flat part of the lead. Contact time must be limited to
10 seconds at up to 300

C. When using a dedicated tool, all other

leads can be soldered in one operation within 2 to 5 seconds
between 270 and 320

Philips Semiconductors

Product data sheet

PCA9500

8-bit I

C and SMBus I/O port with 2-kbit EEPROM

2004 Sep 30

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.

Koninklijke Philips Electronics N.V. 2004

Date of release: 09-04

Document number:

9397 750 14134

Philips

Semiconductors

Data sheet status

[1]

Objective data sheet

Preliminary data sheet

Product data sheet

Product
status

[2] [3]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Level

III

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Document Outline

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Document Outline

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