General description

The SC16C654B/654DB is a Quad Universal Asynchronous Receiver and Transmitter
(QUART) used for serial data communications. Its principal function is to convert parallel
data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s.
It comes with an Intel or Motorola interface.

The SC16C654B/654DB is pin compatible with the ST16C654 and TL16C754 and it will
power-up to be functionally equivalent to the 16C454. Programming of control registers
enables the added features of the SC16C654B/654DB. Some of these added features are
the 64-byte receive and transmit FIFOs, automatic hardware or software flow control and
infrared encoding/decoding. The selectable auto-flow control feature significantly reduces
software overload and increases system efficiency while in FIFO mode by automatically
controlling serial data flow using RTS output and CTS input signals. The
SC16C654B/654DB also provides DMA mode data transfers through FIFO trigger levels
and the TXRDY and RXRDY signals. (TXRDY and RXRDY signals are not available in the
HVQFN48 package.) On-board status registers provide the user with error indications,
operational status, and modem interface control. System interrupts may be tailored to
meet user requirements. An internal loop-back capability allows on-board diagnostics.

The SC16C654B/654DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, HVQFN48 and LFBGA64 packages.

On the HVQFN48 package, only channel C has all the modem pins. Channel A and
channel B have only RTS and CTS pins, and channel D does not have any modem pin.

Features

4 channel UART

5 V, 3.3 V and 2.5 V operation

Industrial temperature range (

C to +85

SC16C654B is pin and software compatible with the industry-standard
ST16C454/554, ST16C654, ST68C454/554, TL16C554

SC16C654DB is pin and software compatible with ST16C654D, and software
compatible with ST16C454/554, ST68C454/554, TL16C554

Up to 5 Mbit/s data rate at 5 V and 3.3 V and 3 Mbit/s at 2.5 V

5 V tolerant inputs

64-byte transmit FIFO

64-byte receive FIFO with error flags

Automatic software (Xon/Xoff)/hardware (RTS/CTS) flow control

Programmable Xon/Xoff characters

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte
FIFOs and infrared (IrDA) encoder/decoder

Rev. 02 -- 20 June 2005

Product data sheet

9397 750 14965

Product data sheet

Rev. 02 -- 20 June 2005

2 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Software selectable baud rate generator

Four selectable Receive and Transmit FIFO interrupt trigger levels

Standard modem interface or infrared (IrDA) encoder/decoder interface

Sleep mode

Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break)

Transmit, Receive, Line Status, and Data Set interrupts independently controlled

Fully programmable character formatting:

5, 6, 7, or 8-bit characters

Even, Odd, or No Parity formats

1, 1

, or 2-stop bit

Baud generation (DC to 5 Mbit/s)

False start-bit detection

Complete status reporting capabilities

3-state output TTL drive capabilities for bi-directional data bus and control bus

Line break generation and detection

Internal diagnostic capabilities:

Loop-back controls for communications link fault isolation

Prioritized interrupt system controls

Modem control functions (CTS, RTS, DSR, DTR, RI, CD).

Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

SC16C654BIA68

PLCC68

plastic leaded chip carrier; 68 leads

SOT188-2

SC16C654BIB64

LQFP64

plastic low profile quad flat package; 64 leads; body 10

1.4 mm

SOT314-2

SC16C654BIBM

LQFP64

plastic low profile quad flat package; 64 leads; body 7

1.4 mm

SOT414-1

SC16C654BIBS

HVQFN48

plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 6

0.85 mm

SOT778-3

SC16C654BIEC

LFBGA64

plastic low profile fine-pitch ball grid array package; 64 balls;
body 6

1.05 mm

SOT686-1

SC16C654DBIB64

LQFP64

plastic low profile quad flat package; 64 leads; body 10

1.4 mm

SOT314-2

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Pinning information

5.1 Pinning

Fig 3.

Pin configuration for PLCC68 (16 mode)

SC16C654BIA68

16 mode

DSRA

DSRD

CTSA

CTSD

DTRA

DTRD

GND

RTSA

RTSD

INTA

INTD

CSA

CSD

TXA

TXD

IOW

IOR

TXB

TXC

CSB

INTB

RTSB

GND

DTRB

CTSB

DSRB

CSC

INTC

RTSC

DTRC

CTSC

DSRC

CDB

GND

RIB

RXB

CLKSEL

CDA

RIA

RXA

16/68

XTAL1

XTAL2

INTSEL

RESET

RXRDY

TXRDY

GND

RXC

RIC

CDC

RXD

RID

CDD

002aaa873

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SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Fig 6.

Pin configuration for HVQFN48 (16 mode)

Fig 7.

Pin configuration for HVQFN48 (68 mode)

002aab568

SC16C654BIBS

16 mode

Transparent top view

DSRC

CTSB

CTSC

INTB

DTRC

CSB

TXB

RTSC

IOW

INTC

TXA

CSC

CSA

TXC

INTA

IOR

RTSA

TXD

CSD

CTSA

INTD

RXB

16/68

XTAL1

XTAL2

RESET

GND

RXC

RIC

CDC

RXA

GND

RXD

GND

terminal 1

index area

RTSB

002aab565

SC16C654BIBS

68 mode

Transparent top view

DSRC

CTSB

CTSC

n.c.

DTRC

TXB

RTSC

R/W

n.c.

TXA

TXC

IRQ

IOR

RTSA

TXD

CSD

CTSA

n.c.

RXB

16/68

XTAL1

XTAL2

RESET

GND

RXC

RIC

CDC

RXA

GND

RXD

GND

terminal 1

index area

RTSB

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SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

5.2 Pin description

Table 2:

Pin description

Symbol

Pin

Type Description

PLCC68 LQFP64 HVQFN48 LFBGA6

16/68

16/68 Interface type select (input with internal pull-up).
This input provides the 16 (Intel) or 68 (Motorola) bus
interface type select. The functions of IOR, IOW,
INTA to INTD, and CSA to CSD are re-assigned with the
logical state of this pin. When this pin is a logic 1, the
16 mode interface (16C654) is selected. When this pin is a
logic 0, the 68 mode interface (68C654) is selected. When
this pin is a logic 0, IOW is re-assigned to R/W, RESET is
re-assigned to RESET, IOR is not used, and INTA to INTD
are connected in a wire-OR configuration. The wire-OR
outputs are connected internally to the open-drain IRQ
signal output. This pin is not available on 64-pin packages
which operate in the 16 mode only.

Address 0 select bit. Internal registers address selection in
16 and 68 modes.

Address 1 select bit. Internal registers address selection in
16 and 68 modes.

Address 2 select bit. Internal registers address selection in
16 and 68 modes.

Address 3, Address 4 select bits. When the 68 mode is
selected, these pins are used to address or select individual
UARTs (providing CS is a logic 0). In the 16 mode, these
pins are re-assigned as chip selects, see CSB and CSC.
These pins are not available on 64-pin packages which
operate in the 16 mode only.

CDA

Carrier Detect (active LOW). These inputs are associated
with individual UART channels A through D. A logic 0 on this
pin indicates that a carrier has been detected by the modem
for that channel.

CDB

CDC

CDD

A10

CLKSEL

Clock Select. The 1

or 4

pre-scalable clock is selected by

this pin. The 1

clock is selected when CLKSEL is a logic 1

(connected to V

) or the 4

is selected when CLKSEL is a

logic 0 (connected to GND). MCR[7] can override the state
of this pin following reset or initialization (see MCR[7]). This
pin is not available on 64-pin packages which provide
MCR[7] selection only.

Chip Select (active LOW). In the 68 mode, this pin
functions as a multiple channel chip enable. In this case, all
four UARTs (A to D) are enabled when the CS pin is a
logic 0. An individual UART channel is selected by the data
contents of address bits A[3:4]. when the 16 mode is
selected (68-pin devices), this pin functions as CSA (see
definition under CSA, CSB). This pin is not available on
64-pin packages which operate in the 16 mode only.

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SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

CSA

Chip Select A, B, C, D (active LOW). This function is
associated with the 16 mode only, and for individual
channels `A' through `D'. When in 16 mode, these pins
enable data transfers between the user CPU and the
SC16C654B/654DB for the channel(s) addressed. Individual
UART sections (A, B, C, D) are addressed by providing a
logic 0 on the respective CSA to CSD pin. When the
68 mode is selected, the functions of these pins are
re-assigned. 68 mode functions are described under their
respective name/pin headings.

CSB

CSC

CSD

CTSA

Clear to Send (active LOW). These inputs are associated
with individual UART channels A through D. A logic 0 on the
CTS pin indicates the modem or data set is ready to accept
transmit data from the SC16C654B/654DB. Status can be
tested by reading MSR[4]. This pin only affects the transmit
or receive operations when Auto CTS function is enabled via
the Enhanced Feature Register EFR[7] for hardware flow
control operation.

CTSB

CTSC

K10

CTSD

B10

D0 to D2,
D3 to D7

66 to 68
, 1 to 5

53 to 55,
56 to 60

39 to 41,
42 to 46

B7, A7,
B6, A6,
B5, A5,
B4, A4

I/O

Data bus (bi-directional). These pins are the 8-bit, 3-state
data bus for transferring information to or from the controlling
CPU. D0 is the least significant bit and the first data bit in a
transmit or receive serial data stream.

DSRA

Data Set Ready (active LOW). These inputs are associated
with individual UART channels, A through D. A logic 0 on this
pin indicates the modem or data set is powered-on and is
ready for data exchange with the UART. This pin has no
effect on the UART's transmit or receive operation.

DSRB

DSRC

DSRD

DTRA

Data Terminal Ready (active LOW). These outputs are
associated with individual UART channels, A through D. A
logic 0 on this pin indicates that the SC16C654B/654DB is
powered-on and ready. This pin can be controlled via the
modem control register. Writing a logic 1 to MCR[0] will set
the DTR output to logic 0, enabling the modem. This pin will
be a logic 1 after writing a logic 0 to MCR[0], or after a reset.
This pin has no effect on the UART's transmit or receive
operation.

DTRB

DTRC

J10

DTRD

GND

6, 23,
40, 57

14, 28,
45, 61

21, 37, 47 B3, K7,

H1, D9

Signal and power ground.

INTA

Interrupt A, B, C, D (active HIGH). This function is
associated with the 16 mode only. These pins provide
individual channel interrupts INTA to INTD. INTA to INTD are
enabled when MCR[3] is set to a logic 1, interrupts are
enabled in the interrupt enable register (IER), and when an
interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer
empty, or when a modem status flag is detected. When the
68 mode is selected, the functions of these pins are
re-assigned. 68 mode functions are described under their
respective name/pin headings.

INTB

INTC

G10

INTD

D10

Table 2:

Pin description

...continued

Symbol

Pin

Type Description

PLCC68 LQFP64 HVQFN48 LFBGA6

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SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

INTSEL

Interrupt Select (active HIGH, with internal pull-down).
This function is associated with the 16 mode only. When the
16 mode is selected, this pin can be used in conjunction with
MCR[3] to enable or disable the 3-state interrupts,
INTA to INTD, or override MCR[3] and force continuous
interrupts. Interrupt outputs are enabled continuously by
making this pin a logic 1. Making this pin a logic 0 allows
MCR[3] to control the 3-state interrupt output. In this mode,
MCR[3] is set to a logic 1 to enable the 3-state outputs. This
pin is disabled in the 68 mode. Due to pin limitations on the
64-pin packages, this pin is not available. To cover this
limitation, the SC16C654DBIB64 version operates in the
continuous interrupt enable mode by bonding this pin to V

internally. The SC16C654BIB64 operates with MCR[3]
control by bonding this pin to GND.

IOR

Input/Output Read strobe (active LOW). This function is
associated with the 16 mode only. A logic 0 transition on this
pin will load the contents of an internal register defined by
address bits A[0:2] onto the SC16C654B/654DB data bus
(D[0:7]) for access by external CPU. This pin is disabled in
the 68 mode.

IOW

Input/Output Write strobe (active LOW). This function is
associated with the 16 mode only. A logic 0 transition on this
pin will transfer the contents of the data bus (D[0:7]) from the
external CPU to an internal register that is defined by
address bits A[0:2]. When the 68 mode is selected
(PLCC68), this pin functions as R/W (see definition under
R/W).

IRQ

Interrupt Request or Interrupt `A'. This function is
associated with the 68 mode only. In the 68 mode, interrupts
from UART channels A-D are wire-ORed internally to
function as a single IRQ interrupt. This pin transitions to a
logic 0 (if enabled by the interrupt enable register) whenever
a UART channel(s) requires service. Individual channel
interrupt status can be determined by addressing each
channel through its associated internal register, using CS
and A[3:4]. In the 68 mode, and external pull-up resistor
must be connected between this pin and V

. The function

of this pin changes to INTA when operating in the 16 mode
(see definition under INTA).

n.c.

21, 49,
52, 54,
55, 65

not connected

RESET,
RESET

Reset. In the 16 mode, a logic 1 on this pin will reset the
internal registers and all the outputs. The UART transmitter
output and the receiver input will be disabled during reset
time. (See

Section 7.11 "SC16C654B/654DB external reset

conditions"

for initialization details.) When 16/68 is a logic 0

(68 mode), this pin functions similarly, but as an inverted
reset interface signal, RESET.

Table 2:

Pin description

...continued

Symbol

Pin

Type Description

PLCC68 LQFP64 HVQFN48 LFBGA6

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5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

RIA

Ring Indicator (active LOW). These inputs are associated
with individual UART channels, A through D. A logic 0 on this
pin indicates the modem has received a ringing signal from
the telephone line. A logic 1 transition on this input pin will
generate an interrupt.

RIB

RIC

RID

RTSA

Request to Send (active LOW). These outputs are
associated with individual UART channels, A through D. A
logic 0 on the RTS pin indicates the transmitter has data
ready and waiting to send. Writing a logic 1 in the modem
control register MCR[1] will set this pin to a logic 0,
indicating data is available. After a reset this pin will be set to
a logic 1. This pin only affects the transmit and receive
operations when Auto RTS function is enabled via the
Enhanced Feature Register (EFR[6]) for hardware flow
control operation.

RTSB

RTSC

RTSD

C10

R/W

Read/Write strobe. This function is associated with the
68 mode only. This pin provides the combined functions for
Read or Write strobes.

Logic 1 = Read from UART register selected by CS and
A[0:4].

Logic 0 = Write to UART register selected by CS and A[0:4].

RXA

Receive data input RXA-RXD. These inputs are associated
with individual serial channel data to the
SC16C654B/654DB. The RX signal will be a logic 1 during
reset, idle (no data), or when the transmitter is disabled.
During the local loop-back mode, the RX input pin is
disabled and TX data is connected to the UART RX input
internally.

RXB

RXC

RXD

RXRDY

Receive Ready (active LOW). This function is associated
with 68-pin package only. RXRDY contains the wire-ORed
status of all four receive channel FIFOs, RXRDYA-RXRDYD.
A logic 0 indicates receive data ready status, that is, the
RHR is full, or the FIFO has one or more RX characters
available for unloading. This pin goes to a logic 1 when the
FIFO/RHR is empty, or when there are no more characters
available in either the FIFO or RHR. Individual channel RX
status is read by examining individual internal registers via
CS and A[0:4] pin functions.

TXA

Transmit data A, B, C, D. These outputs are associated
with individual serial transmit channel data from the
SC16C654B/654DB. The TX signal will be a logic 1 during
reset, idle (no data), or when the transmitter is disabled.
During the local loop-back mode, the TX output pin is
disabled and TX data is internally connected to the UART
RX input.

TXB

TXC

F10

TXD

E10

Table 2:

Pin description

...continued

Symbol

Pin

Type Description

PLCC68 LQFP64 HVQFN48 LFBGA6

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SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Functional description

The SC16C654B/654DB provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character. Data integrity is insured by attaching a parity bit to the data character. The
parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry
to provide all these functions is fairly complex, especially when manufactured on a single
integrated silicon chip. The SC16C654B/654DB represents such an integration with
greatly enhanced features. The SC16C654B/654DB is fabricated with an advanced
CMOS process to achieve low drain power and high speed requirements.

The SC16C654B/654DB is an upward solution that provides 64 bytes of transmit and
receive FIFO memory, instead of 16 bytes provided in the 16C554, or none in the 16C454.
The SC16C654B/654DB is designed to work with high speed modems and shared
network environments that require fast data processing time. Increased performance is
realized in the SC16C654B/654DB by the larger transmit and receive FIFOs. This allows
the external processor to handle more networking tasks within a given time. For example,
the SC16C554 with a 16-byte FIFO unloads 16 bytes of receive data in 1.53 ms. (This
example uses a character length of 11 bits, including start/stop bits at 115.2 kbit/s.) This
means the external CPU will have to service the receive FIFO at 1.53 ms intervals.
However, with the 64-byte FIFO in the SC16C654B/654DB, the data buffer will not require
unloading/loading for 6.1 ms. This increases the service interval, giving the external CPU
additional time for other applications and reducing the overall UART interrupt servicing

TXRDY

Transmit Ready (active LOW). This function is associated
with the 68-pin package only. TXRDY contains the
wire-ORed status of all four transmit channel FIFOs,
TXRDYA-TXRDYD. A logic 0 indicates a buffer ready status,
that is, at least one location is empty and available in one of
the TX channels (A to D). This pin goes to a logic 1 when all
four channels have no more empty locations in the TX FIFO
or THR. Individual channel TX status can be read by
examining individual internal registers via CS and A[0:4] pin
functions.

13, 47,
64

4, 21,
35, 52

2, 28

A8, B2,
J4, H10

Power supply inputs.

XTAL1

Crystal or external clock input. Functions as a crystal
input or as an external clock input. A crystal can be
connected between this pin and XTAL2 to form an internal
oscillator circuit; see

Figure 10

. Alternatively, an external

clock can be connected to this pin to provide custom data
rates; see

Section 6.9 "Programmable baud rate generator"

XTAL2

Output of the crystal oscillator or buffered clock. (See
also XTAL1.) Crystal oscillator output or buffered clock
output.

Table 2:

Pin description

...continued

Symbol

Pin

Type Description

PLCC68 LQFP64 HVQFN48 LFBGA6

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SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

time. In addition, the four selectable levels of FIFO trigger interrupt and automatic
hardware/software flow control is uniquely provided for maximum data throughput
performance, especially when operating in a multi-channel environment. The combination
of the above greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.

The SC16C654B/654DB combines the package interface modes of the 16C454/554 and
68C454/554 series on a single integrated chip. The 16 mode interface is designed to
operate with the Intel-type of microprocessor bus, while the 68 mode is intended to
operate with Motorola and other popular microprocessors. Following a reset, the
SC16C654B/654DB is downward compatible with the 16C454/554 or the 68C454/554,
dependent on the state of the interface mode selection pin, 16/68.

The SC16C654B/654DB is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and
up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the max speed is
3 Mbit/s). With a crystal of 14.7464 MHz, and through a software option, the user can
select data rates up to 460.8 kbit/s or 921.6 kbit/s, 8 times faster than the 16C554.

The rich feature set of the SC16C654B/654DB is available through internal registers.
Automatic hardware/software flow control, selectable transmit and receive FIFO trigger
levels, selectable TX and RX baud rates, infrared encoder/decoder interface, modem
interface controls, and a sleep mode are all standard features. MCR[5] provides a facility
for turning off (Xon) software flow control with any incoming (RX) character. In the
16 mode, INTSEL and MCR[3] can be configured to provide a software controlled or
continuous interrupt capability. Due to pin limitations of the 64-pin package, this feature is
offered by two different LQFP64 packages. The SC16C654DB operates in the continuous
interrupt enable mode by bonding INTSEL to V

internally. The SC16C654B operates in

conjunction with MCR[3] by bonding INTSEL to GND internally.

The PLCC68 SC16C654B package offers a clock select pin to allow system/board
designers to preset the default baud rate table. The CLKSEL pin selects the 1

or 4

pre-scalable baud rate generator table during initialization, but can be overridden following
initialization by MCR[7].

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5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.1 Interface options

Two user interface modes are selectable for the PLCC68 package. These interface modes
are designated as the `16 mode' and the `68 mode'. This nomenclature corresponds to the
early 16C454/554 and 68C454/554 package interfaces respectively.

6.1.1 The 16 mode interface

The 16 mode configures the package interface pins for connection as a standard
16 series (Intel) device and operates similar to the standard CPU interface available on
the 16C454/554. In the 16 mode (pin 16/68 = logic 1), each UART is selected with
individual chip select (CSx) pins, as shown in

Table 3

6.1.2 The 68 mode interface

The 68 mode configures the package interface pins for connection with Motorola, and
other popular microprocessor bus types. The interface operates similar to the
68C454/554. In this mode, the SC16C654B/654DB decodes two additional addresses,
A3-A4, to select one of the four UART ports. The A[3:4] address decode function is used
only when in the 68 mode (16/68 = logic 0), and is shown in

Table 4

Table 3:

Serial port channel selection, 16 mode interface

CSA

CSB

CSC

CSD

UART channel

none

Table 4:

Serial port channel selection, 68 mode interface

UART channel

n/a

none

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5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

6.2 Internal registers

The SC16C654B/654DB provides 17 internal registers for monitoring and control. These
registers are shown in

Table 5

. Twelve registers are similar to those already available in

the standard 16C554. These registers function as data holding registers (THR/RHR),
interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status
and control registers (LCR/LSR), modem status and control registers (MCR/MSR),
programmable data rate (clock) control registers (DLL/DLM), and a user accessible
scratchpad register (SPR). Beyond the general 16C554 features and capabilities, the
SC16C654B/654DB offers an enhanced feature register set (EFR, Xon/Xoff1-2) that
provides on-board hardware/software flow control. Register functions are more fully
described in the following paragraphs.

[1]

These registers are accessible only when LCR[7] is a logic 0.

[2]

These registers are accessible only when LCR[7] is a logic 1.

[3]

Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to `BFh'.

6.3 FIFO operation

The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. With SC16C554 devices, the user can set the receive trigger level, but not the
transmit trigger level. The SC16C654B/654DB provides independent trigger levels for both
receiver and transmitter. To remain compatible with SC16C554, the transmit interrupt
trigger level is set to 8 following a reset. It should be noted that the user can set the
transmit trigger levels by writing to the FCR register, but activation will not take place until
EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure
data is delivered to the external CPU. An interrupt is generated whenever the Receive

Table 5:

Internal registers decoding

Read mode

Write mode

General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)

[1]

Receive Holding Register

Transmit Holding Register

Interrupt Enable Register

Interrupt Status Register

FIFO Control Register

Line Control Register

Modem Control Register

Line Status Register

n/a

Modem Status Register

n/a

Scratchpad Register

Baud rate register set (DLL/DLM)

[2]

LSB of Divisor Latch

MSB of Divisor Latch

Enhanced register set (EFR, Xon/off 1-2)

[3]

Enhanced Feature Register

Xon1 word

Xon2 word

Xoff1 word

Xoff2 word

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Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached. (For a description of this timing, see

Section

6.4 "Hardware flow control"

6.4 Hardware flow control

When automatic hardware flow control is enabled, the SC16C654B/654DB monitors the
CTS pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow
control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C654B/654DB will suspend TX transmissions as soon as the stop bit of the
character in process is shifted out. Transmission is resumed after the CTS input returns to
a logic 0, indicating more data may be sent.

With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin will
return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below
the programmed trigger. However, under the above described conditions, the
SC16C654B/654DB will continue to accept data until the receive FIFO is full.

Remark: Hardware flow control is not supported on channel D in the HVQFN48 package.

6.5 Software flow control

When software flow control is enabled, the SC16C654B/654DB compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2 character
value(s). If received character(s) match the programmed values, the SC16C654B/654DB
will halt transmission (TX) as soon as the current character(s) has completed
transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5]) flags
will be set and the interrupt output pin (if receive interrupt is enabled) will be activated.
Following a suspension due to a match of the Xoff characters' values, the
SC16C654B/654DB will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C654B/654DB will resume operation and
clear the flags (ISR[4]). The SC16C654B/654DB offers a special Xon mode via MCR[5].
The initialized default setting of MCR[5] is a logic 0. In this state, Xoff and Xon will operate
as defined above. Setting MCR[5] to a logic 1 sets a special operational mode for the Xon
function. In this case, Xoff operates normally, however, transmission (Xon) will resume
with the next character received, that is, a match is declared simply by the receipt of an
incoming (RX) character.

Table 6:

RX trigger levels

Selected trigger level
(characters)

INT pin activation

Negate RTS or
send Xoff
(characters)

Assert RTS or
send Xon
(characters)

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5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the
SC16C654B/654DB compares two consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly.
Under the above described flow control mechanisms, flow control characters are not
placed (stacked) in the user accessible RX data buffer or FIFO.

In the event that the receive buffer is overfilling and flow control needs to be executed, the
SC16C654B/654DB automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C654B/654DB sends the Xoff1,2 characters
as soon as received data passes the programmed trigger level. To clear this condition, the
SC16C654B/654DB will transmit the programmed Xon1,2 characters as soon as receive
data drops below the programmed trigger level.

6.6 Special feature software flow control

A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
character is detected, it will be placed on the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[0:3]. Note that
software flow control should be turned off when using this special mode by setting
EFR[0:3] to a logic 0.

The SC16C654B/654DB compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set to
indicate detection of a special character. Although the Internal Register Table (

Table 8

)

shows each X-Register with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register bits LCR[0:1] define the
number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[0:1] also determine the number of bits that will be used for the special
character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive
character.

6.7 Xon any feature

A special feature is provided to return the Xoff flow control to the inactive state following its
activation. In this mode, any RX character received will return the Xoff flow control to the
inactive state so that transmissions may be resumed with a remote buffer. This feature is
more fully defined in

Section 6.5 "Software flow control"

6.8 Hardware/software and time-out interrupts

Three special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[5:7]. Care must be taken when handling these
interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C654B/654DB
will issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt
must be serviced prior to continuing operations. The LSR register provides the current
singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have
lowest interrupt priority. A condition can exist where a higher priority interrupt may mask
the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt
will the lower priority CTS/TRS interrupt(s) be reflected in the status register. Servicing the
interrupt without investigating further interrupt conditions can result in data errors.

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When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the
SC16C654B/654DB FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out
counter is reset at the center of each stop bit received or each time the receive holding
register (RHR) is read. The actual time-out value is 4 character time.

In the 16 mode for the PLCC68 package, the system/board designer can optionally
provide software controlled 3-state interrupt operation. This is accomplished by INTSEL
and MCR[3]. When INTSEL interface pin is left open or made a logic 0, MCR[3] controls
the 3-state interrupt outputs, INTA to INTD. When INTSEL is a logic 1, MCR[3] has no
effect on the INTA to INTD outputs, and the package operates with interrupt outputs
enabled continuously.

6.9 Programmable baud rate generator

The SC16C654B/654DB supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate
of 460.8 kbit/s.

A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is capable
of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as required for
supporting a 5 Mbit/s data rate. The SC16C654B/654DB can be configured for internal or
external clock operation. For internal clock oscillator operation, an industry standard
microprocessor crystal (parallel resonant/22 pF to 33 pF load) is connected externally
between the XTAL1 and XTAL2 pins; see

Figure 10

. Alternatively, an external clock can be

connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates; see

Table 7

The generator divides the input 16

clock by any divisor from 1 to (2

1). The

SC16C654B/654DB divides the basic external clock by 16. Further division of this 16

clock provides two table rates to support low and high data rate applications using the
same system design. After a hardware reset and during initialization, the

Fig 10. Crystal oscillator connection

002aaa870

C2
47 pF

XTAL1

XTAL2

1.8432 MHz

C1
22 pF

C2
33 pF

XTAL1

XTAL2

1.5 k

1.8432 MHz

C1
22 pF

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Philips Semiconductors

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5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

SC16C654B/654DB sets the default baud rate table according to the state of the CLKSEL
pin. A logic 1 on CLKSEL will set the 1

clock default, whereas logic 0 will set the 4

clock

default table. Following the default clock rate selection during initialization, the rate tables
can be changed by the internal register MCR[7]. Setting MCR[7] to a logic 1 when
CLKSEL is a logic 1 provides an additional divide-by-4, whereas setting MCR[7] to a
logic 0 only divides by 1; see

Table 7

and

Figure 11

. Customized baud rates can be

achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate
generator.

Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example in

Table 7

shows the

two selectable baud rate tables available when using a 7.3728 MHz crystal.

Table 7:

Baud rate generator programming table using a 7.3728 MHz clock

Output baud rate

User
16

clock divisor

DLM
program value
(HEX)

DLL
program value
(HEX)

MCR[7] = 1

MCR[7] = 0

Decimal

HEX

200

2304

900

300

1200

384

180

600

2400

192

1200

4800

2400

9600

4800

19.2 k

9600

38.4 k

19.2 k

76.8 k

38.4 k

153.6 k

57.6 k

230.4 k

115.2 k

460.8 k

Fig 11. Baud rate generator circuitry

BAUD RATE

GENERATOR

LOGIC

BAUDOUT

MCR[7] = 1

MCR[7] = 0

DIVIDE-BY-1

LOGIC

DIVIDE-BY-4

LOGIC

CLOCK

OSCILLATOR

LOGIC

002aaa208

XTAL1

XTAL2

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6.10 DMA operation

The SC16C654B/654DB FIFO trigger level provides additional flexibility to the user for
block mode operation. LSR[5:6] provide an indication when the transmitter is empty or has
an empty location(s). The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA
mode is de-activated (DMA Mode 0), the SC16C654B/654DB activates the interrupt
output pin for each data transmit or receive operation. When DMA mode is activated
(DMA Mode 1), the user takes the advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the preset trigger level. In this
mode, the SC16C654B/654DB sets the interrupt output pin when characters in the
transmit FIFOs are below the transmit trigger level, or the characters in the receive FIFOs
are above the receive trigger level.

Remark: DMA operation is not supported in the HVQFN48 package option.

6.11 Sleep mode

The SC16C654B/654DB is designed to operate with low power consumption. A special
sleep mode is included to further reduce power consumption when the chip is not being
used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C654B/654DB enters
the sleep mode, but resumes normal operation when a start bit is detected, a change of
state on any of the modem input pins RX, RI, CTS, DSR, CD, or a transmit data is
provided by the user. If the sleep mode is enabled and the SC16C654B/654DB is
awakened by one of the conditions described above, it will return to the sleep mode
automatically after the last character is transmitted or read by the user. In any case, the
sleep mode will not be entered while an interrupt(s) is pending. The SC16C654B/654DB
will stay in the sleep mode of operation until it is disabled by setting IER[4] to a logic 0.

6.12 Loop-back mode

The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the
normal modem interface pins are disconnected and reconfigured for loop-back internally.
MCR[0:3] register bits are used for controlling loop-back diagnostic testing. In the
loop-back mode, OP1 and OP2 in the MCR register (bits 2:3) control the modem RI and
CD inputs, respectively. MCR signals DTR and RTS (bits 0:1) are used to control the
modem DSR and CTS inputs, respectively. The transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally; see

Figure 12

. The CTS, DSR, CD, and RI are

disconnected from their normal modem control input pins, and instead are connected
internally to RTS, DTR, OP2 and OP1. Loop-back test data is entered into the transmit
holding register via the user data bus interface, D[0:7]. The transmit UART serializes the
data and passes the serial data to the receive UART via the internal loop-back connection.
The receive UART converts the serial data back into parallel data that is then made
available at the user data interface D[0:7]. The user optionally compares the received data
to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits.

In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read using
lower four bits of the Modem Status Register (MSR[0:3]) instead of the four Modem Status
Register bits 4:7. The interrupts are still controlled by the IER.

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Register descriptions

Table 8

details the assigned bit functions for the SC16C654B/654DB internal registers.

The assigned bit functions are more fully defined in

Section 7.1

through

Section 7.11

[1]

The value shown represents the register's initialized HEX value; X = not applicable.

[2]

These registers are accessible only when LCR[7] = 0.

[3]

These bits are only accessible when EFR[4] is set.

[4]

This function is not supported in the HVQFN48 package; TXRDY and RXRDY are removed.

[5]

The Special Register set is accessible only when LCR[7] is set to a logic 1.

[6]

Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to `BFh'.

Table 8:

SC16C654B/654DB internal registers

A2 A1 A0 Register Default

[1]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

General Register Set

[2]

RHR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

THR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

IER

CTS
interrupt

[3]

RTS
interrupt

[3]

Xoff
interrupt

[3]

Sleep
mode

[3]

modem
status
interrupt

receive
line status
interrupt

transmit
holding
register

receive
holding
register

FCR

RCVR
trigger
(MSB)

RCVR
trigger
(LSB)

TX
trigger
(MSB)

[3]

TX trigger
(LSB)

[3]

DMA
mode
select

[4]

XMIT
FIFO reset

RCVR
FIFO
reset

FIFO
enable

ISR

FIFOs
enabled

INT
priority
bit 4

INT
priority
bit 3

INT
priority
bit 2

INT
priority
bit 1

INT
priority
bit 0

INT
status

LCR

divisor
latch
enable

set
break

set parity even

parity

parity
enable

stop bits

word
length
bit 1

word
length
bit 0

MCR

Clock
select

[3]

IR
enable

[3]

Xon
Any

[3]

loop back OP2, INTx

enable

OP1

RTS

DTR

LSR

FIFO
data
error

trans.
empty

trans.
holding
empty

break
interrupt

framing
error

parity
error

overrun
error

receive
data
ready

MSR

DSR

CTS

DSR

CTS

SPR

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Special Register Set

[5]

DLL

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DLM

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

Enhanced Register Set

[6]

EFR

Auto
CTS

Auto
RTS

Special
char.
select

Enable
IER[4:7],
ISR[4:5],
FCR[4:5],
MCR[5:7]

Cont-3 Tx,
Rx Control

Cont-2 Tx,
Rx Control

Cont-1
Tx, Rx
Control

Cont-0
Tx, Rx
Control

Xon-1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Xon-2

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

Xoff-1

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Xoff-2

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

bit 8

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7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C654B/654DB and receive FIFO by reading the
RHR register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting clocks
at the 16

clock rate. After 7

clocks, the start bit time should be shifted to the center of

the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA to INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the
68 mode.

Table 9:

Interrupt Enable Register bits description

Bit

Symbol

Description

IER[7]

CTS interrupt.

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC16C654B/654DB issues an
interrupt when the CTS pin transitions from a logic 0 to a logic 1.

IER[6]

RTS interrupt.

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC16C654B/654DB issues an
interrupt when the RTS pin transitions from a logic 0 to a logic 1.

IER[5]

Xoff interrupt.

logic 0 = disable the software flow control, receive Xoff interrupt (normal
default condition)

logic 1 = enable the software flow control, receive Xoff interrupt. See

Section

6.5 "Software flow control"

for details.

IER[4]

Sleep mode.

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode. See

Section 6.11 "Sleep mode"

for details.

IER[3]

Modem Status Interrupt.

logic 0 = disable the modem status register interrupt (normal default
condition)

logic 1 = enable the modem status register interrupt

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7.2.1 IER versus Receive FIFO interrupt mode operation

When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are
enabled, the receive interrupts and register status will reflect the following:

The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops
below the programmed trigger level.

FIFO status will also be reflected in the user accessible ISR register when the FIFO
trigger level is reached. Both the ISR register status bit and the interrupt will be cleared
when the FIFO drops below the trigger level.

The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.

7.2.2 IER versus Receive/Transmit FIFO polled mode operation

When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C654B/654DB in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the
LSR, either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).

LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.

LSR[1:4] will provide the type of errors encountered, if any.

LSR[5] will indicate when the transmit FIFO is empty.

LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.

LSR[7] will indicate any FIFO data errors.

IER[2]

Receive Line Status interrupt.

logic 0 = disable the receiver line status interrupt (normal default condition)

logic 1 = enable the receiver line status interrupt

IER[1]

Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].

logic 0 = disable the transmitter empty interrupt (normal default condition)

logic 1 = enable the transmitter empty interrupt

IER[0]

Receive Holding Register interrupt. This interrupt will be issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.

logic 0 = disable the receiver ready interrupt (normal default condition)

logic 1 = enable the receiver ready interrupt

Table 9:

Interrupt Enable Register bits description

...continued

Bit

Symbol

Description

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7.3 FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO
trigger levels, and select the DMA mode.

7.3.1 DMA mode

7.3.1.1

Mode 0 (FCR bit 3 = 0)

Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C454 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with
a character.

7.3.1.2

Mode 1 (FCR bit 3 = 1)

Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is below the programmed trigger level. TXRDY remains a logic 0 as long
as one empty FIFO location is available. The receive interrupt is set when the receive
FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless
of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the
FIFO fill level is above the programmed trigger level.

7.3.2 FIFO mode

Table 10:

FIFO Control Register bits description

Bit

Symbol

Description

7:6

FCR[7] (MSB),
FCR[6] (LSB)

RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.

An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to

Table 11

5:4

FCR[5] (MSB),
FCR[4] (LSB)

TX trigger.

These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C654B/654DB will issue a transmit empty interrupt
when the number of characters in FIFO drops below the selected trigger
level. Refer to

Table 12

FCR[3]

DMA mode select.

logic 0 = set DMA mode `0' (normal default condition)

logic 1 = set DMA mode `1'

Transmit operation in mode `0': When the SC16C654B/654DB is in
the 16C454 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO
mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when
there are no characters in the transmit FIFO or transmit holding register,
the TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.

Receive operation in mode `0': When the SC16C654B/654DB is in
mode `0' (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1;
FCR[3] = logic 0) and there is at least one character in the receive FIFO,
the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a
logic 1 when there are no more characters in the receiver.

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Philips Semiconductors

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5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

3
(cont.)

FCR[3]
(continued)

Transmit operation in mode `1': When the SC16C654B/654DB is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0 when
the trigger level has been reached.

Receive operation in mode `1': When the SC16C654B/654DB is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has
been reached, or a Receive Time-Out has occurred, the RXRDY pin will
go to a logic 0. Once activated, it will go to a logic 1 after there are no
more characters in the FIFO.

FCR[2]

XMIT FIFO reset.

logic 0 = no FIFO transmit reset (normal default condition)

logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.

FCR[1]

RCVR FIFO reset.

logic 0 = no FIFO receive reset (normal default condition)

logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.

FCR[0]

FIFO enable.

logic 0 = disable the transmit and receive FIFO (normal default
condition)

logic 1 = enable the transmit and receive FIFO. This bit must be a `1'
when other FCR bits are written to, or they will not be
programmed.

Table 11:

RX trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level

Table 12:

TX trigger levels

FCR[5]

FCR[4]

TX FIFO trigger level (# of characters)

Table 10:

FIFO Control Register bits description

...continued

Bit

Symbol

Description

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.4 Interrupt Status Register (ISR)

The SC16C654B/654DB provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. Whenever the interrupt status register is read, the
interrupt status is cleared. However, it should be noted that only the current pending
interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the
interrupt status bits.

Table 13 "Interrupt source"

shows the data values (bits 0:5) for the six

prioritized interrupt levels and the interrupt sources associated with each of these interrupt
levels.

Table 13:

Interrupt source

Priority
level

ISR[5]

ISR[4]

ISR[3]

ISR[2]

ISR[1]

ISR[0]

Source of the interrupt

LSR (Receiver Line Status
Register)

RXRDY (Receive Data
Ready)

RXRDY (Receive Data
time-out)

TXRDY (Transmitter Holding
Register Empty)

MSR (Modem Status
Register)

RXRDY (Received Xoff
signal)/Special character

CTS, RTS change of state

Table 14:

Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs are enabled.

logic 0 or cleared = default condition

5:4

ISR[5:4]

INT priority bits 4:3. These bits are enabled when EFR[4] is set to a
logic 1. ISR[4] indicates that matching Xoff character(s) have been
detected. ISR[5] indicates that CTS, RTS have been generated. Note
that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon
character(s) are received.

logic 0 or cleared = default condition

3:1

ISR[3:1]

INT priority bits 2:0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3; see

Table 13

Logic 0 or cleared = default condition.

ISR[0]

INT status.

logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine

logic 1 = no interrupt pending (normal default condition)

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.

Table 15:

Line Control Register bits description

Bit

Symbol

Description

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhance
Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch and enhanced feature register enabled

LCR[6]

Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition

LCR[5]

Set parity. If the parity bit is enabled, LCR[5] selects the forced parity
format. Programs the parity conditions; see

Table 16

logic 0 = parity is not forced (normal default condition)

LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data

LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data

LCR[4]

Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,
LCR[4] selects the even or odd parity format.

logic 0 = odd parity is generated by forcing an odd number of logic 1s
in the transmitted data. The receiver must be programmed to check
the same format (normal default condition).

logic 1 = even parity is generated by forcing an even number of
logic 1s in the transmitted data. The receiver must be programmed to
check the same format.

LCR[3]

Parity enable. Parity or no parity can be selected via this bit.

logic 0 = no parity (normal default condition)

logic 1 = a parity bit is generated during the transmission, receiver
checks the data and parity for transmission errors

LCR[2]

Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length; see

Table 17

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be
transmitted or received; see

Table 18

logic 0 or cleared = default condition

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.6 Modem Control Register (MCR)

This register controls the interface with the modem or a peripheral device.

Table 16:

LCR[5] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

odd parity

even parity

forced parity `1'

forced parity `0'

Table 17:

LCR[2] stop bit length

LCR[2]

Word length

Stop bit length (bit times)

5, 6, 7, 8

6, 7, 8

Table 18:

LCR[1:0] word length

LCR[1]

LCR[0]

Word length

Table 19:

Modem Control Register bits description

Bit

Symbol

Description

MCR[7]

Clock select.

logic 0 = divide-by-1. The input clock (crystal or external) is divided by 16
and then presented to the Programmable Baud Rate Generator (BGR)
without further modification, that is, divide-by-1. (normal default condition).

logic 1 = divide-by-4. The divide-by-1 clock described in MCR[7] = a logic 0,
if further divided by four. Also see

Section 6.9 "Programmable baud rate

generator"

MCR[6]

IR enable.

logic 0 = enable the standard modem receive and transmit input/output
interface (normal default condition)

logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in
this mode, the TX/RX output/inputs are routed to the infrared
encoder/decoder. The data input and output levels will conform to the IrDA
infrared interface requirement. As such, while in this mode, the infrared TX
output will be a logic 0 during idle data conditions.

MCR[5]

Xon Any.

logic 0 = disable Xon Any function (for 16C554 compatibility) (normal default
condition)

logic 1 = enable Xon Any function. In this mode, any RX character received
will enable Xon

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

MCR[4]

Loop-back. Enable the local loop-back mode (diagnostics). In this mode the
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are
disconnected from the SC16C654B/654DB I/O pins. Internally the modem
data and control pins are connected into a loop-back data configuration; see

Figure 12

. In this mode, the receiver and transmitter interrupts remain fully

operational. The Modem Control Interrupts are also operational, but the
interrupts' sources are switched to the lower four bits of the Modem Control.
Interrupts continue to be controlled by the IER register.

logic 0 = disable loop-back mode (normal default condition)

logic 1 = enable local loop-back mode (diagnostics)

MCR[3]

OP2, INTx enable. Used to control the modem CD signal in the loop-back
mode.

logic 0 = forces INTA-INTD outputs to the 3-state mode during the 16 mode
(normal default condition). In the loop-back mode, sets OP2 (CD) internally
to a logic 1.

logic 1 = forces the INTA-INTD outputs to the active mode during the
16 mode. In the loop-back mode, sets OP2 (CD) internally to a logic 0.

MCR[2]

OP1. This bit is used in the Loop-back mode only. In the loop-back mode, this
bit is used to write the state of the modem RI interface signal via OP1.

MCR[1]

RTS

logic 0 = force RTS output to a logic 1 (normal default condition)

logic 1 = force RTS output to a logic 0

Automatic RTS may be used for hardware flow control by enabling EFR[6].
See

Table 22

MCR[0]

DTR

logic 0 = force DTR output to a logic 1 (normal default condition)

logic 1 = force DTR output to a logic 0

Table 19:

Modem Control Register bits description

...continued

Bit

Symbol

Description

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.7 Line Status Register (LSR)

This register provides the status of data transfers between the SC16C654B/654DB and
the CPU.

Table 20:

Line Status Register bits description

Bit

Symbol

Description

LSR[7]

FIFO data error.

logic 0 = no error (normal default condition)

logic 1 = at least one parity error, framing error or break indication is in the
current FIFO data. This bit is cleared when LSR register is read.

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a
logic 1 whenever the transmit holding register and the transmit shift register are
both empty. It is reset to logic 0 whenever either the THR or TSR contains a data
character. In the FIFO mode, this bit is set to `1' whenever the transmit FIFO and
transmit shift register are both empty.

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
indicates that the UART is ready to accept a new character for transmission. In
addition, this bit causes the UART to issue an interrupt to CPU when the THR
interrupt enable is set. The THR bit is set to a logic 1 when a character is
transferred from the transmit holding register into the transmitter shift register.
The bit is reset to a logic 0 concurrently with the loading of the transmitter
holding register by the CPU. In the FIFO mode, this bit is set when the transmit
FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

LSR[4]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = the receiver received a break signal (RX was a logic 0 for one
character frame time). In the FIFO mode, only one break character is loaded
into the FIFO.

LSR[3]

Framing error.

logic 0 = no framing error (normal default condition)

logic 1 = framing error. The receive character did not have a valid stop bit(s). In
the FIFO mode, this error is associated with the character at the top of the
FIFO.

LSR[2]

Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error. The receive character does not have correct parity
information and is suspect. In the FIFO mode, this error is associated with the
character at the top of the FIFO.

LSR[1]

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error. A data overrun error occurred in the receive shift
register. This happens when additional data arrives while the FIFO is full. In
this case, the previous data in the shift register is overwritten. Note that under
this condition, the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.

LSR[0]

Receive data ready.

logic 0 = no data in receive holding register or FIFO (normal default condition)

logic 1 = data has been received and is saved in the receive holding register or
FIFO

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.8 Modem Status Register (MSR)

This register provides the current state of the control interface signals from the modem, or
other peripheral device to which the SC16C654B/654DB is connected. Four bits of this
register are used to indicate the changed information. These bits are set to a logic 1
whenever a control input from the modem changes state. These bits are set to a logic 0
whenever the CPU reads this register.

[1]

Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated.

Table 21:

Modem Status Register bits description

Bit

Symbol

Description

MSR[7]

CD (active HIGH, logical 1). Normally this bit is the complement of the CD
input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR
register.

MSR[6]

RI (active HIGH, logical 1). Normally this bit is the complement of the RI input.
In the loop-back mode this bit is equivalent to the OP1 bit in the MCR register.

MSR[5]

DSR (active HIGH, logical 1). Normally this bit is the complement of the DSR
input. In loop-back mode this bit is equivalent to the DTR bit in the MCR
register.

MSR[4]

CTS. CTS functions as hardware flow control signal input if it is enabled via
EFR[7]. The transmit holding register flow control is enabled/disabled by
MSR[4]. Flow control (when enabled) allows starting and stopping the
transmissions based on the external modem CTS signal. A logic 1 at the CTS
pin will stop SC16C654B/654DB transmissions as soon as current character
has finished transmission. Normally MSR[4] is the complement of the CTS
input. However, in the loop-back mode, this bit is equivalent to the RTS bit in
the MCR register.

MSR[3]

[1]

logic 0 = no CD change (normal default condition)

logic 1 = the CD input to the SC16C654B/654DB has changed state since
the last time it was read. A modem Status Interrupt will be generated.

MSR[2]

[1]

logic 0 = no RI change (normal default condition)

logic 1 = the RI input to the SC16C654B/654DB has changed from a logic 0
to a logic 1. A modem Status Interrupt will be generated.

MSR[1]

DSR

[1]

logic 0 = no DSR change (normal default condition)

logic 1 = the DSR input to the SC16C654B/654DB has changed state since
the last time it was read. A Modem Status Interrupt will be generated.

MSR[0]

CTS

[1]

logic 0 = no CTS change (normal default condition)

logic 1 = the CTS input to the SC16C654B/654DB has changed state since
the last time it was read. A Modem Status Interrupt will be generated.

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

7.9 Scratchpad Register (SPR)

The SC16C654B/654DB provides a temporary data register to store 8 bits of user
information.

7.10 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register.

Bits 0 through 4 provide single or dual character software flow control selection. When the
Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential numbers.

Table 22:

Enhanced Feature Register bits description

Bit

Symbol

Description

EFR[7]

Auto CTS. Automatic CTS Flow Control.

logic 0 = automatic CTS flow control is disabled (normal default condition)

logic 1 = enable Automatic CTS flow control. Transmission will stop when
CTS goes to a logical 1. Transmission will resume when the CTS pin
returns to a logical 0.

EFR[6]

Auto RTS. Automatic RTS may be used for hardware flow control by enabling
EFR[6]. When Auto RTS is selected, an interrupt will be generated when the
receive FIFO is filled to the programmed trigger level and RTS will go to a
logic 1 at the next trigger level. RTS will return to a logic 0 when data is
unloaded below the next lower trigger level. The state of this register bit
changes with the status of the hardware flow control. RTS functions normally
when hardware flow control is disabled.

logic 0 = automatic RTS flow control is disabled (normal default condition)

logic 1 = enable Automatic RTS flow control

EFR[5]

Special Character Detect.

logic 0 = special character detect disabled (normal default condition)

logic 1 = special character detect enabled. The SC16C654B/654DB
compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to FIFO and ISR[4] will be set to
indicate detection of special character. Bit-0 in the X-registers corresponds
with the LSB bit for the receive character. When this feature is enabled, the
normal software flow control must be disabled (EFR[3:0] must be set to a
logic 0).

EFR[4]

Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4],
and MCR[7:5] can be modified and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.
This feature prevents existing software from altering or overwriting the
SC16C654B/654DB enhanced functions.

logic 0 = disable (normal default condition)

logic 1 = enable

3:0

EFR[3:0]

Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming these
bits. See

Table 23

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

[1]

When using software flow control the Xon/Xoff characters cannot be used for data transfer.

7.11 SC16C654B/654DB external reset conditions

Table 23:

Software flow control functions

[1]

Cont-3

Cont-2

Cont-1

Cont-0

TX, RX software flow controls

no transmit flow control

transmit Xon1/Xoff1

transmit Xon2/Xoff2

transmit Xon1 and Xon2/Xoff1 and Xoff2

no receive flow control

receiver compares Xon1/Xoff1

receiver compares Xon2/Xoff2

transmit Xon1/Xoff1

receiver compares Xon1 and Xon2, Xoff1 and Xoff2

transmit Xon2/Xoff2

receiver compares Xon1 and Xon2/Xoff1 and Xoff2

transmit Xon1 and Xon2/Xoff1 and Xoff2

receiver compares Xon1 and Xon2/Xoff1 and Xoff2

Table 24:

Reset state for registers

Register

Reset state

IER

IER[7:0] = 0

ISR

ISR[7:1] = 0; ISR[0] = 1

LCR

LCR[7:0] = 0

MCR

MCR[7:0] = 0

LSR

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR

MSR[7:4] = input signals; MSR[3:0] = 0

FCR

FCR[7:0] = 0

EFR

EFR[7:0] = 0

Table 25:

Reset state for outputs

Output

Reset state

TXA, TXB, TXC, TXD

HIGH

RTSA, RTSB, RTSC, RTSD

HIGH

DTRA, DTRB, DTRC, DTRD

HIGH

RXRDY

HIGH

TXRDY

LOW

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9397 750 14965

oninklijk

e Philips Electronics N.V

. 2005. All r

ights reser

ed.

Pr
oduct data sheet

Re
v

.
02 -- 20 J

une 2005

38 of 58

Philips Semiconductor

SC16C654B/654DB

5 V
,
3.3 V and 2.5 V quad U

, 5 Mbit/s (max.) with 64-b

yte FIFOs

Static c

haracteristics

[1]

Except XTAL2, V

= 1 V typical.

[2]

When using crystal oscillator. The use of an external clock will increase the sleep current.

[3]

Refer to

Table 2 "Pin description" on page 10

for a listing of pins having internal pull-up resistors.

Table 27:

Static characteristics

amb

C to +85

C; tolerance of V

10 %, unless otherwise specified.

Symbol

Parameter

Conditions

= 2.5 V

= 3.3 V

= 5.0 V

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

IL(CK)

LOW-level clock input voltage

0.3

0.45

0.3

0.6

0.5

0.6

IH(CK)

HIGH-level clock input voltage

1.8

2.4

3.0

LOW-level input voltage
(except XTAL1 clock)

0.3

0.65

0.3

0.8

0.5

0.8

HIGH-level input voltage
(except XTAL1 clock)

1.6

2.0

2.2

LOW-level output voltage
on all outputs

[1]

= 5 mA

(data bus)

0.4

= 4 mA

(other outputs)

0.4

= 2 mA

(data bus)

0.4

= 1.6 mA

(other outputs)

0.4

HIGH-level output voltage

5 mA

(data bus)

2.4

1 mA

(other outputs)

2.0

800

(data bus)

1.85

400

(other outputs)

1.85

LIL

LOW-level input leakage
current

clock leakage

supply current

f = 5 MHz

4.5

CCsleep

sleep current

[2]

200

input capacitance

pu(int)

internal pull-up resistance

[3]

500

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

10. Dynamic characteristics

Table 28:

Dynamic characteristics

amb

C to +85

C; tolerance of V

10 %, unless otherwise specified.

Symbol

Parameter

Conditions

= 2.5 V

= 3.3 V

= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

, t

clock pulse duration

XTAL

oscillator/clock frequency

[1] [2]

MHz

address setup time

address hold time

IOR delay from chip select

IOR strobe width

25 pF load

chip select hold time from
IOR

read cycle delay

25 pF load

12d

delay from IOR to data

25 pF load

12h

data disable time

25 pF load

13d

IOW delay from chip select

13w

IOW strobe width

13h

chip select hold time from
IOW

15d

write cycle delay

16s

data setup time

16h

data hold time

17d

delay from IOW to output

25 pF load

100

18d

delay to set interrupt from
Modem input

25 pF load

100

19d

delay to reset interrupt
from IOR

25 pF load

100

20d

delay from stop to
set interrupt

RCLK

[3]

RCLK

[3]

RCLK

[3]

21d

delay from IOR to
reset interrupt

25 pF load

100

22d

delay from start to set
interrupt

100

23d

delay from IOW to transmit
start

RCLK

[3]

24T

RCLK

[3]

RCLK

[3]

24T

RCLK

[3]

RCLK

[3]

24T

RCLK

[3]

24d

delay from IOW to
reset interrupt

100

25d

delay from stop to
set RXRDY

RCLK

[3]

RCLK

[3]

RCLK

[3]

26d

delay from IOR to
reset RXRDY

100

27d

delay from IOW to
set TXRDY

100

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

[1]

Applies to external clock, crystal oscillator max 24 MHz.

[2]

Maximum frequency =

[3]

RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.

28d

delay from start to reset
TXRDY

RCLK

[3]

RCLK

[3]

RCLK

[3]

30s

address setup time

30w

chip select strobe width

25 pF load

[1]

30h

address hold time

30d

read cycle delay

25 pF load

31d

delay from CS to data

25 pF load

31h

data disable time

25 pF load

32s

write strobe setup time

32h

write strobe hold time

32d

write cycle delay

33s

data setup time

33h

data hold time

RESET

RESET pulse width

200

baud rate divisor

Table 28:

Dynamic characteristics

...continued

amb

C to +85

C; tolerance of V

10 %, unless otherwise specified.

Symbol

Parameter

Conditions

= 2.5 V

= 3.3 V

= 5.0 V

Unit

Min

Max

Min

Max

Min

Max

-------

9397 750 14965

Product data sheet

Rev. 02 -- 20 June 2005

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

11. Package outline

Fig 27. Package outline SOT188-2 (PLCC68)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

SOT188-2

detail X

(A )

Z D

Z E

pin 1 index

112E10

MS-018

EDR-7319

10 mm

scale

99-12-27
01-11-14

PLCC68: plastic leaded chip carrier; 68 leads

SOT188-2

UNIT

4.57
4.19

0.51

3.3

0.53
0.33

0.021
0.013

1.27

2.16

0.18

0.1

0.18

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

24.33
24.13

25.27
25.02

2.16

0.81
0.66

1.22
1.07

0.180
0.165

0.02

0.13

0.25

0.01

0.05

0.085

0.007 0.004

0.007

1.44
1.02

0.057
0.040

0.958
0.950

24.33
24.13

0.958
0.950

0.995
0.985

25.27
25.02

0.995
0.985

23.62
22.61

0.93
0.89

23.62
22.61

0.93
0.89

0.085

0.032
0.026

0.048
0.042

inches

min.

max.

(1)

max.

(1)

max.

9397 750 14965

Product data sheet

Rev. 02 -- 20 June 2005

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Fig 28. Package outline SOT314-2 (LQFP64)

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

1.6

0.20
0.05

1.45
1.35

0.25

0.27
0.17

0.18
0.12

10.1

9.9

0.5

12.15
11.85

1.45
1.05

7
0

0.12

0.1

0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75
0.45

SOT314-2

MS-026

136E10

00-01-19
03-02-25

(1)

10.1

9.9

12.15
11.85

1.45
1.05

detail X

(A )

Z D

Z E

pin 1 index

2.5

5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

9397 750 14965

Product data sheet

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Fig 29. Package outline SOT414-1 (LQFP64)

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

1.6

0.15
0.05

1.45
1.35

0.25

0.23
0.13

0.20
0.09

7.1
6.9

0.4

9.15
8.85

0.64
0.36

7
0

0.08

0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75
0.45

SOT414-1

136E06

MS-026

00-01-19
03-02-20

(1)

7.1
6.9

9.15
8.85

0.64
0.36

detail X

(A )

Z D

Z E

pin 1 index

2.5

5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm

SOT414-1

9397 750 14965

Product data sheet

Rev. 02 -- 20 June 2005

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Fig 30. Package outline SOT778-3 (HVQFN48)

terminal 1
index area

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

SOT778-3

- - -

SOT778-3

04-06-16
04-06-23

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included

DIMENSIONS (mm are the original dimensions)

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;
48 terminals; body 6 x 6 x 0.85 mm

detail X

1/2 e

2.5

5 mm

scale

UNIT

0.05
0.00

0.25
0.15

6.1
5.9

3.95
3.65

0.5
0.3

(1)

max

(1)

3.95
3.65

0.1

4.4

0.4

0.2

0.05

0.1

9397 750 14965

Product data sheet

Rev. 02 -- 20 June 2005

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Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

Fig 31. Package outline SOT686-1 (LFBGA64)

0.5

UNIT

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

02-03-11

IEC

JEDEC

JEITA

1.5

0.3
0.2

1.20
0.95

6.1
5.9

0.35
0.25

0.08

0.1

4.5

DIMENSIONS (mm are the original dimensions)

SOT686-1

- - -

0.15

0.05

2.5

5 mm

scale

SOT686-1

LFBGA64: plastic low profile fine-pitch ball grid array package; 64 balls; body 6 x 6 x 1.05 mm

max.

detail X

9 10

ball A1
index area

y1 C

1/2

9397 750 14965

Product data sheet

Rev. 02 -- 20 June 2005

53 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

12. Soldering

12.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.

12.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215

C to 270

C depending on solder paste

material. The top-surface temperature of the packages should preferably be kept:

below 225

C (SnPb process) or below 245

C (Pb-free process)

for all BGA, HTSSON..T and SSOP..T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a volume

350 mm

so called

thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free process) for packages with a

thickness < 2.5 mm and a volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

12.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically
developed.

If wave soldering is used the following conditions must be observed for optimal results:

Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

9397 750 14965

Product data sheet

Rev. 02 -- 20 June 2005

54 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45

angle to

the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250

or 265

C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.

12.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300

When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270

C and 320

12.5 Package related soldering information

[1]

For more detailed information on the BGA packages refer to the

(LF)BGA Application Note (AN01026);

order a copy from your Philips Semiconductors sales office.

[2]

All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated Circuit

Packages; Section: Packing Methods.

[3]

These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217

C measured in the atmosphere of the reflow oven. The package

body peak temperature must be kept as low as possible.

Table 29:

Suitability of surface mount IC packages for wave and reflow soldering methods

Package

[1]

Soldering method

Wave

Reflow

[2]

BGA, HTSSON..T

[3]

, LBGA, LFBGA, SQFP,

SSOP..T

[3]

, TFBGA, VFBGA, XSON

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

[4]

suitable

PLCC

[5]

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

[5] [6]

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

[7]

suitable

CWQCCN..L

[8]

, PMFP

[9]

, WQCCN..L

[8]

not suitable

9397 750 14965

Product data sheet

Rev. 02 -- 20 June 2005

55 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

[4]

These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.

[5]

If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6]

Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7]

Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8]

Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.

[9]

Hot bar soldering or manual soldering is suitable for PMFP packages.

13. Abbreviations

Table 30:

Abbreviations

Acronym

Description

BRG

Baud Rate Generator

CPU

Central Processing Unit

DMA

Direct Memory Access

FIFO

First-In, First-Out

ISDN

Integrated Service Digital Network

LSB

Least Significant Bit

MSB

Most Significant Bit

QUART

4-channel (Quad) Universal Asynchronous Receiver and Transmitter

UART

Universal Asynchronous Receiver and Transmitter

9397 750 14965

Product data sheet

Rev. 02 -- 20 June 2005

56 of 58

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

14. Revision history

Table 31:

Revision history

Document ID

Release date

Data sheet status

Change
notice

Doc. number

Supersedes

SC16C654B_654DB_2

20050620

Product data sheet

9397 750 14965

SC16C654B_654DB_1

Modifications:

Section 1 "General description"

2nd paragraph: added 6th sentence.

3rd paragraph: added HVQFN48 and LFBGA64 package options, and added second

sentence.

Table 1 "Ordering information"

: added HVQFN48, LFBGA64, and LQFP64 (SOT414-1)

package options.

Figure 5 "Pin configuration for LQFP64"

: added SC16C654BIBM option

Added

Figure 6 "Pin configuration for HVQFN48 (16 mode)"

Figure 7 "Pin configuration for

HVQFN48 (68 mode)"

Figure 8 "Pin configuration for LFBGA64"

and

Figure 9 "Ball mapping

for LFBGA64"

Table 2 "Pin description"

: added columns for HVQFN48 and LFBGA64 package types

moved

Section 6.1.1 "The 16 mode interface"

(was Section 6.2) and

Section 6.1.2 "The

68 mode interface"

(was Section 6.3) to be sub-sections of

Section 6.1 "Interface options"

Section 6.4 "Hardware flow control"

: added `Remark' following second paragraph.

Section 6.10 "DMA operation"

: added `Remark' following first paragraph.

Table 8 "SC16C654B/654DB internal registers"

: added (new)

Table note 4

and its reference

at FCR[3].

Table 27 "Static characteristics"

descriptive line following title: changed `V

= 2.5 V, 3.3 V or 5.0 V

10 %,' to `tolerance

of V

10 %;'

added `V

= ` to the limits' column headings

Table 28 "Dynamic characteristics"

descriptive line following title: changed `V

= 2.5 V, 3.3 V or 5.0 V

10 %,' to `tolerance

of V

10 %;'

added `V

= ` to the limits' column headings

baud rate divisor Max. columns: changed `2

1 T

RCLK

' to `(2

1)'; deleted `ns' from

Unit column (N is a number).

Section 11 "Package outline"

: added

Figure 29 "Package outline SOT414-1 (LQFP64)"

Figure 30 "Package outline SOT778-3 (HVQFN48)"

, and

Figure 31 "Package outline

SOT686-1 (LFBGA64)"

Added

Section 13 "Abbreviations" on page 55

Section 18 "Trademarks"

re-written.

SC16C654B_654DB_1

20050209

Product data sheet

9397 750 13115

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

9397 750 14965

Product data sheet

Rev. 02 -- 20 June 2005

57 of 58

15. Data sheet status

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

[2]

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Definitions

Short-form specification -- The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.

Application information -- Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.

17. Disclaimers

Life support -- These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status `Production'),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.

18. Trademarks

Notice -- All referenced brands, product names, service names and
trademarks are the property of their respective owners.

19. Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com

Level

Data sheet status

[1]

Product status

[2] [3]

Definition

Objective data

Development

This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.

Date of release: 20 June 2005

Document number: 9397 750 14965

Published in The Netherlands

Philips Semiconductors

SC16C654B/654DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

20. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 5

5.1

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10

Functional description . . . . . . . . . . . . . . . . . . 14

6.1

Interface options . . . . . . . . . . . . . . . . . . . . . . . 16

6.1.1

The 16 mode interface . . . . . . . . . . . . . . . . . . 16

6.1.2

The 68 mode interface . . . . . . . . . . . . . . . . . . 16

6.2

Internal registers . . . . . . . . . . . . . . . . . . . . . . . 17

6.3

FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 17

6.4

Hardware flow control . . . . . . . . . . . . . . . . . . . 18

6.5

Software flow control . . . . . . . . . . . . . . . . . . . 18

6.6

Special feature software flow control . . . . . . . 19

6.7

Xon any feature . . . . . . . . . . . . . . . . . . . . . . . 19

6.8

Hardware/software and time-out interrupts. . . 19

6.9

Programmable baud rate generator . . . . . . . . 20

6.10

DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 22

6.11

Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.12

Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 22

Register descriptions . . . . . . . . . . . . . . . . . . . 24

7.1

Transmit (THR) and Receive (RHR) Holding
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.2

Interrupt Enable Register (IER) . . . . . . . . . . . 25

7.2.1

IER versus Receive FIFO interrupt mode
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.2.2

IER versus Receive/Transmit FIFO polled mode
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.3

FIFO Control Register (FCR) . . . . . . . . . . . . . 27

7.3.1

DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.3.1.1

Mode 0 (FCR bit 3 = 0) . . . . . . . . . . . . . . . . . . 27

7.3.1.2

Mode 1 (FCR bit 3 = 1) . . . . . . . . . . . . . . . . . . 27

7.3.2

FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.4

Interrupt Status Register (ISR) . . . . . . . . . . . . 29

7.5

Line Control Register (LCR) . . . . . . . . . . . . . . 30

7.6

Modem Control Register (MCR) . . . . . . . . . . . 31

7.7

Line Status Register (LSR) . . . . . . . . . . . . . . . 33

7.8

Modem Status Register (MSR). . . . . . . . . . . . 34

7.9

Scratchpad Register (SPR) . . . . . . . . . . . . . . 35

7.10

Enhanced Feature Register (EFR) . . . . . . . . . 35

7.11

SC16C654B/654DB external reset conditions 36

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 37

Static characteristics. . . . . . . . . . . . . . . . . . . . 38

Dynamic characteristics . . . . . . . . . . . . . . . . . 39

10.1

Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . 41

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 48

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12.1

Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12.2

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 53

12.3

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 53

12.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 54

12.5

Package related soldering information . . . . . . 54

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 55

Revision history . . . . . . . . . . . . . . . . . . . . . . . 56

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 57

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Contact information . . . . . . . . . . . . . . . . . . . . 57

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SC16C654DB

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SC16C654DB