Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

853-1682 19973

DESCRIPTION

The Philips Semiconductors SC68C562 Dual Universal Serial
Communications Controller (CDUSCC) is a single-chip CMOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SC68C562 interfaces to the 68000
MPUs via asynchronous bus control signals and is capable of
program-polled, interrupt driven, block-move or DMA data transfers.

The SC68C562 is hardware (pin) and software (Register)
compatible with SCN68562 (NMOS version). It will automatically
configure to NMOS DUSCC register map on power-up or reset.

The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multifunction counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides 16 common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock.

This makes the CDUSCC well suited for dual speed channel
applications. Data rates up to 10Mb/s are supported.

Each transmitter and each receiver is serviced by a 16 byte FIFO.
The receiver FIFO also stores 9 status bits for each character
received; the transmit FIFO is able to store transmitter commands
with each byte. This permits reading and writing of up to 16 bytes at
a time, thus minimizing the

potential for transmitter underrun, receiver overrun and reducing
interrupt or DMA overhead.

In addition, a flow control capability is provided to disable a remote
transmitter when the FIFO of the local receiving device is full. Two
modem control inputs (DCD and CTS) and three modem control
outputs (RTS and two general purpose) are provided. Because the
modem control inputs are general purpose in nature, they can be
optionally programmed for other functions. This document contains
the electrical specifications for the SC68C562. Refer to the CMOS
Dual Universal Serial Communications Controller (CDUSCC) User
Manual for a complete operational description of this product.

FEATURES

Full hardware and software upward compatibility with previous
NMOS device

General Features

Dual full-duplex synchronous/ asynchronous receiver and
transmitter

Low power CMOS process

Multiprotocol operation

BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,

etc.

COP: BISYNC, DDCMP

ASYNC: 58 bits plus optional parity

Sixteen character receiver and transmitter FIFOs

0 to 10MHz data rate

Programmable bit rate for each receiver and transmitter selectable
from:

19 fixed rates: 50 to 64k baud

One user-defined rate derived from programmable

counter/timer

External 1X or 16X clock

Digital phase-locked loop

Parity and FCS (frame check sequence LRC or CRC) generation
and checking

Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester

Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback

Programmable data transfer mode: polled, interrupt, DMA, wait

DMA interface

Compatible with the Philips Semiconductors SCB68430 Direct

Memory Access Interface (DMAI) and other DMA controllers

Single- or dual-address dual transfers

Half- or full-duplex operation

Automatic frame termination on counter/timer terminal count or

DMA DONE

Transmit path clear status

Interrupt capabilities

Daisy chain option

Vector output (fixed or modified by status)

Programmable internal priorities

Interrupt at any FIFO fill level

Maskable interrupt conditions

FIFO'd status bits

Watchdog timer

Multi-function programmable 16-bit counter/timer

Bit rate generator

Event counter

Count received or transmitted characters

Delay generator

Automatic bit length measurement

Modem controls

RTS, CTS, DCD, and up to four general I/O pins per channel

CTS and DCD programmable auto-enables for Tx and Rx

Programmable interrupt on change of CTS or DCD

On-chip oscillator for crystal

TTL compatible

Single +5V power supply

Asynchronous Mode Features

Character length: 5 to 8 bits

Odd or even parity, no parity, or force parity

Up to two stop bits programmable in 1/16-bit increments

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

1X or 16X Rx and Tx clock factors

Parity, overrun, and framing error detection

False start bit detection

Start bit search 1/2-bit time after framing error detection

Break generation with handshake for counting break characters

Detection of start and end of received break

Character compare with optional interrupt on match

Transmits up to 10Mb/s at 1X and receive up to 1Mb/s at 16X
data rates

Character-Oriented Protocol Features

Character length: 5 to 8 bits

Odd or even parity, no parity, or force parity

LRC or CRC generation and checking

Optional opening PAD transmission

One or two SYN characters

External sync capability

SYN detection and optional stripping

SYN or MARK line fill on underrun

Idle in MARK or SYNs

Parity, FCS, overrun, and underrun error detection

BISYNC Features

EBCDIC or ASCII header, text and control messages

SYN, DLE stripping

EOM (end of message) detection and transmission

Auto transparent mode switching

Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)

Control character sequence detection for both transparent and
normal text

Bit-Oriented Protocol Features

Character length: 5 to 8 bits

Detection and transmission of residual character: 07 bits

Automatic switch to programmed character length for I field

Zero insertion and deletion

Optional opening PAD transmission

Detection and generation of FLAG, ABORT, and IDLE bit patterns

Detection and generation of shared (single) FLAG between
frames

Detection of overlapping (shared zero) FLAGs

ABORT, ABORT-FLAGs, or FCS FLAGs line fill on underrun

Idle in MARK or FLAGs

Secondary address recognition including group and global
address

Single- or dual-octet secondary address

Extended address and control fields

Short frame rejection for receiver

Detection and notification of received end of message

CRC generation and checking

SDLC loop mode capability

ORDERING INFORMATION

DESCRIPTION

= +5V

10%,

= 0 to +70

= +5V

10%,

= 40 to +85

DWG #

DESCRIPTION

Serial Data Rate =

10Mbps Maximum

Serial Data Rate =

8Mbps Maximum

DWG #

48-Pin Plastic Dual In-Line Package (DIP)

SC68C562C1N

Not available

SOT240-1

52-Pin Plastic Leaded Chip Carrier (PLCC) Package

SC68C562C1A

SC68C562A8A

SOT238-3

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNIT

SYMBOL

PARAMETER

COMMERCIAL

INDUSTRIAL

UNIT

Operating ambient temperature

0 to +70

-40 to +85

STG

Storage temperature

-65 to +150

Voltage from V

to GND

0.5 to +7.0

Voltage from any pin to ground

0.5 to V

+0.5

0.5 to V

+0.5

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

PIN CONFIGURATIONS

IACKN

RTxDAKBN/

IRQN

RESETN

RTSBN/

TRxCB

RTxCB

DCDBN/

TxDAKBN/

RTxDRQBN/

TxDRQBN/

CTSBN/LCBN

DTACKN

DTCN

GND

CSN

DONEN

CTSAN/LCAN

TxDRQAN/

RTxDRQAN/

TxDAKAN/

TxDA

DCDAN/

RTxCA

TRxCA

RTSAN/

X2/IDCN

X1/CLK

RTxDAKAN/

VDD

N PACKAGE

GPI1BN

SYNOUTBN

SYNIBN

RxDB

TxDB

GPI2BN

GPO1BN

GPO2BN/RTSBN

R/WN

GPO2AN/RTSAN

GPO1AN

GPI2AN

Rxda

SYNIAN

SYNOUTAN

GPI1AN

DIP

Pin Function Pin Function

IACKN

27 CSN

28 R/WN

29 DONEN

30 D3

RTxDAKBN/

31 D2

GPI1BN

32 D1

IRQN

33 D0

34 NC

RESETN

35 CTSAN/LCAN

RTSBN/

36 TxDRQAN/

SYNOUTBN

GPO2AN/RTSAN

10 TRxCB

37 RTxDRQAN/

RTxCB

GPO1AN

12 DCDBN/

38 TxDAKAN/

SYNIBN

GPI2AN

13 NC

39 TxDA

14 RxDB

40 RxDA

15 TxDB

41 NC

16 TxDAKBN/

42 DCDAN/

GPI2BN

SYNIAN

17 RTxDRQBN/

43 RTxCA

GPO1BN

44 TRxCA

18 TxDRQBN/

45 RTSAN/

GPO2BN/RTSBN

SYNOUTAN

19 CTSBN/LCBN

46 X2/IDCN

20 D7

47 X1/CLK

21 D6

48 RTxDAKAN/

22 D5

GPI1AN

23 D4

49 A6

24 DTACKN

50 A5

25 DTCN

51 A4

26 GND

52 VDD

PLCC

TOP VIEW

INDEX

CORNER

A PACKAGE

SD00222

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

BLOCK DIAGRAM

CHANNEL MODE

AND TIMING A/B

CTCRA/B

CTPRHA/B

CTPRLA/B

INTERNAL

BUS

DPLL CLK

MUX A/B

DPLL A/B

BRG

COUNTER/

TIMER A/B

C/T CLK

MUX A/B

CTHA/B

CTLA/B

TRANSMIT A/B

TRANS CLK

MUX

TPRA/B

TTRA/B

TX SHIFT

REG

CRC

GEN

TRANSMIT

16 DEEP

FIFO

SPEC CHAR

GEN LOGIC

RECEIVER A/B

RPRA/B

RTRA/B

S1RA/B

RCVR CLK

MUX

S2RA/B

RCVR

SHIFT REG

RECEIVER

16 DEEP

FIFO

CRC

ACCUM

BISYNC

COMPARE

LOGIC

TxD A/B

RxD A/B

INTERFACE/

OPERATION

CONTROL

ICTSRA/B

GSR

CMR1A/B

ADDRESS

DECODE

DMA

CONTROL

CMR2A/B

OMRA/B

R/W

DECODE

CCRA/B

PCRA/B

RSRA/B

TRSRA/B

ICRA/B

IERA/B

IVR

IVRM

INTERRRUPT

CONTROL

OSCILLATOR

SPECIAL

FUNCTION

PINS

DMA INTERFACE

MPU

INTERFACE

BUS

BUFFER

D0-D7

DTACKN

RWN

A1-A6

CSN

RESETN

RTxDRQAN/GPO1AN

RTxDRQBN/GPO1BN

TxDRQAN/GPO2AN

TxDRQBN/GPO2BN

RTxDAKAN/GPI1AN

RTxDAKBN/GPI1BN

TxDAKAN/GPI2AN

TxDAKBN/GPI2BN

DTCN

DONEN

TRxCA/B

RTxCA/B

RTSBN/SYNOUTBN

RTSAN/SYNOUTAN

CTSA/BN

DCDBN/SYNIBN

DCDAN/SYNIAN

IRQN

IACKN

X1/CLK

X2/IDCN

DUSCC

LOGIC

CONTROL

A7 CONTROL

LOGIC

TRCR A/B

FTLR A/B

TRMR A/B

CID

IER1

IER2

IER3

RFLRA/B

TELRA/B

SD00253

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

PIN DESCRIPTION

MNEMONIC

PIN NO.

TYPE

NAME AND FUNCTION

MNEMONIC

DIP

PLCC

TYPE

NAME AND FUNCTION

A1A6

4-2,

47-45

4-2,

51-49

Address Lines: Active-high. Address inputs which specify which of the internal registers
is accessed for read/write operation.

D0D7

31-28,

21-18

33-30,

23-20

I/O

Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command and status transfers between the CPU and the CDUSCC take place over
this bus. The data bus is enabled when CSN and R/WN or during interrupt acknowledge
cycles and single address DMA acknowledge cycles.

R/WN

Read/Write: A high input indicates a read cycle and a low indicates a write cycle when
CEN is active.

CSN

Chip Select: Active-low input. When active, data transfers between the CPU and the
CDUSCC are enabled on D0D7 as controlled by R/WN and A1A6 inputs. When CSN is
high, the data lines are placed in the 3-State condition (except during interrupt
acknowledge cycles and single address DMA transfers).

IRQN

Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of
any enabled interrupting condition. The CPU can read the general status register to
determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle
to cause the CDUSCC to output an interrupt vector on the data bus.

IACKN

Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds
by either forcing the bus into high-impedance, placing a vector number, call instruction or
zero on the data bus. The vector number can be modified or unmodified by the status. If
no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.

X1/CLK

Crystal or External Clock: When using the crystal oscillator, the crystal is connected

between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input.

This clock is used to drive the internal bit rate generator, as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals. When a crystal is
used, a capacitor must be connected from this pin to ground.

X2/IDCN

Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal
is connected between pins X1 and X2. This pin can be programmed to provide an
interrupt daisy chain active-low output which propagates the IACKN signal to lower priority
devices, if no active interrupt is pending. This pin should be left floating when an external
clock is used on X1 and X2 is not used as an interrupt daisy chain output. When a crystal
is used, a capacitor must be connected from this pin to ground.

RESETN

Master Reset: Active-low. A low on this pin resets the transmitters and receivers and
resets the registers shown in Table 1 of the CDUSCC Users' Guide. Reset is
asynchronous, i.e., no clock is required.

RxDA, RxDB

37, 12

40, 14

Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
external receiver clock is specified for the channel, the input is sampled on the rising edge
of the clock.

TxDA, TxDB

36, 13

39, 15

Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted
first. This output is in the marking (high) condition when the transmitter is disabled or when
the channel is operating in local loopback mode. If external transmitter clock is specified
for the channel, the data is shifted on the falling edge of the clock.

RTxCA, RTxCB

39, 10

43, 11

I/O

Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply
the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock
(1X).

TRxCA, TRxCB

40, 9

44, 10

I/O

Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1

2).

CTSA/BN,
LCA/BN

32, 17

35, 19

I/O

Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal
can be programmed to act as an enable for the transmitter when not in loop mode. The
CDUSCC detects logic level transitions on this input and can be programmed to generate
an interrupt when a transition occurs. When operating in the BOP loop mode, this pin be-
comes a loop control output which is asserted and negated by CDUSCC commands. This
output provides the means of controlling external loop interface hardware to go on-line and
off-line without disturbing operation of the loop.

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

PIN DESCRIPTION (Continued)

MNEMONIC

PIN NO.

TYPE

NAME AND FUNCTION

MNEMONIC

DIP

PLCC

TYPE

NAME AND FUNCTION

DCDA/BN,
SYNIA/BN

38, 11

42, 12

Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-low input, it acts as an enable for the receiver or can be
used as a general purpose input. For the DCD function, the CDUSCC detects logic level
transitions on this pin and can be programmed to generate an interrupt when a transition
occurs. As an active-low external sync input, it is used in COP mode to obtain character
synchronization for the receiver without receipt of a SYN character. This mode can be
used in disc or tape controller applications or for the optional byte timing lead in X.21.

RTxDRQA/BN,
GPO1A/BN

34, 15

37, 17

Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the
receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).
For full-duplex DMA operation, this output indicates to the DMA controller that data is
available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that
can be asserted and negated under program control.

TxDRQA/BN,
GPO2A/BN,
RTSA/BN

33, 16

36, 18

Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the
DMA controller that the transmit FIFO is not full and can accept more data. When not in
full-duplex DMA mode, this pin can be programmed as a general purpose or a
Request-to-Send output, which can be asserted and negated under program control.

RTxDAKA/BN,
GPI1A/BN

44, 5

48, 5

Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-low. For half-duplex single address operation, this input indicates to the CDUSCC
that the DMA controller has acquired the bus and that the requested bus cycle (read
receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter
is enabled) is beginning. For full-duplex single address DMA operation, this input indicates
to the CDUSCC that the DMA controller has acquired the bus and that the requested read
receiver FIFO bus cycle is beginning. Because the state of this input can be read under
program control, it can be used as a general purpose input when not in single address
DMA mode.

TxDAKA/BN,
GPI2A/BN

35, 14

38, 16

Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low.
When the channel is programmed for full-duplex single address DMA operation, this input
is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and
that the requested load transmitter FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when
not in full-duplex single address DMA mode.

DONEN

I/O

Done: Active-low, open-drain. DONEN can be used and is active in both DMA and
non-DMA modes. As an input, DONEN indicates the last DMA transfer cycle to the
TxFIFO. As an output, DONEN indicates either the last DMA transfer from the RxFIFO or
that the transmitted character count has reached terminal count.

RTSA/BN,
SYNOUTA/BN

41, 8

45, 9

Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send
modem control signal, it functions as described previously for the TxDRQN/RTSN pin.

DTACKN

Data Transfer Acknowledge: Active-low, 3-state. DTACKN is asserted on a write cycle to
indicate that the data on the bus has been latched, and on a read cycle or interrupt
acknowledge cycle to indicate valid data is on the bus. In a write bus cycle, input data is
latched by the assertion (falling edge) of DTACKN or by the negation (rising edge) of CSN,
whichever occurs first. The signal is negated when completion of the cycle is indicated by
negation of CSN or IACKN input, and returns to the inactive state (3-state) a short period
after it is negated. In single address DMA mode, input data is latched by the assertion
(falling edge) of DTCN or by the negation (rising edge) of the DMA acknowledge input,
whichever occurs first. DTACK is negated when completion of the cycle is indicated by the
assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first), and
returns to the inactive state (3-state) a short period after it is negated. When inactive,
DTACKN requires an external pull-up resistor.

DTC

Device Transfer Complete: Active-low. DTCN is asserted by the DMA controller to
indicate that the requested data transfer is complete.

34, 52

+5V Power Input

GND

26, 13,

41, 7

Signal and Power Ground Input

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

DC ELECTRICAL CHARACTERISTICS

4, 5 T

= 0 to +70

C, 40 to +85

C, V

= 5.0V

10%

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

Min

Typ

Max

UNIT

Input low voltage:
All except X1/CLK

X1/CLK

Input high voltage:
All except X1/CLK

X1/CLK

0 to 70

40 to 85

2.0
2.3

0.8xV

0.8
0.8

V
V
V
V
V

Output low voltage:

All except IRQN

IRQN

Output high voltage:

(Except open drain outputs)

= 5.3mA (Comm), 4.8mA

(Indus)

= 8.8mA (Comm), 7.8mA

(Indus)

= -400

0.5

0.5
0.5

V
V

ILX1

IHX1

X1/CLK input low current

X1/CLK input high current

= 0, X2 = GND

= V

, X2 = GND

150

0.0

150

SCX2

X2 short circuit current (X2 mode)

X1 open V

= 0

= V

15
+15

mA
mA

Input low current
RESETN, DTCN, TxDAKA/BN,
RTxDAKA/BN

= 0

-15

0.5

Input leakage current

= 0 to V

CC,

0 to 70

40 to 85

-1

+10

OZH

Output off current high, 3-State data bus

= V

CC,

0 to 70

40 to 85

+10

OZL

Output off current low, 3-State data bus

= 0

0 to 70

40 to 85

-1

ODL

ODH

Open drain output low current in off
state:

DONEN

DTACKN (3-state)

IRQN

Open drain output high current in off

state:

DONEN, IRQN, DTACKN (3-state)

= 0

= V

-1

-0.5

Power supply current

(See Figure 17 for graphs)

0 to 70

40 to 85

80
95

OUT

I/O

Input capacitance

Output capacitance

Input/output capacitance

= GND = 0

10
15
20

pF
pF
pF

NOTES:
1. Stresses above those listed under Abs. Max Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied.

2. Clock may be stopped (DC) for testing purposes or when the CDUSCC is in non-operational modes. Operation down to 0 rate clocks is

implied by a full static CMOS design, but is not verified in testing or characterization.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over specified temperature and voltage range.
5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transi-

tion time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V. All time measurements are referenced at input voltages of
0.2V and 3.0V and output voltages of 0.8V and 2.0V, as appropriate.

6. See Figure 18 for test conditions for outputs.
7. Tests for open drain outputs are intended to guarantee switching of the output transistor. To include noise margin this response is measured

from the switching signal midpoint to 0.2 V above the required output level.

8. Execution of the valid command (after it is latched) requires a minimum of three rising edges of X1 (see Figure 19).
9. These values were no explicitly tested; they are guaranteed by design and characterization data.
10. X1/CLK and X2 are not tested with a crystal installed.
11. X1/CLK frequency must be at least as fast as the faster of the receiver or transmitter data rate.
12. The X1 clock drives DTACKN, Baud Rate Generator, command register and the update of the FIFO fill level encoders. The Command

13. The 68562 bus interface may be operated in two modes; a 68000 compatible mode with automatic DTACK generation and a short chip

select mode. DTACKN should not be used externally in the short chip select mode. The DTACKN signal is generated by the assertion of
the chip select, and data is latched by assertion of DTACKN or by de-assertion of the chip select, whichever comes first. In single address
DMA, the DTACK signal will be de-asserted by the assertion of the DTCN or from the de-assertion of the TxDAKN, whichever occurs first.

14. Also includes X2/IDCN pin in IDC mode.
15. In case of 3-state output, output levels V

+ 0.2 are considered float or high impedance.

16. V

= 0 to V

, Rx/Tx at 10MHz and X1 at 10MHz

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

tRELREH

RESETN

SD00205

Figure 1. Reset Timing

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

RELREH

RESETN low to RESETN high

200

A1A6

R/WN

CSN

D0D7

DTACKN12

tADVCSL

tRWHCSL

tCSLADI

tCSLCSH

tCSHRWL

tCSHCSL

tCSHDDF

tCSLDDV

tCSLDDA

tDDVDAL

tCSHDDI

tCSHDAH
tCSHDAZ

tCSLDAL

INVALID

DATA VALID

INVALID

tDALCSH

SD00254

Figure 2. Read Cycle Bus Timing

Times represent an X1 clock frequency of 14.745MHz

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

ADVCSL

A0-A6 valid to CSN low

RWHCSL

RWN high to CSN low

CSHRWL

CSN high to RWN low

CSHCSL

CSN high to CSN low

CSLDDV

CSN low to read data valid

150

130

CSHDDF

CSN high to data bus float

DDVDAL

Read data valid to DTACKN low

DALCSH

DTACKN low to CSN high

CSLDAL

CSN low to DTACKN low

)

140

)

1.5

)

130

)

1.5

CSHDAH

CSN high to DTACKN high

CSHDAZ

CSN high to DTACKN high impedance

CSLADI

CSN low to address invalid

CSLCSH

CSN low to CSN high

150

130

CSLDDA

CSN low to data bus driver active

CSHDDI

CSN high to data invalid

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

A1A6

R/WN

CSN

D0D7

DTACKN12

tADVCSL

tCSLADI

tCSLWDV

tCSLDAL

tCSHRWH

tDALCSH

tCSLCSH

tCSHCSL

tCSHWDI

tDALWDI

tCSHDAH

tCSHDAZ

tRWLCSL

SD00255

Figure 3. Write Cycle Bus Timing

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

ADVCSL

A0-A6 valid to CSN low

CSLADI

CSN low to A0-A6 invalid

RWLCSL

RWN low to CSN low

CSHRWH

CSN high to RWN high

CSHCSL

CSN high to CSN low

DALCSH

DTACKN low to CSN high

DALWDI

DTACKN low to write data invalid

CSLDAL

CSN low to DTACKN low

)

140

)

1.5

)

130

)

1.5

CSHDAH

CSN high to DTACKN high

CSHDAZ

CSN high to DTACKN high impedance

CSLCSH

CSN low to CSN high

150

130

CSLWDV

CSN low to write data valid

CSHWDI

CSN high to write data invalid

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

INVALID

DATA VALID

INVALID

tIALIAH

tIALDDV

tDDVDAL

tIAHDDF

tIAHDAH

tIAHDDI

tIAHDAZ

tIALDAL

tDALIAH

IRQN

IACKN

D0-D7

DTACHN12

tIALDDA

SD00256

Figure 4. Interrupt Cycle Timing

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

IALIAH

IACKN low to IACKN high

140

130

IALDDA

IACKN low to data bus drivers active

IALDDV

IACKN low to read data valid

140

130

IAHDDF

IACKN high to data bus floating

DDVDAL

Read data valid to DTACKN low

IAHDAH

IACKN high to DTACKN high

IAHDAZ

IACKN high to DTACKN high impedance

110

100

IALDAL

IACKN low to DTACKN low

)

140

)

1.5

)

130

)

1.5

IAHDDI

IACKN high to data bus invalid

DALIAH

DTACKN low to IACKN high

IACKN

IDCN

tIALDCL

SD00257

Figure 5. Interrupt Daisy Chain Timing

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

IALDCL

IACKN low to IDCN (daisy chain) low

tCSLGII

tGIVCSL

RWN

CSN

GPI1_N

AND/OR

GPI2_N

SD00258

Figure 6. Input Port Timing

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

tDALIRH

tCSHIRH

CSN

DTACKN

IRQN

SD00260

Figure 8. Interrupt Timing, Write Cycle

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

DALIRH

DTACKN low to IRQN high, write cycle

Write TxFIFO (TxRDY interrupt)

Write RSR (Rx condition interrupt)

Write TRSR (Rx/Tx interrupt)

Write ICTSR (port change and CT interrupt)

Write TRMSR (Tx Path, Patt recognition)

CSHIRH

CSN high to IRQN high, write cycle

Write TxFIFO (TxRDY interrupt)

100

Write RSR (Rx condition interrupt)

100

Write TRSR (Rx/Tx interrupt)

100

Write ICTSR (port change and CT interrupt)

100

Write TRMSR (Tx Path, Patt recognition)

100

tCSHIRH

IRQN

CSN

VOL +.5V

SD00261

Figure 9. Interrupt Timing, Read Cycle

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

CSHIRH

CSN high to IRQN high, read cycle

Read RxFIFO (RxRDY interrupt)

100

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

X1/CLK

CTCLK

RxC

TxC

tCLHCLL
tCCHCCL
tRCHRCL
tTCHTCL

tCLLCLH
tCCLCCH
tRCLRCH
tTCLTCH

+5V

OPEN X2

CLK

470

a. Driving X1 from an External Source

TO DTACKN

ALL OTHER BLOCKS

360k

1.5M

CDUSCC

BLOCK

CRYSTAL SERIES RESISTANCE SHOULD

BE LESS THAN 180

TTL

*PULL-UP RESISTOR IS NOT REQUIRED
WHEN USING CMOS LEVELS

CP1

CP2

SD00262

Figure 10. Receive, Dual Address DMA

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Typ

Max

Min

Typ

Max

CLHCLL

X1/CLK high to low time

CLLCLH

X1/CLK low to high time

CCHCCL

CT and DPLL CLK high to low time

CCLCCH

CT and DPLL CLK low to high time

RCHRCL

RxC high to low time

RCLRCH

RxC low to high time

TCHTCL

TxC high to low time

TCLTCH

TxC low to high time

X1/CLK frequency

11, 2

14.7456

16.0

14.7456

16.0

MHz

CT CLK frequency

MHz

RxC frequency (16X or 1X)

MHz

TxC frequency (16X or 1X)

MHz

RTC

Tx/Rx frequency for FM/Manchester encoding

MHz

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

1 BIT TIME

(1 OR 16 CLOCKS)

tCILTXV

tCOLTXV

TxC

(INPUT)

TxD

TxC

(1X OUTPUT)

tCILTXV

tCOLTXV

TxC

(INPUT)

TxD

TxC

(1X OUTPUT)

tCILTXV

tCOLTXV

a. Transmit Timing NRZ

b. Transmit Timing FM0/1, Manchester Encoding

SD00263

Figure 11.

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

CILTXV

TxC input low (1X) to TxD output

120

TxC input low (16X) to TxD output

125

120

COLTXV

TxC output low to TxD output (NRZ, NRZI)

(FM, Manchester)

NOTE: Characterized with no loads on TxD and TxC outputs.* Tester load approximately 50pF.

tRCHSOL

tSILRCH

tRCHSIH

tRXVRCH

tRCHRXI

SYNOUTN

SYNIN

RXC (1X)

INPUT

RxD

tRXVRCH

RXC

(INPUT)

RxD

tRCHRXI

tRXVRCH

a. Receive Timing NRZ

b. Receive Timing FM0/1, Manchester Encoding

SD00264

Figure 12.

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

RXVRCH

RxD data valid to RxC high:

For NRZ data

For NRZI, Manchester, FM0, FM1 data

RCHRXI

RxC high to RxD data invalid:

For NRZ data

For NRZI, Manchester, FM0, FM1 data

SILRCH

SYNIN low to RxC high

RCHSIH

RxC high to SYNIN high

RCHSOL

RxC high to SYNOUT low

110

100

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

tCSLTOL

DONEN

(OUTPUT)

CSN

DONEN

(INPUT)

TxDRQ_N OR

RTxDRQ_N

tCSLDAL

tCSLDIL

tCSLTRH

tTRHDAL

tDALDIH

tCSHDIH

tCSHTOH

tDALTOH

tTOLDAL

DTACKN12

SD00266

Figure 14. Transmit, Dual Address DMA

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

CSLTOL

CSN low to Tx DONEN output low

110

100

CSLTRH

CSN low to Tx DMA REQN high

110

100

DALDIH

DTACKN low to Tx DONEN input high

DALTOH

DTACKN low to Tx DONEN output high

TOLDAL

Tx DONEN output low to DTACKN low

TRHDAL

Tx DMA REQN high to DTACKN low

CSLDAL

CSN low to DTACKN low

)

140

)

1.5

)

130

)

1.5

CSLDIL

CSN low to Tx DONEN input low

CSHTOH

CSN high to Tx DONEN output high

CSHDIH

CSN high to Tx DONEN input high

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

DMA Rx Read Timing -- Single Address DMA

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

RALDDV

Receive DMA ACKN low to read data valid

140

130

DTLDTH

DTCN low to DTCN high

DALDTL

DTACKN low to DTCN low

DTLDDF

DTCN low to data bus float

RALDAL

Rx DMA ACK low to DTACKN low

)

140

)

1.5

)

130

)

1.5

DDVDAL

Read data valid to DTACKN low

DTLDAH

DTCN low to DTACKN high

DTLDAZ

DTCN low to DTACKN high impedance

110

RRHDAL

Rx DMA REQN high to DTACKN low

ROLDAL

Rx DONEN output low to DTACKN low

RALRRH

Rx DMA ACKN low to receive DMA REQN high

100

RAHRAL

Receive DMA ACKN high to low time

RALROL

Rx DMA ACK low to Rx DONEN output low

100

DTLROH

DTCN low to Rx DONEN output high

RALRAH

Rx DMA ACKN low to Rx DMA ACKN high

140

130

RAHDDF

Rx DMA ACKN high to data bus float

RALDDA

Rx DMA ACKN low to data bus drivers active

RAHDDI

Rx DMA ACKN high to data bus invalid

DTLDDI

DTCN low to data bus invalid

RALDTL

Rx DMA ACKN low to DTCN low

140

130

RAHDAH

Rx DMA ACKN high to DTACKN high

RAHDAZ

Rx DMA ACKN high to DTACKN high impedance

110

100

RAHROH

Rx DMA ACKN high to DONEN output high

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

DMA Tx Write Timing -- Single Address DMA

LIMITS

SYMBOL

PARAMETER

INDUSTRIAL SC68C562

COMMERCIAL SC68C562

UNIT

Min

Max

Min

Max

DTLDTH

DTCN low to DTCN high

DALDTL

DTACKN low to DTCN low

TALDAL

Tx DMA ACK low to DTACKN low

)

140

)

1.5

)

130

)

1.5

DTLDAH

DTCN low to DTACKN high

DTLDAZ

DTCN low to DTACKN high impedance

110

TRHDAL

Tx DMA REQN high to DTACKN low

TOLDAL

Tx DONEN output low to DTACKN low

DTLTOH

DTCN low to Tx DONEN output high

WDVDTL

Write data valid to DTCN low

DTLWDI

DTCN low to write data invalid

TALTRH

Tx DMA ACKN low to transmit DMA REQN high

110

100

TAHTAL

Transmit DMA ACKN high to low time

TALTOL

Tx DMA ACKN low to Tx DONEN output low

100

DILDTL

Transmit DONEN input low to DTCN low

DTLDIH

DTCN low to transmit DONEN input high

TALTAH

Tx ACKN low to Tx ACKN high

110

100

TAHWDI

Tx ACKN high to write data invalid

WDVTAH

Write data valid to Tx DAKN high

TAHDAH

Tx DAKN high to DTACKN high

TAHDAZ

Tx DAKN high to DTACKN high impedance

110

100

TAHTOH

Tx DAKN high to DONEN output high

DILTAH

DONEN input low to Tx DAKN high

TAHDIH

Tx DAKN high to DONEN input high

TALDTL

Tx DAKN low to DTCN low

110

100

Philips Semiconductors

Product specification

SC68C562

CMOS Dual universal serial communications controller
(CDUSCC)

1998 Sep 04

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 940883409
Telephone 800-234-7381

Date of release: 08-98

Document order number:

9397 750 04356

Philips

Semiconductors

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

[1]

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SC68C562

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