Data Sheet
Final Version 1.5
October 27, 2003
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RDC Semiconductor Co., Ltd
http://www.rdc.com.tw
TEL: 886-3-666-2866
FAX: 886-3-563-1498
R1610C
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Fast Ethernet RISC Processor
Data Sheet
Final Version 1.5
October 27, 2003
2
CONTENTS
1.
Features ............................................................................................. 7
2.
Block Diagram ................................................................................... 8
3.
Pin Description .................................................................................. 9
3.1
PIN Placement ...............................................................................................................................9
3.2
Functional Description ................................................................................................................10
3.3
PIN Capacitance Description.......................................................................................................17
3.4
PIN Pull-up/Pull-down Description.............................................................................................17
4.
Oscillator Characteristics............................................................... 19
4.1
Fundamental Mode......................................................................................................................19
4.2
Third-Overtone Mode..................................................................................................................19
5.
Clock Unit......................................................................................... 20
6.
Execution UNIT................................................................................ 21
6.1
General Registers.........................................................................................................................21
6.2
Segment Registers .......................................................................................................................21
6.3
Instruction Pointer and Status Flags Registers ............................................................................22
6.4
Address Generation .....................................................................................................................23
7.
Peripheral Register List .................................................................. 24
7.1
Legacy Peripheral Registers (Base Address FF00h) ...................................................................24
7.2
16550 UART Register Definitions (Base Address FF00h) .........................................................25
7.3
SDRAM Control Registers (Base Address FE00h).....................................................................25
7.4
Cache control register (Base Address FEC0h) ............................................................................25
7.5
Fast Ethernet MAC Control Registers (Base Address: MAC / FE00h) ......................................26
8.
Peripheral Control Block Registers............................................... 28
9.
Reset................................................................................................. 30
9.1
Power-up Reset............................................................................................................................31
R1610C
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Fast Ethernet RISC Processor
Data Sheet
Final Version 1.5
October 27, 2003
3
10.
Bus Interface UNIT........................................................................32
10.1
Slow Bus and Memory Shadow............................................................................................... 32
10.2
Memory and I/O Interface ....................................................................................................... 34
10.3
Data Bus................................................................................................................................... 35
10.4
Wait States................................................................................................................................ 36
10.5
Bus Width ................................................................................................................................ 37
11.
Chip Select UNIT...........................................................................38
11.1 UCS_n......................................................................................................................................... 38
11.2 PCSx_n ....................................................................................................................................... 39
12.
Refresh Control UNIT ...................................................................42
13.
Interrupt Controller UNIT .............................................................43
13.1
Interrupt Vector, Type and Priority .......................................................................................... 44
13.2
Interrupt Requests .................................................................................................................... 44
13.3
Programming the Registers...................................................................................................... 45
14.
DMA UNIT ......................................................................................55
14.1
DMA Operation ....................................................................................................................... 55
14.2
External Requests .................................................................................................................... 61
14.3
Serial Port/DMA Transfer........................................................................................................ 63
15.
Timer Control UNIT .......................................................................64
15.1
Timer/Counter Unit Output Mode ........................................................................................... 69
15.2
Watchdog Timer....................................................................................................................... 70
16.
16550 UART Serial Port................................................................72
16.1
Receiver Buffer Register and Transmitter Holding Register................................................... 73
16.2
Divisor Latch LS and MS Register.......................................................................................... 74
16.3
Interrupt Enable Register ......................................................................................................... 75
16.4
Interrupt Identification Register............................................................................................... 75
16.5
FIFO Control Register ............................................................................................................. 77
16.6
Line Control Register............................................................................................................... 78
16.7
Modem Control Register ......................................................................................................... 79
R1610C
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Fast Ethernet RISC Processor
Data Sheet
Final Version 1.5
October 27, 2003
4
16.8
Line Status Register..................................................................................................................80
16.9
Modem Status Register.............................................................................................................82
16.10 Scratchpad Register ..................................................................................................................83
16.11 Programmable Baud Generator ................................................................................................83
16.12 FIFO Interrupt Mode Operation ...............................................................................................84
16.13 FIFO Polled Mode Operation...................................................................................................85
17.
PIO UNIT ........................................................................................ 86
17.1
PIO multi-function Pin list table...............................................................................................86
18.
SDRAM Controller ........................................................................ 90
18.1
SDRAM Mode Set Register .....................................................................................................90
18.2
SDRAM Control Register ........................................................................................................90
18.3
SDRAM Timing Parameter Register........................................................................................91
19.
CACHE Controller......................................................................... 92
19.1
Cache Control Register.............................................................................................................92
19.2
Non-Cache Region Register .....................................................................................................92
19.3
Write Invalid Region Register ..................................................................................................98
20.
Fast Ethernet Controller............................................................. 100
20.1
RX Descriptor Format ............................................................................................................100
20.2
TX Descriptor Format ............................................................................................................104
20.3
MCR0: MAC Control Register 0 (00h)..................................................................................106
20.4
MCR1: MAC Control Register 1 (04h)..................................................................................107
20.5
MBCR: MAC Bus Control Register (08h).............................................................................109
20.6
MTICR: TX Interrupt Control Register (0Ch) .......................................................................110
20.7
MRICR: RX Interrupt Control Register (10h) .......................................................................110
20.8
MTPR: TX Poll Command Register (14h)............................................................................. 111
20.9
MRBSR: RX Buffer Size Register (18h) ............................................................................... 111
20.10 MRDCR: RX Descriptor Control Register (1Ah) ..................................................................112
20.11 MLSR: MAC Last Status Register(1Ch)................................................................................112
20.12 MMDIO: MDIO Control Register (20h) ................................................................................113
20.13 MMRD: MDIO Read Data Register (24h).............................................................................114
20.14 MMWD: MDIO Write Data Register (28h) ...........................................................................114
20.15 MTDSA0: TX Descriptor Start Address 0 (2Ch) ...................................................................114
R1610C
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Fast Ethernet RISC Processor
Data Sheet
Final Version 1.5
October 27, 2003
5
20.16 MTDSA1: TX Descriptor Start Address 1 (30h) ....................................................................115
20.17 MRDSA0: RX Descriptor Start Address 0 (34h)....................................................................115
20.18 MRDSA1: RX Descriptor Start Address 1 (38h)....................................................................116
20.19 MISR: INT Status Register (3Ch)...........................................................................................116
20.20 MIER: INT Enable Register (40h)..........................................................................................117
20.21 MECISR: Event Counter INT Status Register(44h) ...............................................................117
20.22 MECIER: Event Counter INT Enable Register (48h) ............................................................118
20.23 MRCNT: Successfully Received Packet Counter (50h) .........................................................119
20.24 MECNT0: Event Counter 0 (52H)..........................................................................................119
20.25 MECNT1: Event Counter 1 (54h) ......................................................................................... 120
20.26 MECNT2: Event Counter 2 (56h) ......................................................................................... 120
20.27 MCENT3: Event Counter 3 (58h) ......................................................................................... 120
20.28 MTCNT: Successfully Transmit Packet Counter (5Ah) ........................................................ 121
20.29 MCENT4: Event Counter 4 (5Ch)......................................................................................... 121
20.30 MPCNT: Pause Frame Counter (5Eh) ................................................................................... 122
20.31 MAR0 ~3: Hash Table Word 0 ~3 (60h, 62h, 64h, 66h)........................................................ 122
20.32 MID0 (68h, 6Ah, 6Ch)........................................................................................................... 124
20.33 MID1 (70h, 72h, 74h) ............................................................................................................ 125
20.34 MID2 (78h, 7Ah, 7Ch)........................................................................................................... 126
20.35 MID3 (80h, 82h, 84h) ............................................................................................................ 127
21.
DC Electrical Characteristics.....................................................128
21.1
Absolute Maximum Ratings (25) ...................................................................................... 128
21.2
Operating Temperature .......................................................................................................... 128
22.
AC Electrical Characteristics.....................................................129
22.1
Alphabetical Key to Switching Parameter Symbols.............................................................. 129
22.2
Numerical Key to Switching Parameter Symbols ................................................................. 129
22.3
CPU Bus ................................................................................................................................ 130
22.4
SDRAM Bus .......................................................................................................................... 134
22.5
CPU Reset.............................................................................................................................. 136
22.6
MDC/MDIO Timing .............................................................................................................. 137
22.7
TX Transmit Timing Parameters............................................................................................ 138
22.8
TX Transmit Timing Diagram ............................................................................................... 138
22.9
RX Receive Timing Parameters............................................................................................. 138
22.10 RX Receive Timing Diagram ................................................................................................ 138
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