Multimedia ICs

NTSC / PAL digital RGB encoder

BU1425AK / BU1425AKV

The BU1425AK / BU1425AKV are ICs which convert digital RGB / YUV input to composite (NTSC / PAL / PAL60),

luminance (Y), and chrominance (C) signals, and outputs the results.

Applications

Video interfaces for VIDEO-CDs and CD-G decoders

Features

1) Input clocks supported

27.0 / 13.5MHz

28.636 / 14.318MHz

28.375 / 14.1875MHz

35.4695 / 17.73475MHz

2) 24-bit RGB and 16-bit YUV input signals are sup-

ported.

3) Both master and slave systems are supported.

4) 9-bit high-speed DAC is used for DAC output of

composite VIDEO, Y, and C signals.

5) Internal 8-color OSD output function is provided.

6) FSC-TRAP on the Y channel can be turned on and

off.

7) C channel is equipped with an internal chromi-

nance band-pass filter in addition to the U.V. low-

pass filter.

8) 5V single power supply, low power consumption

(0.4W typ.)

9) Y and C output can be turned off (the power con-

sumption with Y and C off is 0.25W typ.).

10) In the Master mode, applying 3.3V to the I / O V

and 5.0V to other V

s produces HSY and VSY

output with an amplitude of 3.3V. This enables

direct connection to LSIs that use a power supply

voltage of 3.3V. (The clock output for the OSD has

a fixed amplitude of 5.0V.)

11) In the Slave mode, applying voltage to the I / O V

only, and applying 0V to other V

s, enables a cur-

rent consumption of 0 even when RGB DATA,

HSY, VSY, and OSD DATA are in the active state.

Multimedia ICs

BU1425AK / BU1425AKV

Pin descriptions

Pin No. Pin name

Function

With pull-down resistor (approx. 30k

)

BOSD

GD0 / Y0

GD1 / Y1

GD2 / Y2

GD3 / Y3

GD4 / Y4

GD5 / Y5

GD6 / Y6

GND

GD7 / Y7

BD0 / UV0

BD1 / UV1

BD2 / UV2

BD3 / UV3

OSDSW

CDGSWB

BD4 / UV4

BD5 / UV5

BD6 / UV6

BD7 / UV7

GND

NTB

IM0

IM1

TEST1

TEST2

VSY

HSY

PIXCLK

IOV

INT

SLABEB

ADDH

VREF-C

CGND

COUT

VGND

VOUT

P-V

YGND

YOUT

YFILON2B

YCOFF

YFILON1B

PAL60B

VCLK

RSTB

CLKSW

RD0

RD1

RD2

ROSD

RD3

RD4

RD5

IOV

RD6

RD7

GOSD

OSD BLUE DATA INPUT

GREEN DATA Bit0 (LSB)

GREEN DATA Bit1

GREEN DATA Bit2

GREEN DATA Bit3

GREEN DATA Bit4

GREEN DATA Bit5

GREEN DATA Bit6

DIGITAL GROUND

GREEN DATA Bit7 (MSB)

BLUE DATA Bit0 (LSB)

BLUE DATA Bit1

BLUE DATA Bit2

BLUE DATA Bit3

OSD ENABLE / DISABLE

SELECT Video-CD / CD-G

BLUE DATA Bit4

BLUE DATA Bit5

BLUE DATA Bit6

BLUE DATA Bit7 (MSB)

DIGITAL GROUND

SELECT NTSC / PAL MODE

SELECT YUV / RGB

SELECT DAC / NORMAL

Normally pull down to GND

SELECT U / V TIMING

V-SYNC INPUT or OUTPUT

H-SYNC INPUT or OUTPUT

1 / 2freq. of BCLK

DIGITAL V

for I / O

Interlace / Non-Interlace

Pin No. Pin name

SELECT MASTER / SLAVE

+ 0.5 /

0.5LINE at NON-INTER

DAC BIAS

CHROMA OUTPUT GROUND

CHROMA OUTPUT

Composite Output Ground

COMPOSITE OUTPUT

Analog Ground (DAC VREF)

POWER (DAC) V

REFERENCE RESISTOR

ANALOG (VREF) V

Luminance Output Ground

Luminance Output

DIGITAL V

Y-FILSEL THROU / FILON2

DAC (YOUTCOUT) OFF

Y-FILSEL THROU / FILON1

NORMAL / PAL60 at PALMODE

Video Clock Input

NORMAL / RESET

SEL

1CLK /

2CLK

RED DATA Bit0 (LSB)

RED DATA Bit1

RED DATA Bit2

OSD RED DATA INPUT

RED DATA Bit3

RED DATA Bit4

RED DATA Bit5

for I / O

RED DATA Bit6

RED DATA Bit7

OSDGREEN DATA INPUT

Function

Multimedia ICs

BU1425AK / BU1425AKV

Absolute maximum ratings (Ta = 25°C)

Parameter

Symbol

Limits

Unit

Applied voltage

Input voltage

Storage temperature

Power dissipation

, AV

Tstg

0.5 ~ + 7.0

0.3 ~ IOV

+ 0.3

55 ~ + 150

1350

Reduced by 11mW for each increase in Ta of 1

C over 25

When mounted on 120mm

140mm

1.0mm glass epoxy board.

Operation is not guaranteed at this value.

Not designed for radiation resistance.

Recommended operating conditions

Parameter

Symbol

Limits

Unit

Power supply voltage

Input high level voltage

Input low level voltage

Analog input voltage

Operating temperature

= AV

IOV

AIN

Topr

0 ~ + 0.8

0 ~ AV

25 ~ + 60

4.50 ~

3.30 ~

2.1 ~

5.50

Should be used at V

= AV

Electrical characteristics (unless otherwise noted, Ta = 25°C, V

= AV

= 5.0V, GND = AV

= VGND = CGND = YGND)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Conditions

Digital block

Burst frequency 1

Burst frequency 2

Burst cycle

Operating circuit current 1

Operating circuit current 2

Output high level voltage

Output low level voltage

Input high level voltage

Input low level voltage

Input high level current

Input low level current

fBST1

fBST2

CBST

Idd1

Idd2

4.0

2.1

3.57954

4.43361

4.5

0.5

0.0

1.0

0.8

10.0

MHz

CYC

27MHz color bar

27MHz color bar PD mode

= 2.0mA

DAC block

DAC resolution

Linearity error

Y white level current

Y black level current

Y zero level current

V white level current

V black level current

V zero level current

RES

IYW

IYB

IYZ

IYW

IYB

IYZ

25.14

7.24

0.0

25.14

7.24

0.0

10.0

BITS

LSB

IR = 1.2k

Sleep mode current

Iddpd

1.0

Max. = IOV

+ 0.3V

Min. = 0.3V

0.5

3.0

Multimedia ICs

BU1425AK / BU1425AKV

Application example

(1) Example in Master mode: Doubled clock is input and 24-bit RGB input is used

6 5

B Data 0...7

G Data 0...7

R Data 0...7

[Blue]

[Green]

[Red]

OSD in

Vsync out

Hsync out

OSD CLOCK

OSD in

Video-CD / CD-G

Reset [Low active] in

Pixel Clock in

Y-filter select

INTERLACE / NON-INTER

PAL / NTSC

DIGITAL GND

Chrominance

Composite

Luminance

MAIN V

5.0 V

SLEEP MODE CTL

L: SLEEP

H: NORMAL

I / O V

5.0V or 3.3V

BU1425AK / AKV

ANALOG V

1.2k

0.01

ANALOG GND

POWER GND

POWER V

DIGITAL V

CDGSWB

OSDSW

BD3

BD2

BD1

BD0

GD7

GND

GD6

GD5

GD4

GD3

GD2

GD1

GD0

BOSD

SLABEB

ADDH

VREF

CGND

COUT

VGND

OUT

YGND

YOUT

YFILON2B

YCOFF

BD4

BD5

BD6

BD7

GND

NTB

IM0

IM1

TEST1

TEST2

VSY

HSY

PIXCLK

I / O V

INT

GOSD

RD7

RD6

I / O V

RD5

RD4

RD3

ROSD

RD2

RD1

RD0

CLKSW

RSTB

VCLK

PAL GOB

YFILON1B

OSD enable

Fig.1

Multimedia ICs

BU1425AK / BU1425AKV

(2) Example in Slave mode: Doubled clock is input and 16-bit YUV input is used

6 5

U.V Data 0...7

Y Data 0...7

[Blue]

[Green]

[Red]

OSD in

OSD CLOCK

OSD in

Video-CD / CD-G

Reset [Low active] in

Pixel Clock in

Y-filter select

INTERLACE / NON-INTER

PAL / NTSC

DIGITAL GND

Hsync in

Vsync in

Chrominance

Composite

Luminance

MAIN V

5.0V

SLEEP MODE CTL

L: SLEEP

H: NORMAL

I / 0 V

5.0V or 3.3V

BU1425AK / AKV

ANALOG VDD

0.01

ANALOG GND

POWER GND

POWER VDD

DIGITAL VDD

CDGSWB

OSDSW

BD3

BD2

BD1

BD0

GD7

GND

GD6

GD5

GD4

GD3

GD2

GD1

GD0

BOSD

SLABEB

ADDH

VREF

CGND

COUT

VGND

OUT

YGND

YOUT

YFILON2B

YCOFF

BD4

BD5

BD6

BD7

GND

NTB

IM0

IM1

TEST1

TEST2

VSY

HSY

PIXCLK

I / O V

INT

GOSD

RD7

RD6

I / O V

RD5

RD4

RD3

ROSD

RD2

RD1

RD0

CLKSW

RSTB

YCLK

PAL GOB

YFILON1B

1.2k

Fig.2

OSD enable

Multimedia ICs

BU1425AK / BU1425AKV

Equivalent circuits

Pin No.

Pin name

Equivalent circuit

I / O

Function

2 ~ 8

GD (7: 0)

G data input pin for 24-bit RGB input
Y data input pin for 16-bit YUV input

11 ~ 14
17 ~ 20

BD (0: 7)

B data input pin for 24-bit RGB input
U, V data input pins for 16-bit YUV
input

Control pins used to select RGB (24-
bit), YUV (16-bit) or DAC Through as
the input mode.

CDGSWB

Switches the mode between Video-
CD (HIGH) and CD-G (LOW).

54 ~ 56
58 ~ 60

62.63

RD (0: 7)

R data input pin for 24-bit RGB input

57
64
15

ROSD
GOSD
BOSD

OSDSW

OSD data input pin when using the
OSD function.
When the OSDSW pin is HIGH, input
to the ROSD, GOSD, and BOSD pins
takes precedence over RGB, and the
data is converted.

23
24

IM0
IM1

NTB

Switches the mode between NTSC
(LOW) and PAL (HIGH).

Multimedia ICs

BU1425AK / BU1425AKV

Pin No.

Pin name

Equivalent circuit

I / O

Function

VSY

I / O

Vertical synchronization signals (Vsync)
are input (when SLABEB = LOW) or
output (when SLABEB = HIGH) here.

VREF-C

This is the reference voltage generator
circuit monitoring pin which deter-
mines the output amplitude (output cur-
rent for 1 LSB) of the DAC. A 0.01

capacitor should be attached between
this and pin 43 (AV

PIXCLK

The internal processing clock is divid-
ed in half and output. Data is read at
the point at which the edge of this
clock changes. This can also be used
as the clock for the OSD IC.

INT

This pin switches between interlace
(when HIGH) and non-interlace (when
LOW) modes. This pin is effective in
both the VIDEO-CD and CD-G
modes.

33
34

SLABEB

ADDH

I
I

This pin switches between the Master
(when HIGH) and Slave (when LOW)
modes. It is effective in the non-
interlace mode, and it switches bet-
ween 0.5 lines (when LOW) and + 0.5
lines (when HIGH) for the number of
lines in an interlace field.

HSY

I / O

This is the horizontal synchronization
signal pin. Negative polarity Hsync
signals are input (when SLABEB =
LOW) or output (when SLABEB =
HIGH) here. This is also used as the
synchronization signal for fixing the
PIXCLK output phase.

COUT

This is the chrominance output pin for
the S pin.

Multimedia ICs

BU1425AK / BU1425AKV

Circuit operation

Table 1: Low power consumption mode with the YCOFF pin

Pin No.

Pin Name

YCOFF

LOW

HIGH

VOUT pin

Composite signal

Output Mode and Power Consumption

YOUT pin

Luminance signal

No output (0V)

COUT pin

Chrominance signal

No output (0V)

Power consumption (typ.)

0.45W

0.25W

(1) Overview

The BU1425AK / AKV converts digital images and video

data with an 8-bit configuration to 9-bit composite signals

OUT

), luminance signals (YOUT), and chrominance sig-

nals (COUT) for the NTSC, PAL, and PAL60 formats,

and outputs the converted data as analog TV signals.

The user may select whether V

OUT

consists of chromi-

nance signals that have passed through a chrominance

band pass and luminance signals that have been mixed,

or luminance signals that have passed through a chromi-

nance trap and luminance signals that have not passed

through a chrominance trap. The F characteristic of this

chrominance trap may be selected from among three

available types. Since YOUT normally does not pass

through the trap, it is optimum for the S pin. COUT nor-

mally passes through the chrominance band pass, and is

thus highly resistance to dot interference. In addition,

when used in the doubled clock mode, it passes through

an interpolator filter, and for that reason is able to repro-

duce even cleaner image quality.

A correspondence can be set up between input digital

image data and Video-CD and CD-G decoder output.

Output TV signals, in addition to switching among the

NTSC, PAL, and PAL60 modes, can be switched

between the interlace and non-interlace modes.

The data clock input to the VCLK pin can also be input as

a doubled clock for the data rate (in doubled clock

modes). In doubled clock modes, data is read and

processed at the rising edge of an internal clock that has

been divided in half. In ordinary clock modes, data is

read and processed at the rising edge of the clock that

has the same phase as the input clock. Two input data

formats are supported: 24-bit RGB (4: 4: 4) and 16-bit

YUV (4: 2: 2). These are input to RD0 to 7, GD0 to 7, and

BD0 to 7, respectively. The selected input format can be

switched using the IM0 and IM1 pin input. When the

OSDSW pin is set to the "Enabled" (H) state, data input

to the ROSD, GOSD, and BOSD pins becomes effective,

making it possible to input 7-color (8 including black)

chrominance data. At the same time, a clock with a fre-

quency half that of the internal clock is output from the

PIXCLK pin. As a result, the PIXCLK pin can easily be

directly connected to the OSD IC clock input pin, and the

OSDSW pin can be directly connected to the BLK output

pin. Thus, the BU1425AK and the OSD IC can be syn-

chronized, and OSD text with a burster trimmer stacker

feature can be used.

If the input data is in the RGB format, it is converted to

YUV. If it is in the YUV format, it is converted from the

CCIR-601 format to level-shifted YUV data. The YUV

data is then adjusted to the 100IRE level in the NTSC,

PAL, and PAL60 modes, and U and V data is phase-

adjusted by a sub-carrier generated internally, and is

modulated to chrominance signals.

Ultimately, elements such as the necessary synchroniza-

tion level, the color blanking level, and burst signals are

mixed, and pass through the 9-bit DAC to be output as

NTSC or PAL composite signals, luminance signals, and

chrominance signals (conforming to RS-170A). At this

point, the DAC is operating at twice the internal clock,

making it possible to reduce the number of attachments.

Furthermore, luminance signal output and chrominance

signal output can be turned off. At this point, it is possible

to reduce the level of power consumption.

The DAC output is current output. If a resistor of a speci-

fied value is connected to the IR pin, 2.0V

P-P

output can

be obtained by connecting 75

to the VOUT pin as an

external resistor. As a result, normally, when a video

input pin (75

terminus) is connected, the output is

approximately 1.0V

P-P

voltage output at a white 100%

level.

(2) Specifying the mode

1) Power saving mode

With the BU1425AK / AKV, setting the YCOFF pin to

HIGH turns off the output from the YOUT and COUT pins

of the DAC output, enabling use in the low power con-

sumption mode.

Multimedia ICs

BU1425AK / BU1425AKV

2) Output modes

The "Video-CD" and "CD-G" modes can be supported

by both digital image and video data, with the mode

being switched by the CDGSWB pin input. When the

CDGSWB pin input is LOW, the CD-G mode is set, and

when HIGH, the Video-CD mode is set. Also, the

"NTSC", "PAL", and "PAL60" modes may be selected

as the output TV modes. The output TV mode is

switched using the NTB and PAL60 pin input. Setting

the NTB pin input to LOW sets the NTSC mode, and

setting it HIGH with the PAL60 pin also HIGH sets the

PAL mode. Setting the NTB pin HIGH and the PAL60

pin LOW, sets the PAL60 mode.

Table 2: Specifying modes

NTB

PAL60

CDGSWB

Decoder mode

CD-G

Video-CD

CD-G

Video-CD

CD-G

Video-CD

TV mode

NTSC

PAL60

PAL

Also, INT pin input can be used to switch between

"interlace output" and "non-interlace output."

Setting the input to LOW enables non-interlace output,

and setting it to HIGH enables interlace output. When

non-interlace output is used, the number of lines in one

field can be controlled using the ADDH pin. If the ADDH

pin is LOW, the number of lines in one field is set to the

number of interlace output lines minus 0.5 lines, and

when HIGH, the number of lines in one field is set to the

number of interlace output lines plus 0.5 lines.

Table 3: Pin settings for interlace / non-interlace modes

INT

Scan Mode

No. of Lines / Field

Non-interlace

Interlace

262

263

262.5

312

313

312.5

NTSC / PAL60

PAL

3) Input formats

The digital data input format can be set as shown in the

table below, using the IM1 and IM0 pins. Both 24-bit

RGB (4: 4: 4) and 16-bit YUV (4: 2: 2) are supported. In

addition, digital RGB input can be output as analog

RGB output (RGB Through mode).

Table 4: Input format settings

IM1

IM0

Input format

R (8 bits), G (8 bits), B (8 bits)

16-bit YUV (4: 2: 2)

ROSD, GOSD, BOSD expanded to RGB input

Output signal

TV signals (9-bit resolution)

RGB analog signals (9 bits)

Multimedia ICs

BU1425AK / BU1425AKV

Table 5: Bit assignments in RGB Through mode

Output Pin

YOUT (45)

VOUT (39)

COUT (37)

BIT8

RD7

GD7

BD7

BIT7

RD6

GD6

BD6

BIT6

RD5

GD5

BD5

BIT5

RD4

GD4

BD4

BIT4

RD3

GD3

BD3

BIT3

RD2

GD2

BD2

BIT2

RD1

GD1

BD1

BIT1

RD0

GD0

BD0

BIT0

ROSD

GOSD

BOSD

The BU1425AK / AKV has an internal OSD switch and

chrominance data generating function. Consequently,

joint usage of an OSD-IC with blanking and R, G, and B

output can be easily supported by the OSD. Moreover,

a clock with half the internal processing frequency of

the BU1425AK is output from the PIXCLK pin, and can

be connected to the OSD-IC clock input, enabling the

timing to be captured.

ROSD, GOSD, and BOSD pin input is effective as long

as the OSDSW pin input is HIGH. The relationship

between OSD data and chrominance data is as shown

in Table 6 below.

Table 6: Correspondence between OSD function, input data and chrominance output

OSDSW

ROSD

GOSD

BOSD

Output Chrominance Signal

Black (blanking)

Blue

Green

Cyan

Red

Magenta

Yellow

White

Based on input specified by IM0 and IM1

4) Clock modes

With the BU1425AK / AKV, clock input is available at the

VCLK pin.

Clocks supplied from an external source should basically

be input at a frequency double that of clocks used inter-

nally (basic clock: BCLK) (when the CLKSW pin is LOW).

The phase relationship between the internal clock and

the external clock at this time is as shown in Fig. 3, with

the HSY pin input serving as a reference. In the Master

mode, in which data from the HSY pin is output and

used, HSY is output at the timing shown in Fig. 3. With

the BU1425AK, data (RD, GD, BD, etc.) is read at the ris-

ing edge of the internal clock (BCLK), so data should be

input to the BU1425AK / AKV as shown in Fig. 3.

HSY

VCLK

Internal clock (BCLK)

Input data

Fig. 3 Illustration of clock timing (CLKSW is LOW)

Multimedia ICs

BU1425AK / BU1425AKV

Also, setting the CLKSW pin to HIGH enables the fre-

quency of the external clock to be used as BCLK, the

internal clock, just as it is. Since the data is read to the

BU1425AK / AKV at the rising edge of BCLK at this

time as well, data should be input as shown in Fig. 4.

The relationship with HSY is also as shown in Fig. 4.

HSY

VCLK

Internal clock (BCLK)

Input data

Fig. 4 Illustration of clock timing (CLKSW is HIGH)

With the BU1425AK / AKV, the sub-carrier (burst) fre-

quency is generated using the internal clock. For this

reason, the frequencies used in the various modes are

limited, so those frequencies should be input (see Table

7 below).

Table 7: BU1425AK / AKV clock input frequency settings

CLKSW Pin

Video-CD Mode

27.000MHz

13.500MHz

CD-G Mode

Same for NTSC / PAL / PAL60

NTSC

28.636MHz

14.318MHz

PAL / PAL60

28.3750MHz

14.1875MHz

5) Synchronization signals

The BU1425AK / AKV has an "Encoder Master" mode in

which synchronization signals are output, and an

"Encoder Slave" mode in which synchronization signals

are input from an external source and used to achieve

synchronization. These modes are switched at the

SLABEB pin. When the SLABEB pin is LOW, the Slave

mode is in effect, and when HIGH, the Master mode is in

effect.

In the Master mode, the HSY and VSY pins serve as out-

put, with horizontal synchronization signals (HSYNC)

being output from the HSY pin and vertical synchroniza-

tion signals (VSYNC) from the VSY pin. At this time, the

reference timing for synchronization signal output is

determined at the rising edge of the RSTB pin. Output is

obtained in accordance with the specified mode (NTSC,

PAL, or PAL60, interlace or non-interlace). Output in the

non-interlace mode, however, is output only under "Odd"

field conditions (the falling edges of Hsy and Vsy are the

same).

In the Slave mode, the HSY and VSY pins serve as input,

and horizontal synchronization signals (HSYNC) should

be input to the HSY pin and vertical synchronization sig-

nals (VSYNC) to the VSY pin. The input synchronization

signals at this time should be input in accordance with

the specified mode. With the BU1425AK / AKV, field dis-

tinction between odd and even fields is made automati-

cally for each field when interlace input is used. With the

BU1425AK, all synchronization signals are treated as

negative polarity signals (signals for which the sync inter-

val goes LOW). When using the non-interlace mode,

operation is normally carried out under odd field condi-

tions (the falling edges of Hsy and Vsy are simultane-

ous).

Multimedia ICs

BU1425AK / BU1425AKV

6) Y filter

With the BU1425AK / AKV, the frequency characteristic

of Y, which is mixed with the VOUT pin output, is set so

that it can be selected using the YFILON1B and 2B pins.

A through filter is normally used on the YOUT pin output,

so that it is not limited to this method.

Table 8: Frequency characteristic of the Y channel

YFILON2B

YFILON1B

TRAP filter through

(same signal as YOUT pin output is mixed with VOUT)

Frequency characteristic of the Y channel

chart1

chart2

chart3

100

20000

10000

1000

AMPLITUDE (dB)

PHASE (deg)

FREQUENCY (kHz)

180

135

180

Gain-Phase Graphic

Fig.5 chart1 (BCLK = 13.5MHz)

100

20000

10000

1000

AMPLITUDE (dB)

FREQUENCY (kHz)

PHASE (deg)

180

135

180

Gain-Phase Graphic

Fig.6 chart2 (BCLK = 13.5MHz)

100

20000

10000

1000

AMPLITUDE (dB)

FREQUENCY (kHz)

PHASE (deg)

180

135

180

Gain-Phase Graphic

Fig.7 chart3 (BCLK = 14.318MHz)

Multimedia ICs

BU1425AK / BU1425AKV

Table 9: BU1425AK color bar input / output data

SYNC TIP

Color Burst NTSC

Color Burst PAL

BLANK LEVEL

BLACK (Pedestal)

BLUE

GREEN

CYAN

RED

MAGENTA

YELLOW

WHITE

RGB24bit

YOUT

YUV (4: 2: 2)

NAME&COLOR

Input (8-bit hexadecimal for each)

Output (9-bit hexadecimal for each)

033

038

072

096

0A0

096

072

033

038

072

096

0A0

096

072

000

072

092

117

138

0C6

0E6

16C

18C

COUT

OUT

COUT and VOUT display the chrominance amplitude. COUT is C8H

XXXH.

VOUT is YOUT

XXXH.

000

100

072

000

(4) Timing

Table 10 below shows the input and output pins related

to timing.

Table 10: BU1425AK timing-related input / output pins

Pin No.

Pin name

Function

RSTB

VCLK

CLKSW

VSY

HSY

CDGSWB

NTB

PAL60B

INT

SLABEB

ADDH

PIXCLK

I / O

System reset input pin

Clock input pin

Clock input mode setting pin

Vertical synchronization signal I / O pin

Horizontal synchronization signal I / O pin

Video-CD / CD-G mode switching pin

NTSC / PAL mode switching pin

PAL / PAL60 mode switching pin

Interlace / Non-interlace mode switching pin

Master / Slave mode switching pin

Pin which adds 1 line in non-interlace mode

1 / 2 divider output for internal clock (OSD clock)

Multimedia ICs

BU1425AK / BU1425AKV

In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise

of the RSTB pin (pin 52).

Table 13

Parameter

Symbol

Max.

Typ.

Min.

Tds3S

Tds3H

Tsd1

Tsh1

Data setup time 3S

Data hold time 3H

Sync signal setup time

Sync signal hold time

4. Slave mode, doubled clock mode

Encoder slave (pin 33 = L)

Internal clock = 2

input clock (pin 53 = L)

Tsh2

Tsd2

Input data

Input data
(HSY, VSY)

VCLK (pin53)

Tds4

Internal clock
(BCLK)

Fig.14

In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, fol-

lowing the rise of the RSTB pin (pin 52). When HSY is input, phase correction is carried out at the falling edge, as

shown in Fig. 14. (In other words, the phase of the internal clock (BCLK) is not determined until HSY is input.)

Table 14

Parameter

Symbol

Max.

Typ.

Min.

Tds4

Tsh2

Tsd2

Data setup time 4

Sync signal hold time 2

Sync signal setup time 2

Multimedia ICs

BU1425AK / BU1425AKV

2) Clock timing when the OSD function is used

Eight-color OSD color with a burster trimmer stacker fea-

ture can be used, simply by connecting an OSD with

external clock input. Output from the PIXCLK pin of the

BU1425AK should be input to the OSC-IN of the OSD IC.

The OSDSW input pin can be used as a signal for the

burster trimmer stacker feature called VBLK, or a similar

name. (See page 13 for a table showing the correspon-

dence between input data and color output.)

BLACK

YELLOW

VIDEO-DATA

Internal clock (BCLK)

HSY (IN / OUT)

PIXCLK

OSDSW

ROSD.GOSD

V.Y.C.OUT

Fig. 15 Clock timing with the OSD function

The frequency of the PIXCLK pin output is one-half that of the internal clock. This phase is determined at the rising

edge of HSY, as shown in Fig.15. (In the Encoder Master mode, phase correction is implemented using the HSY

output of the BU1425AK itself.) The OSD function is effective only during the time that video output is enabled.

(See the TV signal timing diagram on page 27.)

Multimedia ICs

BU1425AK / BU1425AKV

4) Odd / even recognition timing in Slave mode

1. Timing based on recognition of odd conditions

The BU1425AK / AKV distinguishes whether the condi-

tions of each field (each time that VSY is input) are odd

or otherwise, and internal operation is carried out based

on that recognition after the data is input. As a result,

HSY and VSY are input under input conditions appropri-

ate to the specified mode, enabling regulated output for

the first time. Odd input conditions are indicated below.

Timing that does not match these conditions is recog-

nized as an even field.

Expanded view

HSY

VSY

HSY

Tvl

VSY

Thvdiff

Fig. 18 Odd recognition conditions

Table 17: Odd recognition conditions

VSY Delay from HSY

Parameter

Symbol

Max.

Typ.

Min.

Tvl

128

VSY input L interval

Thvdiff

Unit

BCLK

HSY Rising edge

2clk

HSY falling edge

1clk

BCLK = One cycle of internal clock

Multimedia ICs

BU1425AK / BU1425AKV

2. Even timing

The BU1425AK / AKV distinguishes whether the condi-

tions of each field (each time that VSY is input) are odd

or otherwise, and internal operation is carried out based

on that recognition after the data is input. As a result,

HSY and VSY are input under input conditions appropri-

ate to the specified mode, enabling regulated output for

the first time. Timing that does not match the odd field

conditions is recognized as an even field. In order to pre-

vent malfunctioning of the internal HSY counter, howev-

er, there are regulations which apply to the timing at

which VSYNC is input in even fields.

Expanded view

HSY

VSY

HSY

T = 1 / Fhsync

1 / 2

T = 1 / Fhsync

1 / 2

The middle of HSY

Tvl

VSY

Thvdiff

Fig. 19 Even conditions

Table 18: Even conditions

Parameter

Symbol

Max.

Typ.

Min.

Tvl

128

VSY input L interval

Thvdiff

Unit

BCLK

HSY Falling edge

128clk

The middle of HYS

128clk

VSY Delay from The
middle of HSY

BCLK = One cycle of internal clock

Multimedia ICs

BU1425AK / BU1425AKV

(5) Adjustment of the DAC output level

The voltage level of the DAC output is determined by the

DAC internal output current and the DAC output external

resistor. The output current per 1 DAC bit is determined

by the external resistor of the IR pin (pin 42), as shown

below.

I (1LSB) = VVREF/RIR

1 / 16 [A] ... (equation 6-1)

VVREF ... Voltage generated by the regulator circuit in

the BU1425AK

[V]

RIR ... External resistor for the IR pin

1200[

]

Consequently, when VVREF = 1.3V and RIR = 1200

a current of 67.71

A per 1LSB is output. Because the

white level of Y is a digital value of 396 (decimal value),

the following results:

V (Y white) = 0.0677

396 = 26.81mA

At this point, if the DAC output external resistance is

37.5

, an amplitude of 1.005V

P-P

is obtained.

(6) YUV input mode

With the BU1425AK, setting the IM0 pin (pin 23) to

HIGH enables a 16-bit YUV input format to be support-

ed. At that time, the timing of U and V can be reversed

when data is input, using the H / L state of the Test2

pin.

The input conditions for this mode are shown below.

Internal clock (BCLK)

HSY

Y-Data

U.V-Data

2n + 1

Fig. 25 YUV input timing when TEST[2] = L

Internal clock (BCLK)

HSY

Y-Data

U.V-Data

2n + 1

Fig. 26 YUV input timing when TEST[2] = H

Multimedia ICs

BU1425AK / BU1425AKV

Reversal of the U and V timing using the H / L state of TEST[2] can be controlled regardless of whether CLKSW is

HIGH or LOW (the input clock is a doubled clock or not).

When using the RGB input mode, TEST[2] should be fixed at LOW.

In the Master mode, HSYNC is output at the timing shown in Fig. 26. For that reason, the timing of U and V should

be determined by counting from that falling edge. In the Slave mode, the HSY, U, and V data should be input at the

timing shown in Fig. 26.

Table 20

TEST2
(pin26)

CLKSW

(pin53)

0
0

1
1

0
1

In a doubled clock mode, the timing of U and V is as shown in Fig. 7-1.
In a regular clock mode, the timing of U and V is as shown in Fig. 7-1.

In a doubled clock mode, the timing of U and V is as shown in Fig. 7-2.
In a regular clock mode, the timing of U and V is as shown in Fig. 7-2.

External dimensions (Units: mm)

VQFP64

QFP-A64

BU1425AK

BU1425AKV

0.15

0.1

14.0

0.2

16.4

0.3

14.0

0.2

0.35

0.1

0.05

0.5

16.4

0.3

0.8

2.7

0.1

0.15

10.0

0.2

12.0

0.3

10.0

0.2

12.0

0.3

0.2

0.1

0.5

0.125

0.1

0.5

0.10

1.4

0.1

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