ADC1342X

0.13

µ
µ

m 10-BIT 30MSPS ADC

GENERAL DESCRIPTION

The adc1342x is a CMOS 10-bit low-voltage and high-speed A/D converter (ADC) for video and other
applications. It has a four-step pipelined architecture, which consists of sample & hold amplifier, multiplying D/A
converters (DACs), and subranging flash ADCs.

The maximum conversion rate of adc1342x is 30MSPS and supply voltage is 2.5V single.

FEATURES

Resolution

10-bit

-- Differential

linearity

error:

1.0LSB

-- Integral

linearity

error:

2.0LSB

-- Maximum

conversion

rate:

30MSPS

-- Sample

hold

function

implemented

-- Low

power

consumption:

75mW (Typ)

-- Power

supply:

2.5V

single

-- Operation

temperature

range:

C ~ 85

TYPICAL APPLICATIONS

-- CCD imaging processors

-- Camcorders, scanners, and security cameras.

-- Read channel LSI

HDD, DVD, and CD-ROM drives

-- IF and baseband signal digitizers

-- Portable equipments for low-power applications

0.13

µ
µ

m 10-BIT 30MSPS ADC

ADC1342X

FUNCTIONAL BLOCK DIAGRAM

Flash1

SHA

MDAC1

Flash2

MDAC2

Flash3

MDAC3

Flash4

Digital Correction Logic (DCL)

Bias

Current

Generator

Clock

Generator

CML Level

Generator

STC

ITEST

CKIN

AINT

AINC

EOC

DO[9:0]

CML

REFTOP

REFBOT

AVDD25A

AVSS25A

AVBB25A

AVDD25D

AVSS25D

AVBB25D

SPEEDUP

Ver 1.0 (Apr. 2002)
This data sheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents
or other rights of third parties that may result from its use. The content of this data sheet is subject to change without any
notice.

ADC1342X

0.13

µ
µ

m 10-BIT 30MSPS ADC

CORE PIN DESCRIPTION

Name

I/O Type

I/O Pad

Pin Description

AINT

pmiar10_abb

Analog

input

(

0.95V

1.55V)

AINC

pmiar10_abb

Analog

input

(1.55V ~ 0.95V)

REFTOP

pmia_abb

Reference

top

(1.55V)

REFBOT

pmia_abb

Reference

bottom (0.95V)

AVDD25A

vdd25tm_abb

Analog

power

(2.5V)

AVSS25A

vsstm_abb

Analog

ground

AVBB25A

vbbm_abb

Analog

sub

bias

ITEST

pmia_abb

Test pin (normally, open)

pmicc_abb

Power down

mode (normally,

gnd)

STC

pmicc_abb

Start

conversion

signal

(normally,

high)

SPEEDUP

pmicc_abb

Speed

test

pin (normally,

gnd)

CKIN

pmicc_abb

Sampling

clock

input

CML

pmoa_abb

Test

pin (normally, open)

DO[9:0]

pmot8_abb

Digital

output

EOC

pmot8_abb

End

conversion

signal

AVBB25D

vbbm_abb

Digital

sub

bias

AVSS25D

vsstm_abb

Digital

ground

AVDD25D

vdd25tm_abb

Digital

power

I/O

Type

Abbr.

-- AI: Analog Input

-- DI: Digital Input

-- AO: Analog Output

-- DO: Analog Output

-- AP: Analog Power

-- AG: Analog Ground

-- DP: Digital Power

-- DG: Digital Ground

-- AB: Analog Bi-Direction

-- DB: Digital Bi-Direction

ADC1342X

0.13

µ
µ

m 10-BIT 30MSPS ADC

ABSOLUTE MAXIMUM RATINGS

Characteristic

Symbol

Value

Unit

Supply voltage

VDD

3.6

Analog input voltage

AIN

VSS to VDD

Digital input voltage

CLK

VSS to VDD

Digital output voltage

, V

VSS to VDD

Storage temperature range

Tstg

45 to 150

NOTES:
1.

Absolute

maximum

rating

specifies

the

values

beyond

which

the

device

may

damaged

permanently.

Exposure

absolute

maximum

rating

conditions

for

extended

periods

may

affect

reliability.

Each

condition

value

applied

with

the

other

values

kept

within

the

following

operating

conditions

and

function

operation

under

any

these

conditions

not

implied.

All

voltages

are

measured

with

respect

VSS

unless

otherwise

specified.

100pF

capacitor

discharged

through

1.5k

resistor

(Human

body

model).

RECOMMENDED OPERATING

CONDITIONS

Characteristics

Symbol

Min

Typ

Max

Unit

Supply voltage

AVDD25A AVSS25A

AVDD25D AVSS25D

2.38

2.5

2.63

Supply voltage difference

AVDD25A AVDD25D

0.1

0.0

0.1

Reference input voltage (externally)

REFTOP
REFBOT

1.55
0.95

Analog input voltage (+)

AINT

0.95

1.55

Analog input voltage (-)

AINC

1.55

0.95

Operating temperature

Topr

NOTE: is

strongly

recommended

that

all

the

supply

pins

(AVDD25A,

AVDD25D)

powered

from

the

same

source

avoid

power

latch-up.

0.13

µ
µ

m 10-BIT 30MSPS ADC

ADC1342X

DC ELECTRICAL

CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Conditions

Resolution

Bits

Reference current

IREF

Differential linearity error

DLE

1.0

LSB

Integral linearity error

ILE

2.0

LSB

Bottom offset voltage error

EOB

LSB

Top offset voltage error

EOT

LSB

NOTES:
1.

Converter

specifications

(unless

otherwise

specified)

AVDD25A=2.5V

AVDD25D=2.5V

AVSS25A=GND

AVSS25D=GND

Ta=25

TBD:

determined

AC ELECTRICAL CHARACTERISTICS

Characteristics

Symbol

Min

Typ

Max

Unit

Conditions

Maximum conversion rate

MSPS

Dynamic supply current

Ivdd

fc = 30MHz
(without system load)

Digital output data delay

1.8

See
"Timing Diagram"

Signal - to - noise ratio

SNR

AINT = 1MHz
fc = 30MHz

ADC1342X

0.13

µ
µ

m 10-BIT 30MSPS ADC

I/O

CHART

Index

AINT Input (V)

AINC Input (V)

Digital Output

0.950000 ~ 0.950587

1.549413 ~ 1.550000

0000000000

1LSB = 1.1730mV
for differential input

0.950587 ~ 0.951174

1.548826 ~ 1.549413

0000000001

REFTOP = 1.55V

0.951174 ~ 0.951761

1.548239 ~ 1.548826

0000000010

REFBOT = 0.95V

511

1.249413 ~ 1.250000

1.250578 ~ 1.251174

0111111111

512

1.250000 ~ 1.250578

1000000000

513

1.250578 ~ 1.251174

1.249413 ~ 1.250000

1000000001

1021

1.548239 ~ 1.548826

0.951174 ~ 0.951761

1111111101

1022

1.548826 ~ 1.549413

0.950587 ~ 0.951174

1111111110

1023

1.549413 ~ 1.550000

0.950000 ~ 0.950587

1111111111

0.13

µ
µ

m 10-BIT 30MSPS ADC

ADC1342X

TIMING DIAGRAM

1. Main Waveform

STC

EOC

DO[9:0]

CKIN

Analog

Input

Pipeline Delay

Output code of DO[9:0] is generated during STC (Start of Conversion) signal is just "HIGH". Otherwise, it keeps
the current states.

After STC goes "HIGH", the A/D converter requires the pipeline delay of 3 clock period to generate EOC signal
and DO[9:0].

2. STC & CKIN

8ns

CKIN

STC

4ns

SAFE

. . .

8ns

4ns

SAFE

The STC signal is rising-edge triggered, and it should be changed during "T

SAFE

" region on CKIN.

ADC1342X

0.13

µ
µ

m 10-BIT 30MSPS ADC

CORE EVALUATION GUIDE

ADC function is evaluated by external check on the bi-directional pads connected to input nodes of HOST DSP
back-end circuit.
The reference voltages may be biased internally through resistor divider.

DO[9:0]

EOC

Digital Mux

HOST

DSP

CORE

Bi-Directional PAD

(ADC Function Measuring &

Digital Input Forcing)

Analog Input

Clock Input

AINT

AINC

CKIN

AVDD25A

AVSS25A

AVBB25A

AVSS25D

AVBB25D

AVDD25D

REFTOP

REFBOT

SPEEDUP

STC

CML

ITEST

10-bit Digital Output

2.5V

GND

2.5V

GND

1.55V

GND

0.95V

GND

Reference
Top

Reference

Bottom

GND

STC Input

or 2.5V

GND

NOTES:
: 10uF electronic capacitor unless otherwise specified
: 0.1uF ceramic capacitor unless otherwise specified

adc1342x

0.13

µ
µ

m 10-BIT 30MSPS ADC

ADC1342X

PACKAGE CONFIGURATION

adc1342x_top

REFTOP

REFBOT

CML

AVDD25A

AVBB25A

AVSS25A

AINT

AINC

SPEEDUP

ITEST

AVDD25R

AVSS25R

CKIN

AVDD25D

AVSS25D

AVDD25D

STC

DO[9]

DO[8]

DO[7]

DO[6]

DO[5]

DO[4]

DO[3]

DO[2]

DO[1]

DO[0]

0.1u

10u

EOC

0.1u

10u

0.1u

10-bit ADC

Output

STC In

EOC Out

2.5V

1.55V

10u

0.1u

0.95V

0.1u

2.5V

10u

0.1u

Clock In

2.5V

Test Pin
No bisa forcing, remain floating

Analog

Input

0.1u

NOTE: This information is for testing the provided test-chips of ADC1342X.

ADC1342X

0.13

µ
µ

m 10-BIT 30MSPS ADC

PACKAGE PIN DESCRIPTION

Name

Pin No.

I/O Type

Pin Description

REFTOP

1, 2

External reference top bias (1.55V)

REFBOT

3, 4

External reference bottom bias (0.95V)

CML

Internal bias point (test pin)

AVDD25A

6, 7

Analog power (2.5V)

AVBB25A

Analog sub bias

AVSS25A

9, 10

Analog ground

AINT

Analog input + (Input range: 0.95~1.55V differential)

AINC

Analog input. - (Input range: 1.55~0.95V differential)

SPEEDUP

Speed test pin. Tie to analog GND

ITEST

Open = Use internal bias point

Power Down mode (normally gnd)

AVDD25R

Output driver power (2.5V)

AVSS25R

Output driver ground

CKIN

Sampling clock input

DO[9:0]

27~36

10-bit digitized output

EOC

End of conversion signal

STC

Start of conversion signal

AVBB25D

Digital substrate bias

AVSS25D

45, 46

Digital ground

AVDD25D

47, 48

Digital power (2.5V)

NOTES:
1.

This information is for testing the provided test-chips of ADC1342X.

I/O

TYPE

and

denote

PAD

Power

and

PAD

Ground

respectively.

0.13

µ
µ

m 10-BIT 30MSPS ADC

ADC1342X

USER GUIDE

1. Input Signal Range

The ADC was designed to use both single and differential mode input, but the differential mode is recommended
to guarantee the operating margin in the low voltage condition.

-- Differential Mode Input Condition

Pin

Input Range

Conditions

AINT

0.95V ~ 1.55V

AINC

1.55V ~ 0.95V

180

phase shifted input with the same DC level with AINT

-- Single Mode Input Condition

Pin

Input Range

Conditions

AINT

0.65V ~ 1.85V

AINC

1.25V

Forced from the clean DC source or CML pin of ADC1342X

2. Input Signal Speed

Normal speed range of ADC1342X is 1MHz ~ 4MHz input quantized by 30MHz clock, which is fixed by a normal
video signal format.

ADC1342X

0.13

µ
µ

m 10-BIT 30MSPS ADC

PHANTOM CELL INFORMATION

Pins of the core can be assigned externally (package pins) or internally (internal ports) depending on design
methods.

The term "External" implies that the pins should be assigned externally like power pins.
The term "External/internal" implies that the applications of these pins depend on the user.

adc1342X

10-bit 30MSPS adc

AVDD25D

AVBB25D

AVSS25D

EOC

STC

DO[9]

DO[8]

DO[7]

DO[6]

DO[5]

DO[4]

DO[3]

DO[2]

DO[1]

DO[0]

CKIN

AVDD25D

AVBB25D

AVSS25D

SPEEDUP

ITEST

REFBOT

CML

REFTOP

AINT

AINC

AVSS25A

AVBB25A

AVDD25A

AVSS25A

AVBB25A

AVDD25A

0.13

µ
µ

m 10-BIT 30MSPS ADC

ADC1342X

Pin Name

Pin Usage

Pin Layout Guide

AVDD25A

External

Maintain the large width of lines as far as the pads.

AVSS25A

External

Place the port positions to minimize the length of power lines.

AVBB25A

External

Do not merge the analog powers with anoter power from other
blocks.

AVDD25A

External

Use good power and ground source on board.

AVSS25D

External

AVBB25D

External

AINT

External / Internal

Do not overlap with digital lines.

AINC

External / Internal

Maintain the shotest path to pads.

CKIN

External / Internal

Separate from all other analog signals

REFTOP

External / Internal

Maintain the larger width and the shorter length as far as the
pads.

REFBOT

External / Internal

Separate from all other digital lines.

CML

External / Internal

ITEST

External / Internal

STC

External / Internal

SPEEDUP

External / Internal

EOC

External / Internal

Separated from the analog clean signals if possible.

DO[9]

External / Internal

Do not exceed the length by 1,000um.

DO[8]

External / Internal

DO[7]

External / Internal

DO[6]

External / Internal

DO[5]

External / Internal

DO[4]

External / Internal

DO[3]

External / Internal

DO[2]

External / Internal

DO[1]

External / Internal

DO[0]

External / Internal

ADC1342X

0.13

µ
µ

m 10-BIT 30MSPS ADC

FEEDBACK

REQUEST

It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the
following characteristic checking table and fill out the additional questions.

We appreciate your interest in our products. Thank you very much.

Characteristic

Min

Typ

Max

Unit

Remarks

Analog power supply voltage

Digital power supply voltage

Bit resolution

Bit

Reference input voltage

Analog input voltage

Vpp

Operating temperature

Integral non-linearity error

LSB

Differential non-linearity error

LSB

Bottom offset voltage error

Top offset voltage error

Maximum conversion rate

MSPS

Dynamic supply current

Power dissipation

Signal-to-noise ratio

Pipeline delay

CLK

Digital output format (provide detailed
description & timing diagram)

-- Between single input-output and differential input-output configurations, which one is suitable for your system

and why?

-- Please comment on the internal/external pin configurations you want our ADC to have, if you have any

reason to prefer some type of configuration.

-- Freely list those functions you want to be implemented in our ADC, if you have any.

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