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AFE1400X

GENERAL

DESCRIPTION

The samsung analog front end(AFE) for CCD/CIS image signal is an integrated analog signal processor for color
image signal.

The AFE converts CCD/CIS output signal to digital data. The AFE includes three-channel CDS(Correlated Double
Sampling) circuit, PGA(Programmable Gain Amplifier), and 12-bit analog to digital converter with reference
generator.

The 12-bit digital output is multiplexed into an 8-bit output word that is accessed using 8+4 format two read cycles.
The internal resgisters are programmed through a 3-wire serial interface, and provide adjustment of the gain,
offset, and operating mode.

APPLICATIONS

-- Color and B/W Scanner

-- Digital Copiers

-- General Purpose CCD/CIS imager

FEATURES

-- 12-bit 20 MSPS A/D Converter

-- Integrated Triple Correlated Double Sampler

-- 3-Channel 2 MSPS Color Mode

-- 1 ~ 6.25x Analog Programmable Gain Amplifier

-- Internal Voltage Reference

-- No Missing Code Guaranteed

-- Multiplexed Byte-Wide Output (8+4 Format)

-- 3-Wire Serial Digital Interface

-- Operation by Single 3.3V Supply

-- CMOS Low Power Dissipation

-- 28-SOP-375 Package

KEY

SPECIFICATION

-- Resolution: 12-bit

-- Conversion Rate: 20 MHz(2 MHz*3)

-- Supply Voltage: 3.3 V ± 5%

-- Power Dissipation: 415 mW(Typical)

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AFE1400X

CORE

PIN

DESCRIPTION

Name

I/O Type

I/O Pad

Description

AVDDA

vdda

3.3 V Analog Supply

AVSSA

vssa

Analog Ground

AVDDD

vdda

3.3 V Digital Supply

AVSSD

vssa

Digital Ground

AVBBA

vbba

Analog Substrate

AVBBD

vbba

Digital Substrate

REFT

poa_bb

Reference Decoupling

REFB

poa_bb

Reference Decoupling

VCOM

poa_bb

Analog Common Voltage

R_VIN

piar10_bb

Analog Input; Red

G_VIN

piar10_bb

Analog Input; Green

B_VIN

piar10_bb

Analog Input; Blue

OFFSET

piar10_bb

Clamp Bias Level Decoupling

CDS1_CLK

picc_bb

CDS Reset Clock Pulse Input

CDS2_CLK

picc_bb

CDS Data Clock Pulse Input

ADCCLK

picc_bb

A/D Converter Sample Clock Input

SDATA

poa_bb

Serial Interface Data Input/Output

SCLK

picc_bb

Serial Interface Clock Input

SLOAD

picc_bb

Serial Interface Load Pulse

OEB

picc_bb

Output Enable; Active Low

D[7:0]

pot4_bb

Data Outputs

I/O Type Abbr.

-- AI: Analog Input

-- DI: Digital Input

-- AO: Analog Output

-- DO: Digital Output

-- AB: Analog Bidirectional

-- DB: Digital Bidirectional

-- AP: Analog Power

-- DP: Digital Power

-- AG: Analog Ground

-- DG: Digital Ground

AFE1400X

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CODE CONFIGURATION

afe_cip4

ADCCLK

D[7:0]

REFT

SDATA
SCLK
SLOAD

CDS2_CLK

CDS1_CLK

G_VIN

B_VIN

R_VIN

VCOM REFB

AVDDA

AVSSA

AVDDD

AVSSD

AVBBA

OEB

OFFSET

AVBBD

ABSOLUTE MAXIMUM

RATINGS

Characteristic

Symbol

Value

Unit

Supply Voltage

VDD

4.5

Analog Input Voltage

AIN

VSS to VDD

Digital Input Voltage

CLK

VSS to VDD

Digital Output Voltage

, V

VSS to VDD

Reference Voltage

VRT/VRB

VSS to VDD

Storage Temperature Range

Tstg

-45 to 150

Operating Temperature Range

Topr

0 to 70

NOTES:
1.

ABSOLUTE

MAXIMUM

RATING

specifies

the

values

beyond

which

the

device

may

damaged

permanently.

Exposure

ABSOLUTE

MAXIMUM

RATING

conditions

for

extended

periods

may

affect

reliability.

Each

condition

value

applied

with

the

other

values

kept

within

the

following

operating

conditions

and

function

operation

under

any

these

conditions

not

implied.

All

voltages

are

measured

with

respect

VSS

unless

otherwise

specified.

100pF

capacitor

discharged

through

1.5k

resistor

(Human

body

model)

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AFE1400X

ANALOG SPECIFICATIONS

(VDDA1=3.3V, VDDA2=3.3V, ADCCLK=20MHz, CDS1_CLK=6.666MHz,CDS2_CLK=6.666MHz, PGA Gain=1
unless otherwise noted)

Characteristics

Symbol

Min

Typ

Max

Unit

Comment

Resolution

Bits

Conversion Rate
3-Channel with CDS
1-Channel with CDS

MSPS
MSPS

Signal-to-Noise & Distortion
Ratio @ 1MHz Input

SNDR

Entire

Signal Path

Differential
Nonlinearity

DNL

LSB

Integral
Nonlinearity

INL

LSB

Unipolar Offset Error

1.0

%FSR

Gain Error

2.0

%FSR

Analog Input
Full-Scale Input
Input Capacitance
Reference Top
Reference Bottom

0.04

2.2
1.0

2.4

Vp-p

V
V

Amplifier
PGA Gain
PGA Resolution
OFFSET Range
OFFSET Resolution

-200

6

9

6.25

+200

V/V

Bits

Power Supply
Analog Voltage
Digital Voltage
Analog Current
Digital Current

VDDA1
VDDA2

IDD1
IDD2

3.3
3.3

120

V
V

mA
mA

3.3V

Power Consumption

415

Temperature Range

Operating

AFE1400X

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DIGITAL SPECIFICATIONS

(VDDA1=3.3V, VDDA2=3.3V, ADCCLK=20MHz, CDS1_CLK=6.666MHz, CDS2_CLK=6.666MHz, C

=20pF unless

otherwise noted)

Characteristics

Symbol

Min

Typ

Max

Unit

Comment

High

Level

Input

Voltage

2.0

Low

Level

Input

Voltage

0.7

High

Level

Input

Current

Low

Level

Input

Current

High

Level

Output

Voltage

3.0

= 0.5mA

Low

Level

Output

Voltage

0.3

= -0.5mA

TIMING SPECIFICATIONS

(VDDA1=3.3V, VDDA2=3.3V unless otherwise noted)

Characteristics

Symbol

Min

Typ

Max

Unit

CLOCK CHARACTERISTICS

3-Channel Conversion Rate

150

1-Channel Conversion Rate

CDSCLK1 Pulse Width

C1CLK

CDSCLK2 Pulse Width

C2CLK

CDSCLK2B Pulse Width

C2CLKB

CDSCLK1 Falling to CDSCLK2 Rising

C1C2A

CDSCLK2 Falling to CDSCLK1 Rising

C2C1A

ADCCLK Pulse Width

ADCLK

CDSCLK2 Rising to ADCCLK Rising

C2ADA

CDSCLK2 Falling to ADCCLK Falling

C2ADB

ADCCLK Rising to CDS2CLK Falling

ADC2A

Aperture Delay

SERIAL INTERFACE

Maximum SCLK Frequency

CLK

MHz

SLOAD to SCLK Set-up Time

SCLK to SLOAD Hold Time

SDATA to SCLK Rising Set-up Time

SCLK Rising to SDATA Hold Time

SCLK Falling to SDATA Valid

RDV

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AFE1400X

TIMING SPECIFICATIONS

(VDDA1=3.3V, VDDA2=3.3V unless otherwise noted)

Characteristics

Symbol

Min

Typ

Max

Unit

DATA OUTPUT

ADC Output Delay

ADDT

Tri-State to Data Valid

DEV

Output Enable High to Tri-State

ADC Latency(Pipeline Delay)

ADCCLK

Cycles

NOTE: Aperture

delay

timing

measurement

between

the

sampling

clocks

and

CDS.

measured

from

the

falling

edge

the

CDS2_CLK

input

when

the

input

signal

held

for

data

conversion

AFE1400X

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TIMING

DIAGRAM

3-Channel CDS Mode

Analog
Input

CDS1_CLK

CDS2_CLK

ADCCLK

OUTPUT

D[7:0]

C1C2A

C2C1A

C1CLK

C2ADA

ADC2A

C2CLKB

ADCLK

R0,G0,B0

R1,G1,B1

R2,G2,B2

R-2 R-2 G-2 G-2 B-2 B-2 R-1 R-1 G-1 G-1 B-1 B-1 R0 R0 G0 G0 B0 B

ADDT

3-Channel SHA Mode

Analog
Input

CDS2_CLK

ADCCLK

R0,G0,B0

R1,G1,B1

R2,G2,B2

C2ADA

ADC2A

C2CLKB

ADCLK

OUTPUT

D[7:0]

R-2 R-2 G-2 G-2 B-2 B-2 R-1 R-1 G-1 G-1 B-1 B-1 R0 R0 G0 G0 B0 B

ADDT

AFE1400X

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Digital Output Data Timing

ADCCLK

OUTPUT

D[7:0]

Low

Byte

High Byte

D13-D6

D5-D0

Low

High

Low

ADDT

DEV

OEB

Serial Write Operation Timing

SCLK

SDATA

R/Wb A2 A1 A0 XX XX XX D8 D7 D6 D5 D4 D3 D2 D1 D0

SLOAD

Serial Read Operation Timing

SCLK

SDATA

R/Wb A2 A1 A0 XX XX XX D8 D7 D6 D5 D4 D3 D2 D1 D0

SLOAD

RDV

'Read' means microcontroller reads SDATA.

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AFE1400X

FUNCTIONAL

DESCRIPTION

1) 3-Channel Operation with CDS

This mode enables simultaneous sampling of a triple output CCD. The CCD waveforms are ac coupled to the
R_VIN, G_VIN and B_VIN pins where they are automatically biased at an appropriate voltage using the on-
chip clamp. The internal CDSs take two samples of the incoming pixel data; the first samples are taken during
the reset time while the second samples are taken during data portion of the input pixels.

2) 3-Channel SHA Operation

This mode enables simultaneous sampling of a triple output CIS or something like that. The CDS functions
are replaced with the sample and hold amplifiers. The input waveforms are either dc coupled or dc restored to
the R_VIN, G_VIN and B_VIN pins. The input reference voltage in this mode will be defined by external
OFFSET pin.

3) 1-Channel Operation with CDS

This mode enables single channel or monochrome sampling. The CCD waveforms are ac coupled to the
analog input pin where they are automatically biased at an appropriate voltage using the on-chip clamp.

Bit4, bit5 and bit6 in MUX register select the desired input among red, green and blue.

4) 1-Channel SHA Operation

This mode enables single-channel or monochrome sampling. The CDS function is replaced with the sample
and hold amplifier.

The input waveforms are either dc coupled or dc restored to the analog input pin. The input reference voltage
in this mode will be defined by clamp level control register.

Bit4, bit5 and bit6 in MUX register select the desired input among red, green and blue.

AFE1400X

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MAIN BLOCK

DESCRIPTION

1) Programmable Gain Amplifier

The analog programmable gain can accommodate a wide range of input voltage spans. The transfer function
of the PGA is as follows.

H(X) = 1/12*X + 1,

where the range of X is 0 to 63.

Thus, the minimum gain value is equal to 1, and the maximum gain value is equal to 6.25. The transfer
function has linearity in linear scale. The overall gain is equal to analog gain multiplied by digital gain. So,
the multiplier should be required in back end of AFE.

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AFE1400X

BLOCK

DIAGRAM

Input Offset

(R,G,B)

CDS

PGA

12-bit
ADC

REF

PGA Gain

(R,G,B)

Configuration

R_VIN

RED

G_VIN

GREEN

B_VIN

BLUE

CDS1_CLK

CDS2_CLK

ADCCLK

OEB

SCLK

D[7:0]

OFFSET

MPU

PORT

VDDA1 VSSA1

VCOM

VDDA2 VSSA2

REFT

REFB

CDS

PGA

CDS

CLAMP

PGA

R_GAIN[5:0]

G_GAIN[5:0]

B_GAIN[5:0]

R_OFFSET[8:0]

G_OFFSET[8:0]

B_OFFSET[8:0]

R_OFFSET[8:0]

G_OFFSET[8:0]

B_OFFSET[8:0]

B_GAIN[5:0]

R_GAIN[5:0]

G_GAIN[5:0]

MUX

SDATA

VDDDR VSSDR

DAC

12:8

MUX

SLOAD

AFE1400X

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2) INTERNAL REGISTER OVERVIEW

The internal register map is accessed through serial data pin SDATA's A0, A1 and A2.

Register Map

Register

Address

Data Bits

Configuration

3Ch/

1Ch

CDS

PWR

MUX

RGB/

BGR

Red

Green

Blue

Red PGA

MSB

LSB

Green PGA

MSB

LSB

Blue PGA

MSB

LSB

Red Offset

MSB

LSB

Green Offset

MSB

LSB

Blue Offset

MSB

LSB

Configuration Register

Set to 0

# of Channels

CDS Operation

Power Down

Set to 0

1=3-CH mode*

0=1-CH mode

1=CDS Mode*

0=SHA Mode*

1=On

0=Off(Operation)*

NOTE: Power-on Default Value, X: Don't care

MUX Register

Set to 0

3-CH Select

1-CH

Set to 0

1=R-G-B*

0=B-G-R

1=RED*

0=Off

1=Green

0=Off*

1=Blue

0=Off*

NOTE: Power-on Default Value

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AFE1400X

PGA Gain Register

(MSB)

(LSB)

Gain
(V/V)

Gain

(dB)

1.083

0.693

1.167

1.341

. . .

6.167

15.801

6.25

15.918

NOTE: Power-on Default Value.

Offset Register

D8(MSB)

Sign Bit

(LSB)

Offset

(mV)

0.781

1.563

. . .

200

-0.781

-1.563

. . .

-200

NOTE: Power-on Default Value.

AFE1400X

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OVERALL TRANSFER

FUNCTION

The overall transfer function can be calculated as follows.

ADC

out

=[(Vin+Input_Offset)* PGA_Gain]/(2*REF)*4096,

where REF is equal to (REFT-REFB) and Input _Offset means the DAC value of the input offset register. The
analog offset range of the input offset register is varied between 200mV and -200 mV. The 9-bit data format for
the input offset register is sign magnitude, with D8 as the sign bit.

To maximize the dynamic range of the ADC input, it is necessary to program the input offset register code to
move the ADC code corresponding to the black level towards 'zero'.

And also PGA_gain is to maximize the dynamic range of the 12-bit ADC's input. The PGA_gain range is varied
between 1 and 6.25 by PGA gain register. The 6-bit data format for the PGA gain register is straight binary coding.

INPUT COUPLING

CAPACITOR

Because of the DC offset present at the output of CCD, some kind of DC restoration is required. In case of
CDS enable mode, to simplify input level shifting, a DC decoupling capacitor is used in conjuction with the
internal input circuitry.

The capacitor charging or discharging depends on the clamping time, the analog input resistance of the AFE and
the output resistance of the circuit driving the coupling capacitor.

The clamping time is typically (n*T), where n is the number of periods CDSCLK1 is asserted and T is the period
of assertion. CDSCLK2 should not be asserted during clamping time. The analog input resistance of the AFE's
Clamp is equal to 1 kW. The recommended input coupling capacitor is more than 0.1uF. The time constant of the
input clamp is determined by the internal 1K resistance and the external 0.1uF input capacitance. Thus, to extend
the clamping time, the time a transport motor moves the scanner carriage can be available, for example.

AFE1400X

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m 12-BIT 20MSPS AFE FOR CCD/CIS SIGNAL PROCESSOR

CALIBRATION

Decide clamp level for SHA mode

(Refer to next page)

Set PGA gain

(Input offset = 0 mV)

Set another color

YES

Scan dark line

Compute pixel offsets

Set input offset

Set odd/even offset in back end

Set gain/offset bus size

in back end

Set external pixel offset

in back end

Scan white line

Compute pixel gains

in back end

Adjust PGA gain

YES

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AFE1400X

CORE EVALUATION

GUIDE

0.1u

TIMING GENERATOR

MPU INTERFACE

DSP ASIC

MUX

Externally forced digital input/output

afe_cip4

ADCCLK

D[7:0]

REFT

SDATA
SCLK
SLOAD

CDS2_CLK

CDS1_CLK

G_VIN

B_VIN

R_VIN

VCOM REFB

AVDDA

AVSSA

AVDDD

AVSSD

AVBBA

OEB

OFFSET

AVBBD

AFE1400X

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APPLICATIONS INFORMATION

CDS Mode Applications

-- The recommended input coupling capacitor value is 0.1uF.

-- A single ground plane is recommended for the afe_cip4. Thus the digital pins should be well decoupled to the

analog ground plane.

-- If possible, a separate power supply should be used for VDDDR, but this supply pin should still be decoupled

to the same ground plane as the rest of the afe_cip4.

-- The loading of digital outputs should be minimized.

-- All 0.1uF decoupling capacitors should be located as close as possible to the afe_cip4 pins.

-- When operating in single channel mode, the unused analog inputs must be grounded.

D7(MSB)

VSSDR

VDDDR

ADCCLK

CDSCLK

OEB

D0(LSB)

B_VIN

VCOM

G_VIN

R_VIN

VSSA2

VDDA2

OFFSET

REFT

SCLK

SLOAD

VDDA1

REFB

VSSA1

SDATA

afe_cip4

0.01u

0.1u

0.01u

0.1u 1.0u

0.1u

10u

0.1u

Data Outputs

3-Channel CDS Mode Application Circuit Configuration

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AFE1400X

SHA Mode Applications

-- All of the CDS mode's considerations also apply for this configuration, except that analog inputs are directly

connected to the afe_cip4 without coupling capacitors.

-- The OFFSET pin may be used in a CIS application for DC offset adjustment. By connecting the appropriate dc

voltage to the OFFSET pin, the CIS signal will be restored to "zero".

3-Channel SHA Mode Application Circuit Configuration

D7(MSB)

VSSDR

VDDDR

ADCCLK

CDSCLK

OEB

D0(LSB)

B_VIN

VCOM

G_VIN

R_VIN

VSSA2

VDDA2

OFFSET

REFT

SCLK

SLOAD

VDDA1

REFB

VSSA1

SDATA

afe_cip4

0.1u

10u

0.1u

Data Outputs

AFE1400X

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m 12-BIT 20MSPS AFE FOR CCD/CIS SIGNAL PROCESSOR

PACKAGE PIN

DESCRIPTION

Pin No.

Pin Name

I/O Type

Description

CDS1_CLK

CDS Reference Sampling Clock

CDS2_CLK

CDS Data Sampling Clock

ADCCLK

A/D Converter Clock

OEB

Output Enable (Active Low)

VDDDR

Output Buffer Power

VSSDR

Output Buffer Ground

D[7]

Digital Output (MSB)
High Byte: D13, Low Byte: D5

D[6]

Digital Output (D12, D4)

D[5]

Digital Output (D11, D3)

D[4]

Digital Output (D10, D2)

D[3]

Digital Output (D9, D1)

D[2]

Digital Output (D8, D0)

D[1]

Digital Output (D7, X)

D[0]

Digital Output (LSB)
High Byte: D6, Low Byte: X(Don't care)

SDATA

Serial Interface Data Input/Output

SCLK

Serial Interface Clock Input

SLOAD

Serial Interface Load Pulse

VDDA1

Analog Power

VSSA1

Aanlog Ground

REFB

Reference Decoupling

REFT

Reference Decoupling

B_VIN

Analog Input: Blue

VCOM

Analog Common Voltage

G_VIN

Analog Input: Green

OFFSET

Clamp Bias Level Decoupling

R_VIN

Analog Input: Red

VSSA2

Digital Ground

VDDA2

Digital Power

AFE1400X

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m 12-BIT 20MSPS AFE FOR CCD/CIS SIGNAL PROCESSOR

QUESTIONNAIRE FOR ANALOG CORE

Characteristics

Symbol

Min

Typ

Max

Unit

Comment

Resolution

Bits

Signal-to-Noise & Distortion
Ratio

SNDR

Conversion Rate
3-Channel with CDS
1-Channel with CDS

MSPS
MSPS

Differential
Nonlinearity

DNL

LSB

Integral
Nonlinearity

INL

LSB

Unipolar Offset Error

%FSR

Gain Error

%FSR

Anlog Input
Full-Scale Input

Vp-p

Power Supply
Analog Voltage
Digital Voltage

VDDA
VDDD

V
V

Power Consumption

Temperature Range

-- What do you want to choose as power supply voltages?

For example, the analog VDD needs to be 3.3V. The digital VDD can be 2.5V/3.3V.

-- Which modes of AFE do you use for overall system ? (Refer to page 9)

For example: 3channel operation with CDS / 3channel SHI(CIS) operation
1channel operation with CDS / 1channel SHI(CIS) operation

-- Would you define the gain range and input offset range ?

-- Could you explain external/internal pin configurations as required?

-- If possible, present other requirements below.

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AFE1400X