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GENERAL

DESCRIPTION

The samsung analog front end(AFE) for CCD/CIS image signal is an integrated analog signal processor for color
image signal.

The AFE converts CCD/CIS output signal to digital data. The AFE includes three-channel CDS(Correlated Double
Sampler) circuit, PGA(Programmable Gain Amplifier), and 10-bit analog to digital converter with reference
generator.

A parallel data bus provides a simple interface to 8-bit microcontroller.

APPLICATIONS

-- Color and B/W Scanner

-- Digital Copiers

-- Facsimile

-- General Purpose CCD/CIS imager

FEATURES

-- 10-bit 6MSPS A/D Converter

-- Integrated Triple Correlated Double Sampler

-- 3-Channel 2 MSPS Color Mode

-- Analog Programmble Gain Amplifier

-- Internal Voltage Reference

-- Wide clamp level controllability for CIS signal

-- No Missing Code Guaranteed

-- Microcontroller-Compatible Control Interface

-- Operation by 3.3V Power Supply

-- CMOS Low Power Dissipation

KEY

SPECIFICATION

-- Resolution: 10-bit

-- Conversion Rate: 6 MHz(2 MHz*3)

-- Supply Voltage: 3.3 V ± 5%

-- Power Dissipation: 250 mW(Typical)

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CORE

PIN

DESCRIPTION

Name

I/O Type

I/O Pad

Description

VDDA1, VDDA2

vdda

Analog Supply

VSSA1, VSSA2

vssa

Analog Ground

VBB

vbba

Analog Bulk

REFT

pia_bb

Reference Decoupling

REFB

pia_bb

Reference Decoupling

VCOM

pia_bb

Analog Common Voltage

R_VIN

piar10_bb

Analog Input; Red

G_VIN

piar10_bb

Analog Input; Green

B_VIN

piar10_bb

Analog Input; Blue

STRTLN

picc_bb

STRTLN indicates beginning of line

CDS1_CLK

picc_bb

CDS Reset Clock Pulse Input

CDS2_CLK

picc_bb

CDS Data Clock Pulse Input

ADCCLK

picc_bb

A/D Converter Sample Clock Input

VDDA3

vddd

Digital Supply (2 pins;VDDA3, VDDA4)

VSSA3

vssd

Digital Ground (2 pins;VSSA3, VSSA4)

CSB

picc_bb

Chip Select; Active Low

WRB

picc_bb

Write Strobe; Active Low

RDB

picc_bb

Read Strobe; Active Low

OEB

picc_bb

Output Enable; Active Low

D[9:0]

poa_bb

Data Inputs/Outputs

AD[2:0]

picc_bb

TEST_S1, TEST_S2

picc_bb

Channel Select in Test Mode

TEST_CTL

picc_bb

Test Mode Control; Active Low

TEST_OUT

poa_bb

Test Mode Output

MCTL1, MCTL2

picc_bb

Channel Select in External MUX Control

EXT_MCTL

picc_bb

External MUX Control; Active Low

I/O Type Abbr.

-- AI: Analog Input

-- DI: Digital Input

-- AO: Analog Output

-- DO: Digital Output

-- AB: Analog Bidirectional

-- DB: Digital Bidirectional

-- AP: Analog Power

-- DP: Digital Power

-- AG: Analog Ground

-- DG: Digital Ground

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CODE CONFIGURATION

bw1222l

R_VIN

ADCCLK

MCTL1,MCTL2

D[9:0]

REFT

AD[2:0]
CSB
WRB
RDB
OEB

EXT_MCTL

TEST_S1,TESTS2

TEST_OUT

CDS2_CLK

CDS1_CLK

STRTLN

G_VIN

R_VIN

B_VIN

R_VIN

VCOM

REFB

VDDA1,VDDA2

VSSA1,VSSA2,VBBA

VDDA3,VDDA4

VSSA3,VSSA4

TEST_CTL

ABSOLUTE MAXIMUM

RATINGS

Characteristics

Symbol

Value

Unit

Supply Voltage

VDD

4.5

Analog Input Voltage

AIN

VSS to VDD

Digital Input Voltage

CLK

VSS to VDD

Reference Voltage

VRT/VRB

VSS to VDD

Storage Temperature Range

Tstg

-45 to 150

Operating Temperature Range

Topr

0 to 70

NOTES:
1.

ABSOLUTE

MAXIMUM

RATING

specifies

the

values

beyond

which

the

device

may

damaged

permanently.

Exposure

ABSOLUTE

MAXIMUM

RATING

conditions

for

extended

periods

may

affect

reliability.

Each

condition

value

applied

with

the

other

values

kept

within

the

following

operating

conditions

and

function

operation

under

any

these

conditions

not

implied.

All

voltages

are

measured

with

respect

VSS

unless

otherwise

specified.

100pF

capacitor

discharged

through

1.5k

resistor

(Human

body

model)

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ANALOG SPECIFICATIONS

(VDDA1, VDDA2=3.3V, VDDA3=3.3V, ADCCLK=6MHz, CDS1_CLK=2MHz,CDS2_CLK=2MHz, PGA Gain=1
unless otherwise noted)

Characteristics

Symbol

Min

Typ

Max

Unit

Comment

Resolution

Bits

Signal-to-Noise &
Distortion Ratio

SNDR

Conversion Rate
3-Channel with CDS
1-Channel with CDS

MSPS
MSPS

Differential
Nonlinearity

DNL

LSB

Integral
Nonlinearity

INL

LSB

Unipolar Offset Error

0.8

%FSR

Gain Error

1.6

%FSR

Anlog Input
Full-Scale Input
Input Capacitance
Reference Top
Reference Bottom

0.06

2.1
1.1

2.0

Vp-p

V
V

Power Supply
Analog Voltage
Digital Voltage
Analog Current
Digital Current

VDDA
VDDD

IDDA
IDDD

3.15
3.15

3.3
3.3

3.45
3.45

V
V

mA
mA

3.3V

Power Consumption

250

Temperature Range

DIGITAL SPECIFICATIONS

(VDDA1, VDDA2=3.3V, VDDA3=3.3V, ADCCLK=6MHz, CDS1_CLK=2MHz, CDS2_CLK=2MHz, C

=20pF

unless otherwise noted)

Characteristics

Symbol

Min

Typ

Max

Unit

Comment

High

Level

Input

Voltage

2.0

Low

Level

Input

Voltage

0.8

High

Level

Input

Current

Low

Level

Input

Current

High

Level

Output

Voltage

2.4

=0.5mA

Low

Level

Output

Voltage

0.4

=-0.5mA

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TIMING SPECIFICATIONS

Characteristics

Symbol

Min

Typ

Max

Unit

3-Channel Conversion Rate

500

1-Channel Conversion Rate

166

CDS1_CLK Pulse Width

C1CLK

CDS2_CLK Pulse Width

C2CLK

CDS2_CLK2 Pulse Width

C2CLKB

CDS1_CLK Falling to
CDS2_CLK2Rising

C1C2A

CDS2_CLK Falling to CDS1_CLK
Rising

C2C1A

ADCCLK Pulse Width

ADCLK

CDS2_CLK Rising to ADCCLK Rising

C2ADA

CDS2_CLK Falling to ADCCLK Falling

C2ADB

ADCCLK Rising to CDS2CLK Falling

ADC2A

STRTLN Rising, Falling Setup & Hold

S, tH

ADC Output Delay

ADDT

Data Hold Time

CSS

CSH

PWR

Write Pulse Width

PWW

Output Enable High to Tri-State

Tri-State to Data Valid

DEV

Aperture Delay

Latency for 1 Channel mode

3.5

ADCCLK

Cycles

NOTE: Aperture delay is a timing measurement between the sampling clocks and CDS. It is measured from the falling

edge of the CDS2_CLK input to when the input signal is held for data conversion

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FUNCTIONAL

DESCRIPTION

1) 3-Channel Operation with CDS

This mode enables simultaneous sampling of a triple output CCD. The CCD waveforms are ac coupled to the
VINR, VING and VINB pins where they are automatically biased at an appropriate voltage using the on-chip clamp.
The internal CDSs take two samples of the incoming pixel data; the first samples are taken during the reset time
while the second samples are taken during data portion of the input pixels. When STRTLN is low, the internal
circuitry is reset on the next rising edge of ADCCLK; the multiplexer is switched to red channel.

2) 3-Channel SHA Operation

This mode enables simultaneous sampling of a triple output CIS or something like that. The CDS functions are
replaced with the sample and hold amplifiers. The input waveforms are either dc coupled or dc restored to the
VINR, VING and VINB pins. The input reference voltage in this mode will be defined by clamp level control
register.

When STRTLN is low, the internal circuitry is reset on the next rising edge of ADCCLK; the multiplexer is switched
to red channel.

3) 1-Channel Operation with CDS

This mode enables single channel or monochrome sampling. The CCD waveforms are ac coupled to the analog
input pin where they are automatically biased at an appropriate voltage using the on-chip clamp.

Bit2 and bit3 in configuration register select the desired input among red, green and blue.

4) 1-Channel SHA Operation

This mode enables single-channel or monochrome sampling. The CDS function is replaced with the sample and
hold amplifier.

The input waveforms are either dc coupled or dc restored to the analog input pin. The input

reference voltage in this mode will be defined by clamp level control register. Bit2 and bit2 in configuration register
select the desired input among red, green and blue.

MAIN

BLOCK

DESCRIPTION

1) Programmable Gain Amplifier

The analog programmable gain can accommodate a wide range of input voltage spans. The transfer function of
the PGA is as follows.

H(X)

1/6*X

5/6,

where the range of X is 0 to 31.

Thus, the minimum gain value is equal to 5/6, and the maximum gain value is equal to 6. The transfer function has
linearity in linear scale. The overall gain is equal to analog gain multiplied by digital gain. So, the multiplier should
be required in back end of AFE.

2) REGISTER OVERVIEW

The MPU port map is accessed through pins A0, A1 and A2. See MPU port map format.(next page)

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BLOCK

DIAGRAM

Input Offset

(R,G,B)

CDS

PGA

ADC

REF

Gain & Clamp Level

(R,G,B)

Configuration

R_VIN

RED

G_VIN

GREEN

B_VIN

BLUE

CDS1_CLK

CDS2_CLK

ADCCLK

OEB

WRB

AD[2]

D[9:0]/

MPU[7:0]

CSB

MPU

PORT

VDDA1, 2

VSSA1, 2

VCOM

VDDA3

VSSA3

MCTL2

MCTL1

EXT_MCTL

TEST_S2

TEST_S1

TEST_CTL

TEST_OUT

REFT

REFB

STRTLN

CDS

PGA

CDS

CLAMP

PGA

R_CLAMP[2:0], R_GAIN[4:0]

G_CLAMP[2:0], G_GAIN[4:0]

B_CLAMP[2:0], B_GAIN[4:0]

R_OFFSET[7:0]

G_OFFSET[7:0]

B_OFFSET[7:0]

R_OFFSET[7:0]

G_OFFSET[7:0]

B_OFFSET[7:0]

R_CLAMP[2:0]; For only SHA mode

G_CLAMP[2:0]; For only SHA mode

B_CLAMP[2:0]; For only SHA mode

B_GAIN[4:0]

R_GAIN[4:0]

G_GAIN[4:0]

MUX

RDB

AD[1]

AD[0]

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Table 1.

MPU

Port

Map

Format

Register

Configuration

Red

Input

Offset

Green

Input

Offset

Blue

Input

Offset

Red

Gain

CIS

Clamp

Control

Green

Gain

CIS

Clamp

Control

Blue

Gain

CIS

Clamp

Control

Reserved

Configuration Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Clamp

mode

select1

Clamp

mode

select0

Set to 0

External

Reference

Color1

(Single

Channel)

Color0

(Single

Channel)

Single

Channel

CDS

Enable

Single Channel Color Pointer

Bit3

Bit2

Color

Red

Green

Blue

Reserved

Clamp Mode Selection

Bit3

Bit2

Clamp Mode

Line Clamp

Pixel Clamp

No Clamp

Reserved

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OVERALL

TRANSFER

FUNCTION

The overall transfer function can be calculated as follows.

ADC

out

=[(Vin+Input_Offset)* PGA_Gain]/(2*REF)*1024,

where REF is equal to (REFT-REFB) and Input _Offset means the DAC value of the input offset register. The
analog offset range of the input offset register is varied between 150mV and -150 mV. The 8-bit data format for
the input offset register is straight binary coding. Thus, an all 'zeros' data word corresponds to -150 mV. An all
'ones' data word corresponds to 150 mV. To maximize the dynamic range of the ADC input, it is necessary to
program the input offset register code to move the ADC code corresponding to the black level towards 'zero'.

In case of processing CIS signal, 3bits of the gain & clamp control register are allocated to control CIS clamp level.
Like the input offset register, the 3-bit data format is straight binary coding. An all 'zeros' data word corresponds to
0.1 V and an all 'ones' data word corresponds to 1.5 V.

INPUT

COUPLING

CAPACITOR

Because of the DC offset present at the output of CCD, some kind of DC restoration is required. In case of CDS
enable mode, to simplify input level shifting, a DC decoupling capacitor is used in conjuction with the internal input
circuitry.

The capacitor charging or discharging depends on the clamping time, the analog input resistance of the AFE and
the output resistance of the circuit driving the coupling capacitor.

The clamping time is typically (n*T), where n is the number of periods CDSCLK1 is asserted and T is the period of
assertion. CDSCLK2 should not be asserted during clamping time. And, STRTLN must be low in line clamp mode
for clamping operation. The analog input resistance of the AFE is equal to 1 kW. The recommended input coupling
capacitor is more than 0.01uF. Thus, to extend the clamping time, the time a transport motor moves the scanner
carriage can be available, for example.

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TEST

MODE

FOR

EACH

PGA

OUTPUT

(OPTIONAL)

It is possible to test each PGA output that is connected to next ADC block by external control pins. So, each PGA
output can be shown with an external test pin.

Test mode control(TEST_CTL) pin should go 'LOW' to operate AFE in test mode.

Color Pointer for Test Mode

TEST_S2

TEST_S1

Color

Red

Green

Blue

Reserved

PGA

ADC

R
G
B

TEST MUX

<TEST_CTL>

<TEST_S2>

<TEST_S1>

<TEST_OUT>

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Write to configuration register

Set CDS or SHA operation
Set 3 or 1 channel mode
Set color pointer
Set clamp mode

Write to PGA gain register
Set to gain of one(00001)

Write to input offset register

Set to 0mV(10000000)

Set another color

YES

Decide clamp level for SHA mode

(Refer to next page)

Set PGA gain

(Input offset = 0 mV)

Set another color

YES

Scan dark line

Compute pixel offsets

Set input offset

Set odd/even offset in back end

Set gain/offset bus size

in back end

Set external pixel offset

in back end

Scan white line

Compute pixel gains

in back end

Adjust PGA gain

YES

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CIS

CLAMP

LEVEL

DECISION

FOR

EACH

INPUT

*Assume

that

PGA

gain

The

user

can

modify

this

alogorithm

required

overall

system

ADC output > 0

YES

Scan clamp level input

Decrease CIS clamp control

Write CIS clamp control register

Set to (111)

Scan dark line

MIN(ADC output)

> 52

MIN(ADC output)

> 104

YES

MIN(ADC output)

> 0

YES

Go to calibration

Increase CIS

clamp control

Increase CIS

clamp control

YES

MIN(ADC output)

> 52

YES

Decrease CIS
clamp control
register by 1.

Scan dark line

Increase CIS

clamp control

[MIN(ADC output) = Minimum value of all pixels]

[Repeatedly, scan clamp level.

Average ADC output]

[(100mV)/(2V) * 1024 -1 = 52]

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PACKAGE

CONFIGURATION

The digital pins should be well decoupled to the analog ground plane.

ITEST

STBY

SPEEDUP

VBBA

VSSA1

VDDA1

IBIAS

B_VIN

G_VIN

R_VIN

D[7]

D[8]

D[9]

INDEX1

INDEX2

TEST_S1

TEST_S2

TEST_CTL

EXT_MCTL

MCTL1

MCTL2

AD[0]

AD[1]

AD[2]

[

]

[

]

[

]

[

]

[

]

[

]

[

]

0.01u

0.1u

10u

0.1u

0.1u
10u

10u

0.1u

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10u

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PACKAGE

PIN

DESCRIPTION

Pin No.

Pin Name

I/O Type

Description

TEST_OUT

Analog Output in Test Mode

VDDA2

Analog Power for A/D Converter

VDDA2

Analog Power for A/D Converter

VSSA2

Analog Ground for A/D Converter

VSSA2

Analog Ground for A/D Converter

VSSA4

Output Buffer Ground

VSSA4

Output Buffer Ground

VDDA4

Output Buffer Power

VDDA4

Output Buffer Power

D[0]

Digital Output (LSB)

D[1]

Digital Output

D[2]

Digital Output

D[3]

Digital Output

D[4]

Digital Output

D[5]

Digital Output

D[6]

Digital Output

D[7]

Digital Output

D[8]

Digital Output

D[9]

Digital Output (MSB)

INDEX1

Index Resistor(+)

INDEX2

Index Resistor(-)

TEST_S1

Color Pointer in Test Mode

TEST_S2

Color Pointer in Test Mode

TEST_CTL

Test Mode Control (Active Low)

Not Connected

EXT_MCTL

MUX Control Mode Selection(Active Low)

MCTL1

Color Pointer for MUX Control

MCTL2

Color Pointer for MUX Control

AD[0]

AD[1]

AD[2]

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PACKAGE

PIN

DESCRIPTION (Continued)

Pin No.

Pin Name

I/O Type

Description

CSB

Chip Selection (Active Low)

RDB

Read Strobe (Active Low)

WRB

Write Strobe (Active Low)

OEB

Output Enable (Active Low)

ADCCLK

A/D Converter Clock Input

CDS2_CLK

CDS Data Clock Input

CDS1_CLK

CDS Reset Clock Input

STRTLN

Start Line (Active Low)

VDDA3

Digital Power

VDDA3

Digital Power

VSSA3

Digital Ground

VSSA3

Digital Ground

Not Connected

VCOM

Reference Middle Voltage

REFT

Reference Top Voltage

REFB

Reference Bottom Voltage

R_VIN

Red Analog Input

G_VIN

Green Analog Input

B_VIN

Blue Analog Input

IBIAS

Current Bias Control for CDS & PGA

VDDA1

Analog Power

VDDA1

Analog Power

VSSA1

Analog Ground

VSSA1

Analog Ground

VBBA

Analog Ground

Not Connected

SPEEDUP

Speed-Up Selection for A/D Converter

STBY

Power Down Mode for A/D Converter

ITEST

Current Bias Control for A/D Converter

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USER

GUIDE

SYSTEM CONFIGURATION

It is necessary that output signal of analog front end be shading-compensated by back end logic block including
subtracter and multiplier.

(Shading-Compensation Block)

CCD/CIS

AFE

Subtracter

Multiplier

Controller

Memory

Table 2. Output Bus Controls

CSB

WRB

RDB

OEB

DOUT

MPU Input

MPU Output

ADC Output

NOTE: x: Don't Care X: Unknown (Not recommended)

Z: High Impedance

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FEEDBACK REQUEST

SPECIFICATION

Characteristics

Symbol

Min

Typ

Max

Unit

Comment

Resolution

Bits

Signal-to-Noise &
Distortion Ratio

SNDR

Conversion Rate
3-Channel with CDS
1-Channel with CDS

MSPS
MSPS

Differential
Nonlinearity

DNL

LSB

Integral
Nonlinearity

INL

LSB

Unipolar Offset Error

%FSR

Gain Error

%FSR

Anlog Input
Full-Scale Input

Vp-p

Power Supply
Analog Voltage
Digital Voltage

VDDA
VDDD

V
V

Power Consumption

Temperature Range

-- What do you want to choose as power supply voltages? For example, the analog VDD needs to be 3V.

The digital VDD can be 3.3V/5V.

-- Which modes of AFE do you use for overall system ? (Refer to page 9)

-- Would you define the gain range and input offset range ?

-- Could you explain external/internal pin configurations as required?

-- Should the bus interface be compatible with TTL ?

-- If possible, present other requirements below.

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