K4S283234F-M
Rev. 1.0 Jan. 2002
CMOS SDRAM
GENERAL DESCRIPTION
FEATURES
1M x 32Bit x 4 Banks SDRAM in 90FBGA
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
K4S283234F-ME/N1L 100MHz(CL=3)
*1
LVTTL
90 Balls
FBGA
K4S283234F-ME/N15 66MHz(CL=2)
*2
- ME ; Normal Power, Extended Temperature.
- MN ; Low Power, Extended Temperature.
1. In case of 40MHz Frequency, CL1 can be supported.
2. In case of 33MHz Frequency, CL1 can be supported.
Note :
. 2.5V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (1, 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
. Burst read single-bit write operation
DQM for masking
. Auto & self refresh
. 64ms refresh period (4K cycle).
. Extended Temperature Operation (-25
C ~ 85
C).
. 90Balls FBGA based on 2 pcs of 4Mx16 SDRAM.
Bank Select
Data Input Register
1M x 32
1M x 32
S
e
n
s
e
A
M
P
O
u
t
p
u
t
B
u
f
f
e
r
I
/
O
C
o
n
t
r
o
l
Column Decoder
Latency & Burst Length
Programming Register
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
R
o
w
B
u
f
f
e
r
R
e
f
r
e
s
h
C
o
u
n
t
e
r
R
o
w
D
e
c
o
d
e
r
C
o
l
.
B
u
f
f
e
r
L
R
A
S
L
C
B
R
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
1M x 32
1M x 32
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
The K4S283234F is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 32
bits, fabricated with SAMSUNG
s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock and I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst lengths and programmable latencies allow the
same device to be useful for a variety of high bandwidth and
high performance memory system applications.
K4S283234F-M
Rev. 1.0 Jan. 2002
CMOS SDRAM
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
D D
2.3
2.5
2.7
V
V
DDQ
2.3
2.5
2.7
V
Input logic high voltage
V
I H
0.9 x V
DDQ
2.5
V
DDQ
+ 0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.3
V
2
Output logic high voltage
V
O H
0.95 x V
DDQ
-
-
V
I
O H
= -2mA
Output logic low voltage
V
OL
-
-
0.2
V
I
OL
= 2mA
Input leakage current
I
LI
-10
-
10
uA
3
CAPACITANCE
(V
DD
= 2.5V, T
A
= 23
C, f = 1MHz, V
REF
=0.9V
50
mV)
Pin
Symbol
Min
Max
Unit
Note
Clock
C
CLK
4.0
8.0
pF
RAS, CAS, WE, CS, CKE, DQM
C
IN
4.0
8.0
pF
Address
C
ADD
4.0
8.0
pF
D Q
0
~ DQ
31
C
OUT
3.0
6.5
pF
1. V
IH
(max) = 3.0V AC. The overshoot voltage duration is
3ns.
2. V
IL
(min) = -1.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V
V
OUT
V
DDQ.
Note
:
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
I N
, V
OUT
-1.0 ~ 3.6
V
Voltage on V
D D
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
K4S283234F-M
Rev. 1.0 Jan. 2002
CMOS SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 85
C)
Parameter
Symbol
Test Condition
Version
Unit
Note
-1H
-1L
Operating Current
(One Bank Active)
I
CC1
Burst length = 1
t
RC
t
R C
(min)
I
O
= 0 mA
140
130
mA
1
Precharge Standby Current
in power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 10ns
2
mA
I
C C 2
PS CKE & CLK
V
IL
(max), t
CC
=
2
Precharge Standby Current
in non power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
30
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
12
Active Standby Current
in power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 10ns
6
mA
I
C C 3
PS CKE & CLK
V
IL
(max), t
CC
=
6
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
60
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
50
mA
Operating Current
(Burst Mode)
I
CC4
I
O
= 0 mA
Page burst
4Banks Activated
t
C C D
= 2CLKs
180
170
mA
1
Refresh Current
I
CC5
t
RC
t
R C
(min)
220
210
mA
2
Self Refresh Current
I
CC6
CKE
0.2V
-ME
2
mA
3
-MN
800
uA
4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S283234F-ME**
4. K4S283234F-MN**
5. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Notes :
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