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KM681001A
CMOS SRAM
PRELIMINARY
Rev 5.0
- 1 -
February 1998
Document Title
128Kx8 High Speed Static RAM(5V Operating), Evolutionary Pin Out.
Operated at Commercial Temperature Range.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
Rev. 3.0
Rev. 4.0
Rev. 5.0
Remark
Design Target
Preliminary
Final
Final
Final
Final
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary
Release to final Data Sheet.
2.1. Delete Preliminary
Update D.C and A.C parameters.
3.1. Update D.C parameters
3.2. Update A.C parameters
Update D.C and A.C parameters and add 300mil-SOJ PKG.
4. 1. Add 32-Pin 300mil-SOJ Package.
4. 2. Update D.C and A.C parameters.
4.3. Add the test condition for Voh1 with Vcc=5V
5% at 25
C
4.4. Add timing diagram to define tWP1 as
(
Timing Wave Form of
Write Cycle(OE=Low Fixed)
5.1. Delete 17ns Part
5.2. Delete 32-SOJ-300 Package
Items
Previous spec.
(15/17/20ns part)
Updated spec.
(15/17/20ns part)
Icc
190/180/170mA
165/165/160mA
Isb
30mA
25mA
Isb1
10mA
8mA
Items
Previous spec.
(15/17/20ns part)
Updated spec.
(15/17/20ns part)
t
CW
12/12/13ns
10/11/12ns
t
AW
12/12/13ns
10/11/12ns
t
WP1
(OE=H)
12/12/13ns
10/11/12ns
t
DW
8/9/10ns
7/8/9ns
Items
Previous spec.
(15/17/20ns part)
Updated spec.
(15/17/20ns part)
Icc
165/165/160mA
125/125/120mA
t
OW
3/4/5ns
3/3/3ns
Draft Data
Jan. 18th, 1995
Apr. 22th, 1995
Feb. 29th, 1996
Jul. 16th, 1996
Jun. 2nd, 1997
Feb. 25th, 1998
KM681001A
CMOS SRAM
PRELIMINARY
Rev 5.0
- 2 -
February 1998
128K x 8 Bit High-Speed CMOS Static RAM
GENERAL DESCRIPTION
FEATURES
Fast Access Time 15, 20ns(Max.)
Low Power Dissipation
Standby (TTL) : 25mA(Max.)
(CMOS) : 8mA(Max.)
Operating KM681001A - 15 : 125mA(Max.)
KM681001A - 20 : 120mA(Max.)
Single 5.0V
10% Power Supply
TTL Compatible Inputs and Outputs
I/O Compatible with 3.3V Device
Fully Static Operation
-No Clock or Refresh required
Three State Outputs
Standard Pin Configuration
KM681001AJ : 32-SOJ-400
Clk Gen.
I/O
1
~I/O
8
CS
1
WE
OE
FUNCTIONAL BLOCK DIAGRAM
R
o
w
S
e
l
e
c
t
Data
Cont.
Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
256x8 Columns
I/O Circuit
PIN FUNCTION
Pin Name
Pin Function
A
0
- A
16
Address Inputs
WE
Write Enable
CS
1
, CS
2
Chip Selects
OE
Output Enable
I/O
1
~ I/O
8
Data Inputs/Outputs
V
CC
Power(+5.0V)
V
SS
Ground
N.C
No Connection
The KM681001A is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
KM681001A uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using Samsung
s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM681001A is packaged
in a 400mil 32-pin plastic SOJ.
PIN CONFIGURATION
(Top View)
SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A
16
CS
2
WE
A
15
A
14
A
13
A
12
OE
A
11
CS
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
N.C
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
I/O
1
I/O
2
I/O
3
Vss
CS
2
A
8
A
9
A
10
A
11
A
13
A
14
A
15
A
16
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
12
KM681001A
CMOS SRAM
PRELIMINARY
Rev 5.0
- 3 -
February 1998
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Symbol
Rating
Unit
Voltage on Any Pin Relative to V
SS
V
IN
,
V
OUT
-0.5 to 7.0
V
Voltage on V
CC
Supply Relative to V
SS
V
CC
-0.5 to 7.0
V
Power Dissipation
P
D
1.0
W
Storage Temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
0 to 70
C
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to 70
C)
* V
IL
(Min) = -2.0V a.c(Pulse Width
10ns) for I
20mA
** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
10ns) for I
20mA
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
V
CC
4.5
5.0
5.5
V
Ground
V
SS
0
0
0
V
Input High Voltage
V
IH
2.2
-
V
CC
+ 0.5**
V
Input Low Voltage
V
IL
-0.5*
-
0.8
V
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70
C, Vcc=5.0V
10%, unless otherwise specified)
* V
CC
=5.0V, Temp.=25
C
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
I
LI
V
IN
= V
SS
to
V
CC
-2
2
A
Output Leakage Current
I
LO
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to
V
CC
-2
2
A
Operating Current
I
CC
Min. Cycle, 100% Duty
CS
1
=V
IL,
CS
2
=V
IH,
V
IN
=V
IH
or
V
IL,
I
OUT
=0mA
15ns
-
125
mA
20ns
-
120
Standby Current
I
SB
Min. Cycle, CS
1
=V
IH
or
CS
2
=V
IL
-
25
mA
I
SB1
f=0MHz, CS
1
V
CC
-0.2V or CS
2
0.2V,
V
IN
V
CC
-0.2V or
V
IN
0.2V
-
8
mA
Output Low Voltage Level
V
OL
I
OL
=8mA
-
0.4
V
Output High Voltage Level
V
OH
I
OH
=-4mA
2.4
-
V
V
OH1
*
I
OH1
=-0.1mA
-
3.95
V
CAPACITANCE*
(T
A
=25
C, f=1.0MHz)
* NOTE : Capacitance is sampled and not 100% tested.
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
C
I/O
V
I/O
=0V
-
8
pF
Input Capacitance
C
IN
V
IN
=0V
-
6
pF
KM681001A
CMOS SRAM
PRELIMINARY
Rev 5.0
- 4 -
February 1998
TEST CONDITIONS
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
C, V
CC
=5.0V
10%, unless otherwise noted.)
READ CYCLE
NOTE: t
CO
=t
CO1
, t
CO2
/ t
LZ
=t
LZ1
, t
LZ2
/ t
HZ
=t
HZ1
, t
HZ2
Parameter
Symbol
KM681001A-15
KM681001A-20
Unit
Min
Max
Min
Max
Read Cycle Time
t
RC
15
-
20
-
ns
Address Access Time
t
AA
-
15
-
20
ns
Chip Select to Output
t
CO*
-
15
-
20
ns
Output Enable to Valid Output
t
OE
-
8
-
10
ns
Chip Enable to Low-Z Output
t
LZ*
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ*
0
6
0
8
ns
Output Disable to High-Z Output
t
OHZ
0
6
0
8
ns
Output Hold from Address Change
t
OH
3
-
3
-
ns
Chip Selection to Power Up Time
t
PU
0
-
0
-
ns
Chip Selection to Power DownTime
t
PD
-
15
-
20
ns
Output Loads(A)
Output Loads(B)
D
OUT
5pF*
480
255
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+5.0V
D
OUT
30pF*
480
255
+5.0V
* Including Scope and Jig Capacitance
KM681001A
CMOS SRAM
PRELIMINARY
Rev 5.0
- 5 -
February 1998
WRITE CYCLE
NOTE: t
WR
=t
WR1
, t
WR2
Parameter
Symbol
KM681001A-15
KM681001A-20
Unit
Min
Max
Min
Max
Write Cycle Time
t
WC
15
-
20
-
ns
Chip Select to End of Write
t
CW
10
-
12
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
10
-
12
-
ns
Write Pulse Width(OE High)
t
WP
10
-
12
-
ns
Write Pulse Width(OE Low)
t
WP1
15
-
20
-
ns
Write Recovery Time
t
WR*
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
8
0
10
ns
Data to Write Time Overlap
t
DW
7
-
9
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS
1
=OE=V
IL
, CS
2
=WE=V
IH
)
t
AA
t
RC
t
OH
KM681001A
CMOS SRAM
PRELIMINARY
Rev 5.0
- 6 -
February 1998
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
200mV
from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS
1
=V
IL
and
CS
2
=V
IH.
7. Address valid prior to coincident with CS
1
transition low and CS
2
transition high.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
Address
CS
1
CS
2
t
WP(2)
t
DW
t
DH
Valid Data
WE
Data in
Data out
t
WC
t
WR(5)
t
AW
t
CW(3)
High-Z(8)
High-Z
OE
t
OHZ(6)
t
AS(4)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
CS
1
Address
OE
Data out
CS
2
t
AA
t
OLZ
t
LZ(4,5)
t
OH
t
OHZ
t
RC
t
OE
t
CO
t
PU
t
PD
Valid Data
t
HZ(3,4,5)
50%
50%
V
CC
Current
I
CC
I
SB
KM681001A
CMOS SRAM
PRELIMINARY
Rev 5.0
- 7 -
February 1998
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
1
=
Controlled)
Address
CS
1
t
AW
t
DW
t
DH
Valid Data
WE
Data in
Data out
High-Z
High-Z(8)
CS
2
t
CW(3)
t
WP(2)
t
AS(4)
t
WC
t
WR(5)
High-Z
High-Z
t
LZ
t
WHZ(6)
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low Fixed)
Address
CS
1
CS
2
t
WP1(2)
t
DW
t
DH
t
OW
t
WHZ(6)
Valid Data
WE
Data in
Data out
t
WC
t
AS(4)
t
WR(5)
t
AW
t
CW(3)
(10)
(9)
High-Z(8)
High-Z
KM681001A
CMOS SRAM
PRELIMINARY
Rev 5.0
- 8 -
February 1998
FUNCTIONAL DESCRIPTION
* NOTE : X means Don
t Care.
CS
1
CS
2
WE
OE
Mode
I/O Pin
Supply Current
H
X
X
X*
Not Select
High-Z
I
SB
, I
SB1
X
L
X
X
Not Select
High-Z
I
SB
, I
SB1
L
H
H
H
Output Disable
High-Z
I
CC
L
H
H
L
Read
D
OUT
I
CC
L
H
L
X
Write
D
IN
I
CC
TIMING WAVEFORM OF WRITE CYCLE(4)
(CS
2
= Controlled)
Address
CS
1
t
AS(4)
CS
2
t
WP(2)
WE
Data in
Data Valid
Data out
High-Z
High-Z
t
CW(3)
t
DW
t
DH
t
WC
t
WR(5)
t
AW
t
WHZ(6)
t
LZ
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS
1
, a high CS
2
and a low WE. A write begins at the latest transition CS
1
going low,a
CS
2
going high and WE going low ; A write ends at the earliest transition CS
1
going high, CS
2
going low or WE going high.
t
WP
is measured from the beginning of write to the end of write.
3. t
CW
is measured from the later of CS
1
going low or CS
2
going high to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR1
applied in case a write ends as CS
1
or WE going high. t
WR2
applied in case a write ends as CS
2
going low.
6. If OE, CS
1
, CS
2
and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS
1
goes low and CS
2
goes high simultaneously with WE going or after WE going low, the outputs remain high impedance
state.
9. Dout is the read data of the new address.
10. When CS
1
is low and CS
2
is high : I/O pins are in the output state. The input signals in the opposite phase leading to the out-
put should not be applied.
KM681001A
CMOS SRAM
PRELIMINARY
Rev 5.0
- 9 -
February 1998
PACKAGE DIMENSIONS
Units:millimeters/Inches
#1
32-SOJ-400
#32
20.95
0.12
0.825
0.005
1
0
.
1
6
0
.
4
0
0
+0.10
MAX
21.36
0.841
0.20
-0.05
+0.004
0.008
-0.002
9.40
0.25
0.370
0.010
MAX
0.148
3.76
MIN
0.69
0.027
1.30
( )
0.051
1.30
( )
0.051
0.95
( )
0.0375
+0.10
0.43
-0.05
+0.004
0.017
-0.002
+0.10
0.71
-0.05
+0.004
0.028
-0.002
1.27
0.050
#16
#17
0.004
0.10
MAX
11.18
0.12
0.440
0.005
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