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Электронный компонент: M53213200BE0

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DRAM MODULE
M53213200BE0/BJ0-C
4Byte 32Mx32 SIMM
Revision 0.1
June 1998
(16Mx4 base)
DRAM MODULE
M53213200BE0/BJ0-C
Revision History
Version 0.0 (Sept. 1997)
Removed two AC parameters t
CACP
(access time from CAS) and t
AAP
(access time from col. addr.) in AC CHARACTERISTICS.
Version 0.1 (June 1998)
The 3rd. generation of 64M DRAM components are applied for this module.
DRAM MODULE
M53213200BE0/BJ0-C
M53213200BE0/BJ0-C Fast Page Mode
32M x 32 DRAM SIMM Using 16Mx4, 4K Refresh, 5V
The Samsung M53213200BE0/BJ0-C is a 32Mx32bits
Dynamic RAM high density memory module. The Samsung
M53213200BE0/BJ0-C consists of sixteen CMOS 16Mx4bits
DRAMs in SOJ packages mounted on a 72-pin glass-epoxy
substrate. A 0.1 or 0.22uF decoupling capacitor is mounted
on the printed circuit board for each DRAM. The
M53213200BE0/BJ0-C is a Single In-line Memory Module
with edge connections and is intended for mounting into 72
pin edge connector sockets.
Part Identification
- M53213200BE0-C(4K cycles/64ms Ref, SOJ, Solder)
- M53213200BJ0-C(4K cycles/64ms Ref, SOJ, Gold)
Fast Page Mode Operation
CAS-before-RAS & Hidden Refresh capability
RAS-only refresh capability
TTL compatible inputs and outputs
Single +5V
10% power supply
JEDEC standard PDpin & pinout
PCB : Height(1420mil), double sided component
GENERAL DESCRIPTION
FEATURES
PERFORMANCE RANGE
Speed
t
RAC
t
CAC
t
RC
t
PC
-C50
50ns
13ns
90ns
35ns
-C60
60ns
15ns
110ns
40ns
PIN NAMES
Pin Name
Function
A0 - A11
Address Inputs
DQ0-7, DQ9-16
DQ18-25, DQ27-34
Data In/Out
W
Read/Write Enable
RAS0 - RAS3
Row Address Strobe
CAS0 - CAS3
Column Address Strobe
PD1 -PD4
Presence Detect
Vcc
Power(+5V)
Vss
Ground
NC
No Connection
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1
PD2
PD3
PD4
NC
Vss
Vss
Vss
NC
Vss
NC
NC
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
RAS3
RAS2
NC
NC
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
NC
NC
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
DRAM MODULE
M53213200BE0/BJ0-C
FUNCTIONAL BLOCK DIAGRAM
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
CAS0
RAS0
U0
Vcc
Vss
0.1 or .22uF Capacitor
for each DRAM
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U1
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U2
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U3
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U4
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U5
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U6
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U7
To all DRAMs
CAS1
CAS2
RAS2
CAS3
W
A0-A11
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
CAS0
RAS1
U8
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U9
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U10
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U11
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U12
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U13
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U14
CAS
RAS
OE
DQ1
DQ2
DQ3
DQ4
W A0-A11
U15
CAS1
CAS2
RAS3
CAS3
DQ0~DQ3
DQ4~DQ7
DQ9~DQ12
DQ13~DQ16
DQ18~DQ21
DQ22~DQ25
DQ27~DQ30
DQ31~DQ34
DRAM MODULE
M53213200BE0/BJ0-C
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Fast page mode cycle time,
t
PC
.
* NOTE :
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
-1 to +7.0
-1 to +7.0
-55 to +125
16
50
V
V
C
W
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70
C)
*1 : V
CC
+2.0V at pulse width
20ns, which is measured at V
CC
.
*2 : -2.0V at pulse width
20ns, which is measured at V
SS
.
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
4.5
0
2.4
-1.0
*2
5.0
0
-
-
5.5
0
V
CC
*1
0.8
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I(
IL)
I(
OL)
V
OH
V
OL
Symbol
Speed
M53213200BE0/BJ0
Unit
Min
Max
I
CC1
-50
-60
-
-
976
896
mA
mA
I
CC2
Don
t care
-
32
mA
I
CC3
-50
-60
-
-
976
896
mA
mA
I
CC4
-50
-60
-
-
576
496
mA
mA
I
CC5
Don
t care
-
16
mA
I
CC6
-50
-60
-
-
976
896
mA
mA
I
I(L)
I
O(L)
Don
t care
-10
-10
10
10
uA
uA
V
OH
V
OL
Don
t care
2.4
-
-
0.4
V
V
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current (RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
: Fast Page Mode Current * (RAS=V
IL
, CAS cycling :
t
PC
=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
V
IN
Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
V
OUT
Vcc)
: Output High Voltage Level (I
OH
= -5mA)
: Output Low Voltage Level (I
OL
= 4.2mA)