DRAM MODULE
M53640410CW0/CB0
M53640400CW0/CB0
M53640400CW0/CB0 & M53640410CW0/CB0 with EDO Mode
4M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K, Refresh, 5V
The Samsung M5364040(1)0C is a 4Mx36bits Dynamic RAM
high density memory module. The Samsung M5364040(1)0C
consists of eight CMOS 4Mx4bits DRAMs in 24-pin SOJ pack-
age and one CMOS 4Mx4 bit Quad CAS with EDO DRAM in
28-pin SOJ package mounted on a 72-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on the
printed circuit board for each DRAM. The M5364040(1)0C is a
Single In-line Memory Module with edge connections and is
intended for mounting into 72 pin edge connector sockets.
Part Identification
- M53640400CW0-C(4096 cycles/64ms Ref, SOJ, Solder)
- M53640400CB0-C(4096 cycles/64ms Ref, SOJ, Gold)
- M53640410CW0-C(2048 cycles/32ms Ref, SOJ, Solder)
- M53640410CB0-C(2048 cycles/32ms Ref, SOJ, Gold)
Extended Data Out
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
TTL compatible inputs and outputs
Single +5V
10% power supply
JEDEC standard PDPin & pinout
PCB : Height(1000mil), single sided component
GENERAL DESCRIPTION
FEATURES
PERFORMANCE RANGE
Speed
t
RAC
t
CAC
t
RC
t
HPC
-50
50ns
13ns
90ns
25ns
-60
60ns
15ns
110ns
30ns
PIN NAMES
Pin Name
Function
A0 - A11
Address Inputs(4K Ref)
A0 - A10
Address Inputs(2K Ref)
DQ0 - DQ35
Data In/Out
W
Read/Write Enable
RAS0
Row Address Strobe
CAS0 - CAS3
Column Address Strobe
PD1 -PD4
Presence Detect
Vcc
Power(+5V)
Vss
Ground
NC
No Connection
PRESENCE DETECT PINS (Optional)
* Pin connection changing available
Pin
50NS
60NS
PD1
PD2
PD3
PD4
Vss
NC
Vss
Vss
Vss
NC
NC
NC
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
Res(RAS1)
RAS0
DQ26
DQ8
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
* NOTE : A11 is used for only M53640400CW0/CB0(4K ref.)
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
DRAM MODULE
M53640410CW0/CB0
M53640400CW0/CB0
DQ8
DQ17
DQ26
DQ35
FUNCTIONAL BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
CAS
RAS
OE
W
A0-
Vcc
Vss
.1 or .22uF Capacitor
for each DRAM
To all DRAMs
A11(A10)
DQ0
DQ1
DQ2
DQ3
CAS
RAS
OE
W
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
CAS
RAS
OE
W
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
CAS
RAS
OE
W
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
CAS
RAS
OE
W
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
CAS
RAS
OE
W
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
CAS
RAS
OE
W
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
CAS
RAS
OE
W
A0-
A11(A10)
DQ0
DQ1
DQ2
DQ3
CAS0
CAS1
CAS2
CAS3
RAS
OE
W
A0-
A11(A10)
W
A0-A11(A10)
DQ31-DQ34
DQ27-DQ30
DQ22-DQ25
DQ18-DQ21
DQ13-DQ16
DQ9-DQ12
DQ4-DQ7
DQ0-DQ3
U0
U1
U2
U3
U4
U5
U6
U7
CAS0
RAS0
CAS1
CAS2
CAS3
U8
DRAM MODULE
M53640410CW0/CB0
M53640400CW0/CB0
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle,
t
HPC
.
* NOTE :
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
-1 to +7.0
-1 to +7.0
-55 to +150
9
50
V
V
C
W
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70
C)
*1 : V
CC
+2.0V/20ns, Pulse width is measured at V
CC
.
*2 : -2.0V/20ns, Pulse width is measured at V
SS
.
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
4.5
0
2.4
-1.0
*2
5.0
0
-
-
5.5
0
V
CC
+1
*1
0.8
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Symbol
Speed
M53640400CW0/CB0
M53640410CW0/CB0
Unit
Min
Max
Min
Max
I
CC1
-50
-60
-
-
810
720
-
-
990
900
mA
mA
I
CC2
Don't care
-
18
-
18
mA
I
CC3
-50
-60
-
-
810
720
-
-
990
900
mA
mA
I
CC4
-50
-60
-
-
720
630
-
-
810
720
mA
mA
I
CC5
Don't care
-
9
-
9
mA
I
CC6
-50
-60
-
-
810
720
-
-
990
900
mA
mA
I
I(L)
I
O(L)
Don't care
-45
-5
45
5
-45
-5
45
5
uA
uA
V
OH
V
OL
Don't care
2.4
-
-
0.4
2.4
-
-
0.4
V
V
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current (RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
: EDO Mode Current * (RAS=V
IL
, CAS Address cycling :
t
HPC
=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
V
IN
Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
V
OUT
Vcc)
: Output High Voltage Level (I
OH
= -5mA)
: Output Low Voltage Level (I
OL
= 4.2mA)
DRAM MODULE
M53640410CW0/CB0
M53640400CW0/CB0
CAPACITANCE
(T
A
= 25
C, V
CC
=5V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A11(A10)]
Input capacitance[W]
Input capacitance[RAS0]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-35]
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ1
-
-
-
-
-
65
80
80
40
20
pF
pF
pF
pF
pF
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.0/0.8V, Output loading CL=100pF
Parameter
Symbol
-50
-60
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
90
110
ns
Access time from RAS
t
RAC
50
60
ns
3,4,10
Access time from CAS
t
CAC
13
15
ns
3,4,5
Access time from column address
t
AA
25
30
ns
3,10
CAS to output in Low-Z
t
CLZ
3
3
ns
3
Output buffer turn-off delay from CAS
t
CEZ
3
13
3
15
ns
6,11,12
Transition time(rise and fall)
t
T
2
50
2
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
13
15
ns
CAS hold time
t
CSH
38
45
ns
CAS pulse width
t
CAS
8
10K
10
10K
ns
13
RAS to CAS delay time
t
RCD
20
37
20
45
ns
4
RAS to column address delay time
t
RAD
15
25
15
30
ns
10
CAS to RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
Column address hold time
t
CAH
8
10
ns
Column address to RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
Read command hold time referenced to CAS
t
RCH
0
0
ns
8
Read command hold time referenced to RAS
t
RRH
0
0
ns
8
Write command hold time
t
WCH
10
10
ns
Write command pulse width
t
WP
10
10
ns
Write command to RAS lead time
t
RWL
13
15
ns
Write command to CAS lead time
t
CWL
8
10
ns
Data-in set-up time
t
DS
0
0
ns
9
Data-in hold time
t
DH
8
10
ns
9
Refresh period (4K Ref)
t
REF
64
64
ms
Refresh period (2K Ref)
t
REF
32
32
ms
Write command set-up time
t
WCS
0
0
ns
7
CAS setup time(CAS-before-RAS refresh)
t
CSR
5
5
ns
CAS hold time(CAS-before-RAS refresh)
t
CHR
10
10
ns
RAS to CAS precharge time
t
RPC
5
5
ns
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=5.0V
10%. See notes 1,2.)
DRAM MODULE
M53640410CW0/CB0
M53640400CW0/CB0
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V
IH
(min) and V
IL
(max) and are assumed to be 5ns
for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
t
RCD
(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
t
WCS
is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
t
WCS
t
WCS
(min), the cycle is an early write cycle and the data
out pin will remain high impedance for the duration of the
cycle.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameter are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
t
CEZ
(max),
t
REZ
(max),
t
WEZ
(max) and
t
OEZ
(max) define the
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit cond-
tion of the output is achieved by RAS high going.
t
ASC
t
CP
min
In order to hold the address latched by the first CAS going
low, the parameter
t
CLCH
must be met.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.0/0.8V, Output loading CL=100pF
Parameter
Symbol
-50
-60
Unit
Note
Min
Max
Min
Max
CAS precharge time (C-B-R counter test
t
CPT
20
20
ns
Access time from CAS precharge
t
CPA
30
35
ns
3
Hyper page mode cycle time
t
HPC
25
30
ns
13
CAS precharge time(Hyper page cycle)
t
CP
8
10
ns
RAS pulse width(Hyper page cycle)
t
RASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
30
35
ns
W to RAS precharge time(C-B-R refresh)
t
WRP
10
10
ns
W to RAS hold time(C-B-R refresh)
t
WRH
10
10
ns
Output data hold time
t
DOH
5
5
ns
Output buffer turn off delay from RAS
t
REZ
3
13
3
15
ns
6,11,12
Output buffer turn off delay from W
t
WEZ
3
13
3
15
ns
6,11
W to data delay
t
WED
15
15
ns
W pulse width (Hyper Page Cycle)
t
WPE
5
5
ns
Hold time CAS low to CAS high
t
CLCH
5
5
ns
14
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=5.0V
10%. See notes 1,2.)
11.
12.
13.
14.
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