S3C4530A
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
INTRODUCTION
Samsung's S3C4530A 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4530A, is designed for use in
managed communication hubs and routers.
The S3C4530A is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by
Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose microprocessor macro-cell
that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and
fully static design is particularly suitable for cost-sensitive and power-sensitive applications.
The S3C4530A offers a configurable 8-Kbyte unified cache/SRAM and Ethernet controller which reduces total
system cost. Most of the on-chip function blocks have been designed using an HDL synthesizer and the
S3C4530A has been fully verified in Samsung's state-of-the-art ASIC test environment.
Important peripheral functions include two HDLC channels with buffer descriptor, two UART channels with full
modem interface signal and 32byte buffer, 2-channel GDMA, two 32-bit timers, and 26 programmable I/O ports.
On-board logic includes an interrupt controller, DRAM/ SDRAM controller, and a controller for ROM/SRAM and
flash memory. The System Manager includes an internal 32-bit system bus arbiter and an external memory
controller.
The following integrated on-chip functions are described in detail in this user's manual:
-- 8-Kbyte unified cache/SRAM
-- I
2
C interface
-- Ethernet controller
-- HDLC controller
-- GDMA
-- UART
-- Timers
-- Programmable I/O ports
-- Interrupt controller
PRODUCT OVERVIEW
S3C4530A
1-2
FEATURES
Architecture
Integrated system for embedded ethernet
applications
Fully 16/32-bit RISC architecture
Little/Big-Endian mode supported basically, the
internal architecture is big-endian.
So, the little-endian mode only support for
external memory.
Efficient and powerful ARM7TDMI core
Cost-effective JTAG-based debug solution
Boundary scan
System Manager
8/16/32-bit external bus support for
ROM/SRAM, flash memory, DRAM, and
external I/O
One external bus master with bus request/
acknowledge pins
Support for EDO/normal or SDRAM
Programmable access cycle (0-7 wait cycles)
Four-word depth write buffer
Cost-effective memory-to-peripheral DMA
interface
Unified Instruction/Data Cache
Two-way, set-associative, unified 8-Kbyte cache
Support for LRU (least recently used) protocol
Cache is configurable as an internal SRAM
I
2
C Serial Interface
Master mode operation only
Baud rate generator for serial clock generation
Ethernet Controller
DMA engine with burst mode
DMA Tx/Rx buffers (256 bytes Tx, 256 bytes
Rx)
MAC Tx/Rx FIFO buffers (80 bytes Tx, 16 bytes
Rx)
Data alignment logic
Endian translation
100/10-Mbit per second operation
Full compliance with IEEE standard 802.3
MII(10/100Mbps) or 7-wire 10-Mbps interface
Station management signaling
On-chip CAM (up to 21 destination addresses)
Full-duplex mode with PAUSE feature
Long/short packet modes
PAD generation
HDLCs
HDLC protocol features:
-- Flag detection and synchronization
-- Zero insertion and deletion
-- Idle detection and transmission
-- FCS generation and detection (16-bit)
-- Abort detection and transmission
Address search mode (expandable to 4 bytes)
Selectable CRC or No CRC mode
Automatic CRC generator preset
Digital PLL block for clock recovery
Baud rate generator
NRZ/NRZI/FM/Manchester data formats for
Tx/Rx
Loop-back and auto-echo modes
Tx/Rx FIFOs have 8-word (8
32-bit) depth
Selectable 1-word or 4-word data transfer mode
Data alignment logic
Endian translation
Programmable interrupts
Modem interface
Up to 10 Mbps operation
HDLC frame length based on octets
2-channel DMA buffer descriptor for Tx/Rx on
each HDLC
S3C4530A
PRODUCT OVERVIEW
1-3
DMA Controller
2-channel General DMA for memory-to-
memory, memory-to-UART, UART-to-memory
data transfers without CPU intervention
Initiated by a software or external DMA request
Increments or decrements a source or
destination address in 8-bit, 16-bit or 32-bit data
transfers
4-data burst mode
UARTs
Two UART (serial I/O) blocks with DMA-based
or interrupt-based operation
High speed(460Kbps) UART support with 32
byte Tx/Rx FIFO and modem interface signals
Support for 5-bit, 6-bit, 7-bit, or 8-bit serial data
transmit and receive
Automatic baud rate detection
Eight control character comparison for software
control
Programmable baud rates
1 or 2 stop bits
Odd or even parity
Break generation and detection
Parity, overrun, and framing error detection
16 clock mode
Infra-red (IR) Tx/Rx support (IrDA)
Timers
Two programmable 32-bit timers
Interval mode or toggle mode operation
Programmable I/O
26 programmable I/O ports
Pins individually configurable to input, output, or
I/O mode for dedicated signals
Interrupt Controller
21 interrupt sources, including 4 external
interrupt sources
Normal or fast interrupt mode (IRQ, FIQ)
Prioritized interrupt handling
PLL
The external clock can be multiplied by on-chip
PLL to provide high frequency system clock
The input frequency range is 10-40 MHz
The output frequency is 5 times of input clock.
To get 50 MHz, input clock frequency should be
10 MHz.
Operating Voltage Range
3.3 V
5
%
Operating Temperature Range
0
o
C to + 70
o
C
Operating Frequency
Up to 50 MHz
Package Type
208 pin QFP
PRODUCT OVERVIEW
S3C4530A
1-4
ARM7TDMI
32-bit RISE CPU
CPU Interface
8-Kbyte
Unified
Cache
4-Word
Write
Buffer
Bus Rounter
I
2
C
26 General I/O ports
Interruput Controller
UART 0,1
32-bit Timer 0,1
GDMA 0,1
PLL
Memory
Controller
with
Refresh
Control
System
Bus
Arbiter
2-Channel HDLCs
with DMAs
2-channel BDMA
Ethernet Controller
BDMA RAMs
Tx Buffer (256 bytes)
Rx Buffer (256 bytes)
CAM (128 bytes)
MAC
Tx FIFO (80 bytes)
Rx FIFO (16 bytes)
TAP Controller for JTAG
MII or
7-wire
Remote
port A,B
External
Bus
Master
4-bank
External
I/O
Device
4-bank
DRAM
6-bank
ROM
SRAM
FLASH
Console or
Modem I/F
SCL
SDA
26 I/O Ports including
4: Ext INT req.
2: Timer out (0,1)
2: Ext DMA REQ.
2: Ext DMA ACK
14: UART
Figure 1-1. S3C4530A Block Diagram
S3C4530A
PRODUCT OVERVIEW
1-5
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
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89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
1
2
3
4
5
6
7
8
9
10
18
17
11
12
13
14
15
16
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
V
DD
V
SS
nUADSR1/P<23>
UATXD1/P<24>
nUADTR1/P<25>
nDTRA
RXDA
nRTSA
TXDA
nCTSA
RxDB
nDTRB
V
DD
V
SS
nDCDA
RXCA
nSYNCA
TXCA
TXDB
nRTSB
V
SS
V
DD
nDCDB
nCTSB
nSYNCB
RXCB
CRS/CRS_ 10M
TXCB
RXD<0>/RXD_10M
RX DV/LINK_10M
V
SS
V
DD
RXD<2>
RXD<1>
RX ERR
RXD<3>
COL/COL_10M
RX_CLK/RXCLK_10M
TXD<1>/LOOP_10M
TXD<0>/TXD_10M
V
SS
V
DD
TXD<3>
TXD<2>
TXCLK/TXCLK_10M
Tx_ERR/POCMP_10M
MDIO
TX_EN/TXEN_10M
MDC
LITTLE
V
SS
V
DD
V
SS
V
DD
XDATA<16>
XDATA<15>
XDATA<14>
XDATA<13>
XDATA<12>
XDATA<11>
XDATA<10>
XDATA<9>
XDATA<3>
XDATA<4>
XDATA<8>
XDATA<7>
XDATA<6>
V
SS
V
DD
XDATA<5>
XDATA<1>
XDATA<2>
ADDR<21>
XDATA<0>
ADDR<19>
ADDR<20>
V
SS
ADDR<18>
ADDR<17>
V
DD
ADDR<15>
ADDR<16>
ADDR<13>
ADDR<14>
ADDR<11>
ADDR<12>
ADDR<9>
ADDR<10>/AP
V
SS
ADDR<8>
ADDR<7>
V
DD
ADDR<5>
ADDR<6>
ADDR<3>
ADDR<4>
ADDR<1>
ADDR<2>
ExtMACK
ADDR<0>
nWBE<3>/DQM<3>
ExtMREQ
V
DD
V
SS
V
DDa
V
SSa
FILTER
V
DD
V
SS
TCK
TMS
TDI
TD0
nTRST
TMODE
UCLK
V
DD
V
SS
nECS<0>
nECS<1>
nECS<2>
nECS<3>
nEWAIT
nOE
BOSIZE<0>
BOSIZE<1>
nRCS<0>
CLKOEN
SDCLK/MCLKO
V
DD
V
SS
XCLK
V
SS
nRESET
CLKSEL
nRCS<1>
nRCS<2>
nRCS<3>
nRCS<4>
nRCS<5>
nSDCS<0>/nRAS<0>
nSDCS<1>/nRAS<1>
nSDCS<2>/nRAS<2>
V
DD
V
SS
nSDCS<3>/nRAS<3>
nSDRAS/nCAS<0>
nSDCAS/nCAS<2>
CKE/nCAS<2>
nCAS<3>
nDWE
DQM<0>/nWBE<0>
DQM<1>/nWBE<1>
DQM<2>/nWBE<2>
V
DD
V
SS
156
155
154
153
152
151
150
149
148
147
139
140
146
145
144
143
142
141
137
138
135
136
133
134
131
132
129
130
127
128
125
126
123
124
121
122
119
120
117
118
115
116
113
114
111
112
109
110
107
108
105
106
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
V
SS
V
DD
UARXD1/P<22>
nUADTR0/P<21>
UATXD0/P<20>
nUADSR0/P<19>
UARXD0/P<18>
SDA
SCA
P<17>/TOUT1
V
SS
V
DD
P<16>/TOUT0
P<15>/nXDACK<1>
P<14>/nXDACK<0>
P<13>/nXDREQ<1>
P<12>/nXDREQ<0>
P<11>/XINREQ<3>
P<10>/XINREQ<2>
P<9>/XINREQ<1>
V
SS
V
DD
P<8>/XINREQ<0>
P<7>/nUARTS1
P<6>/nUACTS1
P<5>/nUADCD1
P<4>/nUARTS0
P<3>/nUACTS0
P<2>/nUADCD0
P<1>
V
SS
V
DD
P<0>
XDATA<31>
XDATA<30>
XDATA<29>
XDATA<28>
XDATA<27>
XDATA<26>
XDATA<25>
V
SS
V
DD
XDATA<24>
XDATA<23>
XDATA<22>
XDATA<21>
XDATA<20>
XDATA<19>
XDATA<18>
XDATA<17>
V
SS
V
DD
S3C4530A
(208-QFP)
Figure 1-2. S3C4530A Pin Assignment Diagram
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