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Электронный компонент: LZ21N3V

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In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
DESCRIPTION
The LZ21N3V/VS are 1/2-type (8.08 mm) solid-
state image sensors that consist of PN photo-
diodes and CCDs (charge-coupled devices). With
approximately 2 140 000 pixels (1 704 horizontal x
1 255 vertical), the sensor provides a stable high-
resolution color image.
FEATURES
Optical size : 8.08 mm (aspect ratio 4 : 3)
Interline scan format
Square pixel
Number of effective pixels : 1 650 (H) x 1 250 (V)
Number of optical black pixels
Horizontal : 2 front and 52 rear
Vertical : 3 front and 2 rear
Number of dummy bits
Horizontal : 28
Vertical : 2
Pixel pitch : 3.95 m (H) x 3.95 m (V)
R, G, and B primary color mosaic filters
Supports monitoring mode
Low fixed-pattern noise and lag
No burn-in and no image distortion
Blooming suppression structure
Built-in output amplifier
Built-in overflow drain voltage circuit and reset
gate voltage circuit
Variable electronic shutter
Packages
LZ21N3V : 20-pin half-pitch WDIP [Plastic]
(WDIP020-P-0500)
Row space : 12.20 mm
LZ21N3VS : 20-pin half-pitch WSOP [Plastic]
(WSOP020-P-0525)
PIN CONNECTIONS
PRECAUTIONS
The exit pupil position of lens should be 30 to 50
mm from the top surface of the CCD.
Refer to "PRECAUTIONS FOR CCD AREA
SENSORS" for details.
LZ21N3V/VS
LZ21N3V/VS
1/2-type Interline Color CCD
Area Sensors with 2 140 k Pixels
1
OD
2
GND
3
OFD
4
PW
5
RS
6
NC
1
7
NC
2
8
H1
9
NC
3
10
H2
20
19
18
17
16
15
14
OS
GND
NC
5
NC
4
V1A
V1B
V2
13
V3A
12
V3B
11
V4
20-PIN HALF-PITCH WDIP
20-PIN HALF-PITCH WSOP
TOP VIEW
(WDIP020-P-0500)
(WSOP020-P-0525)
Package
LZ21N3V
20-pin half-pitch WDIP
COMPARISON TABLE
20-pin half-pitch WSOP
LZ21N3VS
2
LZ21N3V/VS
PIN DESCRIPTION
SYMBOL
PIN NAME
OD
Output transistor drain
OS
Output signals
RS
Reset transistor clock
V1A
,
V1B
,
V2
,
V3A
,
V3B
,
V4
Vertical shift register clock
H1
,
H2
Horizontal shift register clock
PW
P-well
GND
Ground
NC
1
, NC
2
, NC
3
, NC
4
, NC
5
No connection
Overflow drain
OFD
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25 C)
PARAMETER
SYMBOL
RATING
UNIT
Output transistor drain voltage
V
OD
0 to +15
V
Reset gate clock voltage
V
RS
Internal output
V
Vertical shift register clock voltage
V
V
V
PW
to +15
V
Horizontal shift register clock voltage
V
H
0.3 to +12
V
Voltage difference between P-well and vertical clock
V
PW
-V
V
24 to 0
V
Storage temperature
T
STG
40 to +85
C
Ambient operating temperature
T
OPR
20 to +70
C
2
NOTE
NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect V
OD
to GND. Overflow drain clock is
applied below 22 Vp-p.
2. Do not connect to DC voltage directly. When
RS
is connected to GND, connect V
OD
to GND. Reset gate clock is
applied below 8 Vp-p.
3. When clock width is below 10 s, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 22 V.
1
V
Internal output
V
OFD
Overflow drain voltage
3
V
0 to +15
V
V
-V
V
Voltage difference between vertical clocks
3
LZ21N3V/VS
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Ambient operating temperature
T
OPR
25.0
C
Output transistor drain voltage
V
OD
12.5
13.0
13.5
V
NOTES :
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.
2. V
PW
is set below V
VL
that is low level of vertical shift register clock, or is used with the same power supply that is connected
to V
L
of V driver IC.
* To apply power, first connect GND and then turn on V
OD
. After turning on V
OD
, turn on PW first and then turn on other powers
and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.
1
V
20.9
19.5
18.6
V
OFD
Overflow drain clock
P-well voltage
V
PW
8.0
V
VL
V
2
Ground
GND
0.0
V
V
6.65
7.0
7.35
V
V1AL
, V
V1BL
, V
V2L
V
V3AL
, V
V3BL
, V
V4L
Vertical shift
register clock
LOW level
INTERMEDIATE level
HIGH level
V
V1AI
, V
V1BI
, V
V2I
V
V3AI
, V
V3BI
, V
V4I
V
V1AH
, V
V1BH
V
V3AH
, V
V3BH
12.5
0.0
13.0
13.5
V
V
LOW level
Horizontal shift
register clock
V
H1L
, V
H2L
0.05
0.0
0.05
V
HIGH level
V
H1H
, V
H2H
4.5
4.8
5.5
V
1
V
5.5
4.8
4.5
V
RS
Reset gate clock
p-p level
Reset gate clock frequency
f
RS
17.94
MHz
Horizontal shift register clock frequency
f
H1
, f
H2
17.94
MHz
Vertical shift register clock frequency
f
V1A
, f
V1B
, f
V2
f
V3A
, f
V3B
, f
V4
7.87
kHz
p-p level
LZ21N3V/VS
4
CHARACTERISTICS
(Drive method : 1/30 s frame accumulation)
(T
A
= +25 C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS".
Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Standard output voltage
V
O
150
mV
2
Photo response non-uniformity
PRNU
10
%
3
Saturation output voltage
V
SAT
450
530
mV
4
Dark output voltage
V
DARK
0.5
3.0
mV
1, 6
Dark signal non-uniformity
DSNU
0.5
2.0
mV
1, 7
Sensitivity (green channel)
R
140
180
mV
8
Smear ratio
SMR
89
82
dB
9
Image lag
AI
1.0
%
10
Blooming suppression ratio
ABL
1 000
11
Output transistor drain current
I
OD
4.0
8.0
mA
NOTES :
Within the recommended operating conditions of V
OD
,
V
OFD
of the internal output satisfies with ABL larger than
1 000 times exposure of the standard exposure conditions,
and V
SAT
larger than 320 mV.
1. T
A
= +60 C
2. The average output voltage of G signal under uniform
illumination. The standard exposure conditions are
defined as when Vo is 150 mV.
3. The image area is divided into 10 x 10 segments under
the standard exposure conditions. Each segment's
voltage is the average output voltage of all pixels within
the segment. PRNU is defined by (Vmax Vmin)/Vo,
where Vmax and Vmin are the maximum and minimum
values of each segment's voltage respectively.
4. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V
SAT
is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions. The operation of OFDC is
high. (for still image capturing)
5. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. V
SAT
is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions. The operation of OFDC is
low.
6. The average output voltage under non-exposure
conditions.
7. The image area is divided into 10 x 10 segments under
non-exposure conditions. DSNU is defined by (Vdmax
Vdmin), where Vdmax and Vdmin are the maximum and
minimum values of each segment's voltage respectively.
8. The average output voltage of G signal when a 1 000
lux light source with a 90% reflector is imaged by a lens
of F4, f50 mm.
9. The sensor is exposed only in the central area of V/10
square with a lens at F4, where V is the vertical image
size. SMR is defined by the ratio of the output voltage
detected during the vertical blanking period to the
maximum output voltage in the V/10 square.
10. The sensor is exposed at the exposure level
corresponding to the standard conditions. AI is defined
by the ratio of the output voltage measured at the 1st
field during the non-exposure period to the standard
output voltage.
11. The sensor is exposed only in the central area of V/10
square, where V is the vertical image size. ABL is
defined by the ratio of the exposure at the standard
conditions to the exposure at a point where blooming is
observed.
5
mV
400
320
LZ21N3V/VS
5
PIXEL STRUCTURE
1 650 (H) x 1 250 (V)
1 pin
OPTICAL BLACK
(2 PIXELS)
OPTICAL BLACK
(52 PIXELS)
OPTICAL BLACK
(3 PIXELS)
OPTICAL BLACK
(2 PIXELS)
COLOR FILTER ARRAY
(1, 1 250)
(1 650, 1 250)
(1, 1)
(1 650, 1)
V3B
V1B
V3A
V1B
V3B
V1B
V3B
V1A
V3B
V1B
V3B
V1B
V3B
V1B
V3B
V1B
V3A
V1B
V3B
V1B
V3B
V1A
V3B
V1B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
G
R G R G R G R G R G
B G B G B G B G B
Pin arrangement
of the vertical
readout clock
LZ21N3V/VS
6
TIMING CHART
NOTES :
1. Do not use these signals immediately after field accumulation mode is transferred to frame
accumulation mode for still image capturing.
2. Do not use these signals immediately after frame accumulation mode is transferred to field
accumulation mode for monitoring image.
* Apply at least an OFD shutter pulse to OFD in each field accumulation mode.
V3A
V2
V1B
V1A
VD
TIMING CHART EXAMPLE
OS
OFDC
OFD
V4
V3B
263
525 1
1
263
525
656 1
263
525 1
656 1
656 1
(at OFD shutter operation)
(Number of
vertical line)
Pulse diagram in more detail is shown in figures q to t after the next page.
Field accumulation mode Frame accumulation
mode at first
Frame accumulation mode
Field accumulation
mode at first
Field accumulation
mode
q
q
w
e
r
t
q
q'
q'
Field accumulation mode
Field accumulation
Not for use
(NOTE 1)
Not for use
(NOTE 2)
Frame accumulation mode
(3, 8, 13,..) (3, 8, 13,..) (3, 8, 13,..)
(1, 3, ..., 1247, 1249)
(2, 4, ..., 1248, 1250)
mode
(3, 8, 13,..)
LZ21N3V/VS
7
V3A
V2
V3B
OS
V1B
V1A
HD
VD
OFD
OFDC
V4
q VERTICAL TRANSFER TIMING FIELD ACCUMULATION MODE
257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284
OB1
RG GB RG GB
8
18
3
13
RG GB RG GB
1238
1248
1233
1243
RG GB RG GB
1218
1228
1213
1223
GB RG GB
1198
1208
1203
Shutter speed
1/30 s
V3A
V2
V3B
OS
V1B
V1A
HD
VD
OFD
OFDC
V4
519 520 521 522 523 524 525 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
OB1
RG GB RG GB
8
18
3
13
RG GB RG GB
1238
1248
1233
1243
RG GB
RG GB
1218
1228
1213
1223
GB RG
RG
GB
1198
1208
1203
1193
q' VERTICAL TRANSFER TIMING FIELD ACCUMULATION MODE
Shutter speed
1/30 s
LZ21N3V/VS
8
V3A
V2
V3B
OS
V1B
V1A
HD
VD
OFD
OFDC
V4
519 520 521 522 523 524 525 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
RG GB RG GB
1238
1248
1233
1243
RG GB RG GB
1218
1228
1213
1223
GB RG
RG
GB
1198
1208
1203
1193
Not for use
w VERTICAL TRANSFER TIMING FRAME ACCUMULATION MODE AT FIRST
Shutter speed
1/15 s
OFD
V3A
OFDC
V4
V3B
V2
V1B
V1A
VD
HD
e VERTICAL TRANSFER TIMING FRAME ACCUMULATION MODE
618 619 620 621 622 623 624
...
655 656 1
2
9
10
12
11
13
15
14
17
16
19
18
21
20
OS
OB2
1
3
5
RG RG RG
Not for use
Charge swept transfer (1 368 stages)
...
...
* Do not use the frame signals immediately after accumulation mode is transferred to frame
accumulation mode.
* Do not use the frame signals immediately after field accumulation mode is transferred to frame
accumulation mode.
LZ21N3V/VS
9
OFD
V3A
OFDC
V4
V3B
V2
V1B
V1A
VD
HD
r VERTICAL TRANSFER TIMING FRAME ACCUMULATION MODE
638 639 640 641 642 643 644 645 646
656 1
2
9
10
12
11
13
15
14
17
16
19
18
21
20
OS
OB1 OB3
2
4
GB GB
RG RG
RG
RG
RG
Not for use
Charge swept transfer (684 stages)
...
...
OB1
1249
1243
1247
1245
1241
OFD
V3A
OFDC
V4
V3B
V2
V1B
V1A
VD
HD
t VERTICAL TRANSFER TIMING FIELD ACCUMULATION MODE AT FIRST
640 641 642 643 644
656
...
6
5
7
1
2
3
4
9
8
10
12
11
13
15
14
17
16
19
18
21
20
OS
1244
OB2
1246
1248
1250
GB
GB
GB GB
Shutter speed
1/15 s
LZ21N3V/VS
10
40.9 s (732 bits)
58.8 s (1 052 bits)
(120 bits)
(120 bits)
892
V3A
V4
V3B
V2
V1A
HD
92 212
172 292
52 252
132 332
2280, 1
228
292
252
332
212
228
2280, 1
932
1172
1052
1012
732 852
972
6.7 s
6.7 s
V1B
READOUT TIMING FIELD ACCUMULATION MODE
40.9 s (732 bits)
58.8 s (1 052 bits)
(120 bits)
(120 bits)
892
972
V3A
V3B
V4
V2
V1A
V1B
HD
92 212
172 292
52
252
132 332
228
292
252
332
212
228
2280, 1
732 852
932
1012
6.7 s
6.7 s
READOUT TIMING FRAME ACCUMULATION MODE
e
r
892
1052 1172
92 212
172 292
52
252
132 332
228
932
1012
2280, 1
212
292
252
332
228
2280, 1
2280, 1
V3A
V3B
V4
V2
V1A
V1B
HD
972
* Keep over 2.2 s when vertical transfer clock pulse is overlapping.
* Keep over 2.2 s when vertical transfer clock pulse is overlapping.
LZ21N3V/VS
11
OS
RS
H2
H1
HD
OB (52)
HORIZONTAL TRANSFER TIMING FIELD ACCUMULATION MODE-1
1 clk = 55.8 ns (= 1/17.9 MHz)
2280, 1
52
92
132
172
212
228
252
292
332
40 clk
(= 2.2 s)
Double transfer
OFD
V4
V2
V1A
V1B
V3A
V3B
V4
V2
V1A
V1B
V3A
V3B
Triple transfer
192
272
1650
LZ21N3V/VS
12
OS
RS
H2
H1
HD
V4
V2
HORIZONTAL TRANSFER TIMING FIELD ACCUMULATION MODE-2
1 clk = 55.8 ns (= 1/17.9 MHz)
332
V1A
V1B
V3A
V3B
372
412
452
492
532
572
600
Double transfer
OFD
V4
V2
V1A
V1B
V3A
V3B
Triple transfer
OUTPUT (1 650) 1
OB (2)
PRE SCAN (28)
LZ21N3V/VS
13
OS
RS
H2
H1
HD
OB (52)
HORIZONTAL TRANSFER TIMING FRAME ACCUMULATION MODE-1
1 clk = 55.8 ns (= 1/17.9 MHz)
2280, 1
..1650
52
92
132
172
212
228
252
292
332
40 clk
(= 2.2 s)
Standard transfer
OFD
V4
V2
V1A
V1B
V3A
V3B
192
272
OS
RS
H2
H1
HD
HORIZONTAL TRANSFER TIMING FRAME ACCUMULATION MODE-2
1 clk = 55.8 ns (= 1/17.9 MHz)
332
372
412
452
492
532
572
600
Standard transfer
OFD
V4
V2
V1A
V1B
V3A
V3B
OUTPUT (1 650) 1
OB (2)
PRE SCAN (28)
V1A
V1B
V4
V3A
V3B
V2
HD
CHARGE SWEPT TRANSFER TIMING e
621H
11H 12H
3H
2H
1H
656H
655H
623H
622H
13H
1
228
2242
2
42
162
122
82
2
42
162
122
82
1
2
3
4
1368
1367
1366
2262
22 62
142
102
2262
22 62
142
102
2242
CHARGE SWEPT TRANSFER TIMING r
V1A
V1B
V4
V3A
V3B
V2
HD
645H
11H 12H
3H
2H
1H
656H
655H
647H
646H
13H
1
228
2242
2
42
162
122
82
2
42
162
122
82
1
2
3
4
684
683
682
2262
22 62
142
102
2262
22 62
142
102
2242
LZ21N3V/VS
14
* Keep over 1.1 s when vertical transfer clock pulse of charge swept transfer is overlapping.
* Keep over 1.1 s when vertical transfer clock pulse of charge swept transfer is overlapping.
LZ21N3V/VS
15
100 k$
33 k$
OD
PW
OFD
V2
V1B
V3A
V3B
V4
GND
NC
1
NC
2
H1
NC
3
H2
OS
GND
NC
5
NC
4
V1A
RS
V
3B
V
3A
V
1B
V
1A
V
Ma
V
H
V
4
V
2
V
L
V
Mb
POFD
NC
V
H
H2
VH
1BX
V
3X
V
2X
VH
3BX
V
4X
V
1X
VH
3AX
VH
1AX
+V
DD
OFDX
H1
RS
V
L
(V
PW
)
CCD
OUT
V
OFDH
VH
3BX
OFDX
V
2X
V
1X
V
3X
V
DD
GND
V
4X
VH
3AX
VH
1BX
VH
1AX
+
+
1
2
3
4
5
6
7
8
12
24
23
22
21
20
19
18
17
13
11
14
10
15
9
16
2
3
4
5
6
7
8
19
18
1
20
17
16
15
14
13
9
10
12
11
LR36685
LZ21N3V
(*1)
(*1)
V
OD
OFDC
270
pF
100 $
1 M$
1 M$
5.6 k$
47 k$
0. 1 F
1.0 F
0.01 F
+
+
(*1)
RS
, OFD :
Use the circuit parameter indicated in
this circuit example, and do not connect
to DC voltage directly.
SYSTEM CONFIGURATION EXAMPLE
PACKAGES FOR CCD AND CMOS DEVICES
16
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
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Glass Lid
Package
6.90
0.075
0.40
0.40
6.00
0.075
0.40
0.40
11.20
0.10
(2)
12.00
0.10
13.80
0.10
13.00
0.10
(2)
1
10
CCD
20
11
Center of effective imaging area
and center of package
Rotation error of die : = 1.0
MAX.
( 1 : Effective imaging area)
( 2 : Lid's size)
12.20
0.10
Refractive index : nd = 1.5
0.50
0.05
(2)
1.41
0.05
0.25
0.10
12.20
0.04
0.02
0.02
(1)
(1)
A'
A
A
A'
0.64
TYP.
0.30
TYP.
P-1.27
TYP.
0.20 M
3.50
0.10
2.40
0.10
2.90
0.10
CCD
+0.30
0
20 WDIP (WDIP020-P-0500)
PACKAGES
(Unit : mm)
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,,,,,,,,,,,,,,,,,,,,,,
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,,,,,,,,,,,,,,,,,,,,,,
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,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,
Glass Lid
Package
6.90
0.075
0.40
0.40
6.00
0.075
0.40
0.40
11.20
0.10
(2)
12.00
0.10
(1.00)
(1.00)
14.00
0.10
13.80
0.10
13.00
0.10
(2)
1
10
CCD
20
11
Center of effective imaging area
and center of package
Rotation error of die : = 1.0
MAX.
( 1 : Effective imaging area)
( 2 : Lid's size)
12.20
0.10
Refractive index : nd = 1.5
0.50
0.05
(2)
1.41
0.05
0.25
0.10
0.83
CCD
0.04
0.02
0.02
(1)
(1)
A'
A
1-5
A
A'
P-1.27
TYP.
0.64
TYP.
0.30
TYP.
0.10
0.20 M
1.00
0.10
2.40
0.10
2.90
0.10
20 WSOP (WSOP020-P-0525)
PRECAUTIONS FOR CCD AREA SENSORS
1. Package Breakage
In order to prevent the package from being broken,
observe the following instructions :
1) The CCD is a precise optical component and
the package material is ceramic or plastic.
Therefore,
Take care not to drop the device when
mounting, handling, or transporting.
Avoid giving a shock to the package.
Especially when leads are fixed to the socket
or the circuit board, small shock could break
the package more easily than when the
package isn't fixed.
2) When applying force for mounting the device or
any other purposes, fix the leads between a
joint and a stand-off, so that no stress will be
given to the jointed part of the lead. In addition,
when applying force, do it at a point below the
stand-off part.
(In the case of ceramic packages)
The leads of the package are fixed with low
melting point glass, so stress added to a
lead could cause a crack in the low melting
point glass in the jointed part of the lead.
(In the case of plastic packages)
The leads of the package are fixed with
package body (plastic), so stress added to a
lead could cause a crack in the package
body (plastic) in the jointed part of the lead.
3) When mounting the package on the housing,
be sure that the package is not bent.
If a bent package is forced into place
between a hard plate or the like, the pack-
age may be broken.
4) If any damage or breakage occurs on the sur-
face of the glass cap, its characteristics could
deteriorate.
Therefore,
Do not hit the glass cap.
Do not give a shock large enough to cause
distortion.
Do not scrub or scratch the glass surface.
Even a soft cloth or applicator, if dry, could
cause dust to scratch the glass.
2. Electrostatic Damage
As compared with general MOS-LSI, CCD has
lower ESD. Therefore, take the following anti-static
measures when handling the CCD :
1) Always discharge static electricity by grounding
the human body and the instrument to be used.
To ground the human body, provide resistance
of about 1 M$ between the human body and
the ground to be on the safe side.
2) When directly handling the device with the
fingers, hold the part without leads and do not
touch any lead.
Glass cap
Package
Lead
Fixed
Stand-off
Fixed
Lead
Stand-off
Low melting point glass
17
PRECAUTIONS FOR CCD AREA SENSORS
3) To avoid generating static electricity,
a. do not scrub the glass surface with cloth or
plastic.
b. do not attach any tape or labels.
c. do not clean the glass surface with dust-
cleaning tape.
4) When storing or transporting the device, put it in
a container of conductive material.
3. Dust and Contamination
Dust or contamination on the glass surface could
deteriorate the output characteristics or cause a
scar. In order to minimize dust or contamination on
the glass surface, take the following precautions :
1) Handle the CCD in a clean environment such
as a cleaned booth. (The cleanliness level
should be, if possible, class 1 000 at least.)
2) Do not touch the glass surface with the fingers.
If dust or contamination gets on the glass
surface, the following cleaning method is
recommended :
Dust from static electricity should be blown
off with an ionized air blower. For anti-
electrostatic measures, however, ground all
the leads on the device before blowing off
the dust.
The contamination on the glass surface
should be wiped off with a clean applicator
soaked in Isopropyl alcohol. Wipe slowly and
gently in one direction only.
Frequently replace the applicator and do not
use the same applicator to clean more than
one device.
Note : In most cases, dust and contamination
are unavoidable, even before the device
is first used. It is, therefore, recommended
that the above procedures should be
taken to wipe out dust and contamination
before using the device.
4. Other
1) Soldering should be manually performed within
5 seconds at 350 C maximum at soldering iron.
2) Avoid using or storing the CCD at high tem-
perature or high humidity as it is a precise
optical component. Do not give a mechanical
shock to the CCD.
3) Do not expose the device to strong light. For
the color device, long exposure to strong light
will fade the color of the color filters.
18
PRECAUTIONS FOR CCD AREA SENSORS