Sitronix

ST7070

Dot Matrix LCD Controller/Driver

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Features

5 x 8 dot matrix possible
Low power operation support:

-- 2.7 to 5.5V

Wide range of LCD driver power

-- 3.0 to 7.0V

Support high speed serial interface
Correspond to high speed MPU bus

interface

-- 2 MHz (when V

= 5V)

80 x 9-bit display RAM (80 characters max.)
19840-bit character generator ROM for a

total of 496 character fonts(5 x 8 dot)

64 x 8-bit character generator RAM

-- 8 character fonts (5 x 8 dot)

16-common x 80-segment liquid crystal

display driver

Programmable duty cycles

-- 1/8 for one line of 5 x 8 dots with cursor
-- 1/16 for two lines of 5 x 8 dots & cursor

Wide range of instruction functions:

Display clear, cursor home, display on/off,
cursor on/off, cursor shift, display shift

Automatic reset circuit that initializes the

controller/driver after power on

Internal oscillator with external resistors
Low power consumption

Description

The ST7070 dot-matrix liquid crystal display
controller and driver LSI displays alphanumeric,
Japanese kana characters, and symbols. It can be
configured to drive a dot-matrix liquid crystal display
under the control of a 4- or 8-bit microprocessor. With
high speed serial interface(3-line SPI , 4-line SPI), the
external MCU can control ST7070 directly. Since all
the functions such as display RAM, character
generator, and liquid crystal driver, required for
driving a dot-matrix liquid crystal display are internally
provided on one chip, a minimal system can be
interfaced with this controller/driver.

The ST7070 has function partial compatibility with the
HD44780, KS0066 and SED1278 that allows the user

to easily replace it with an ST7070. The ST7070
character generator ROM is extended to generate
496 5x8 dot character fonts for a total of 496 different
character fonts. The low power supply (2.7V to 5.5V)
of the ST7070 is suitable for any portable
battery-driven product requiring low power
dissipation.

The ST7070 LCD driver consists of 16 common
signal drivers and 80 segment signal drivers which
can extend display size by cascading segment driver
ST7921. The maximum display size can be either 80
characters in 1-line display or 40 characters in 2-line
display. A single ST7070 can display up to one
16-character line or two 16-character lines.

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ST7070 Serial Specification Revision History

Version Date

Description

0.1-

Preliminary

2002/9/23 Preliminary

version

0.1-

Preliminary

2002/11/21 Add 3-line SPI interface

0.2-

Preliminary

2002/12/20

N substrate change to P substrate.

Pad location modify.

0.3-

Preliminary

2003/01/21

Modify "Supply Voltage for LCD Drive" Description
I/O Pad Configuration

0.4-

Preliminary

2003/2/18 Add Application circuit

0.5

2003/07/24 Modify the 4 bit interface Initializing flow by Instruction

0.6

2003/08/28 Change the font Table (0B)

0.7

2003/09/09 Add the DC Characteristics Note

0.8 2003/11/10

Modify the 4 bit interface Initializing flow by Instruction
Add serial interface Initializing flow

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Block Diagram

Reset

circuit

CPG

Timing

generator

Instruction

decoder

Display data

RAM

(DDRAM)

80x9 bits

16-bit

shift

Common

signal
driver

80-bit

latch

circuit

80-bit

shift

Segment

signal
driver

LCD drive

voltage

selector

Address

counter

Data

(DR)

Busy

flag

MPU

interface

Input/

output

buffer

Character

generator

RAM

(CGRAM)

64 bytes

Character

generator

ROM

(CGROM)

19840 bits

Cursor

and

blink

controller

Parallel/serial converter

and

attribute circuit

DB4 to
DB7

DB0 to
DB3

GND

Vcc

OSC1 OSC2

CL1
CL2

COM1 to
COM16

SEG1 to
SEG80

XRESET

PSB

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Pad Configuration

Pad No.

Function

001 RS

-2585

660

002 DB[7]

-2585

540

003 XRESET -2585

430

004 DB[6]

-2585

320

005 DB[5]

-2585

210

006 DB[4]

-2585

105

007 DB[3]

-2585

008 DB[2]

-2585

-105

009 DB[1]

-2585

-210

010 DB[0]

-2585

-320

011 PSB

-2585

-430

012 RW

-2585

-540

013 E

-2585

-660

014 COM[9] -2585

-790

015 COM[10] -2445

-790

016 COM[11] -2315

-790

017 COM[12] -2195

-790

018 COM[13] -2085

-790

019 COM[14] -1975

-790

020 COM[15] -1865

-790

021 COM[16] -1755

-790

022 SEG[41] -1645

-790

023 SEG[42] -1535

-790

024 SEG[43] -1425

-790

025 SEG[44] -1315

-790

026 SEG[45] -1208

-790

027 SEG[46] -1102

-790

028 SEG[47] -997

-790

029 SEG[48] -892

-790

030 SEG[49] -787

-790

031 SEG[50] -682

-790

032 SEG[51] -577

-790

Pad No.

Function

033 SEG[52] -472

-790

034 SEG[53] -367

-790

035 SEG[54] -262

-790

036 SEG[55] -157

-790

037 SEG[56] -52

-790

038 SEG[57] 52

-790

039 SEG[58] 157

-790

040 SEG[59] 262

-790

041 SEG[60] 367

-790

042 SEG[61] 472

-790

043 SEG[62] 577

-790

044 SEG[63] 682

-790

045 SEG[64] 787

-790

046 SEG[65] 892

-790

047 SEG[66] 997

-790

048 SEG[67] 1102

-790

049 SEG[68] 1207

-790

050 SEG[69] 1315

-790

051 SEG[70] 1425

-790

052 SEG[71] 1535

-790

053 SEG[72] 1645

-790

054 SEG[73] 1755

-790

055 SEG[74] 1865

-790

056 SEG[75] 1975

-790

057 SEG[76] 2085

-790

058 SEG[77] 2195

-790

059 SEG[78] 2315

-790

060 SEG[79] 2445

-790

061 SEG[80] 2585

-790

062 D

2585

-660

063 M

2585

-540

064 CL2

2585

-430

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Pad No.

Function

065 CL1

2585

-320

066 OSC2 2585

-210

067 OSC1 2585

-105

068 VSS

2585

069 V4

2585

105

070 V3

2585

210

071 V2

2585

320

072 V1

2585

430

073 V0

2585

540

074 VDD

2585

660

075 SEG[40] 2585

790

076 SEG[39] 2445

790

077 SEG[38] 2315

790

078 SEG[37] 2195

790

079 SEG[36] 2085

790

080 SEG[35] 1975

790

081 SEG[34] 1865

790

082 SEG[33] 1755

790

083 SEG[32] 1645

790

084 SEG[31] 1535

790

085 SEG[30] 1425

790

086 SEG[29] 1315

790

087 SEG[28] 1207

790

088 SEG[27] 1102

790

089 SEG[26] 997

790

090 SEG[25] 892

790

091 SEG[24] 787

790

092 SEG[23] 682

790

093 SEG[22] 577

790

094 SEG[21] 472

790

095 SEG[20] 367

790

096 SEG[19] 262

790

097 SEG[18] 157

790

Pad No.

Function

098 SEG[17] 52

790

099 SEG[16] -52

790

100 SEG[15] -157

790

101 SEG[14] -262

790

102 SEG[13] -367

790

103 SEG[12] -472

790

104 SEG[11] -577

790

105 SEG[10] -682

790

106 SEG[9] -787

790

107 SEG[8] -892

790

108 SEG[7] -997

790

109 SEG[6] -1102

790

110 SEG[5] -1208

790

111 SEG[4] -1315

790

112 SEG[3] -1425

790

113 SEG[2] -1535

790

114 SEG[1] -1645

790

115 COM[1] -1755

790

116 COM[2] -1865

790

117 COM[3] -1975

790

118 COM[4] -2085

790

119 COM[5] -2195

790

120 COM[6] -2315

790

121 COM[7] -2445

790

122 COM[8] -2585

790

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Pin Function

Name Number

I/O

Interfaced

with

Function

RS 1

MPU

Select registers.
0: Instruction register (for write) Busy flag:

address counter (for read)

1: Data register (for write and read)
When serial interface select ,RS pull low , not floating.

R/W 1

MPU

Select read or write.
0: Write 1: Read
When serial interface select ,R/W pull low, not floating.

E 1

MPU

Starts data read/write.
When serial interface select ,E pull height , not floating.

XRESET

MPU

Hardware reset pin, Low active

PSB

MPU

Parallel /Serial selection. PSB: "1" Parallel , "0" Serial.

DB4 to DB7

I/O

MPU

Four high order bi-directional tristate data bus pins. Used for
data transfer and receive between the MPU and the ST7070.
DB7 can be used as a busy flag.
Serial:
DB7:data input pin for serial mode(SI)
DB6:serial clock input for serial mode(SCL)
DB5:chip select pin for serial mode(/CS)
When serial interface select ,D4 pull height , not floating.
4bits mode : These pins are used during 4-bit operation.

DB0 to DB3

I/O

MPU

Four low order bi-directional tristate data bus
pins. Used for data transfer and receive
between the MPU and the ST7070.
These pins are not used during 4-bit operation and serial
interface , must pull height , not floating.

CL1 1

Extension

driver

Clock to latch serial data D sent to the
Extension driver

CL2

Extension driver Clock to shift serial data D

1 O

Extension

driver

Switch signal for converting the liquid crystal
drive waveform to AC

D 1

Extension

driver

Character pattern data corresponding to each
segment signal

COM1 to

COM16

LCD

Common signals that are not used are changed
to non-selection waveform. COM9 to COM16
are non-selection waveforms at 1/8 duty factor
and COM12 to COM16 are non-selection
waveforms at 1/11 duty factor.

SEG1 to

SEG80

80 O LCD

Segment signals

V0 to V4

Power supply

Power supply for LCD drive
V0

Vss = 10 V (Max)

, GND

Power supply

: 2.7V to 5.5V, GND: 0V

OSC1, OSC2

Oscillation

resistor clock

When crystal oscillation is performed, a resistor
must be connected externally. When the pin
input is an external clock, it must be input to OSC1.

Note:
1. V0 >= V1 >= V2 >= V3 >= V4 >= Vss must be maintained
2. Two clock options:

OSC1

OSC2

Clock

input

R=91K

(Vcc=5V)

R=75K

(Vcc=3V)

OSC1

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Function Description

System Interface

This chip has all two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus or 8-bit bus is selected by DL
bit in the instruction register.

During read or write operation, two 8-bit registers are used. One is data register (DR), the other is instruction
register(IR).

The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM,
target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM,
is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM address is
transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into
DDRAM/CGRAM automatically.

The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read
instruction data.

To select register, use RS input pin in 4-bit/8-bit bus mode.

Table 1. Various kinds of operations according to RS and R/W bits.

Busy Flag (BF)

When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction
cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port.
Before executing the next instruction, be sure that BF is not High.

Address Counter (AC)

Address Counter(AC) stores DDRAM/CGRAM address, transferred from IR.
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.
When RS = "Low" and R/W = "High", AC can be read through DB6 ~ DB0 ports.

RS R/W

Operation

L L

Instruction Write operation (MPU writes Instruction code
into IR)

H Read Busy Flag(DB7) and address counter (DB6 ~ DB0)

L Data Write operation (MPU writes data into DR)

H Data Read operation (MPU reads data from DR)

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Display Data RAM (DDRAM)

Display data RAM (DDRAM) stores display data represented in 9-bit character codes. Its extended capacity is 80 x 9
bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data
RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display.

The DDRAM address (A

) is set in the address counter (AC) as hexadecimal.

1-line display (N = 0) (Figure 2)

When there are fewer than 80 display characters, the display begins at the head position. For
example, if using only the ST7070, 8 characters are displayed. See Figure 3.
When the display shift operation is performed, the DDRAM address shifts. See Figure 3.

Figure 1 DDRAM Address

Figure 2 1-Line Display

Figure 3 1-Line by 8-Character Display Example

AC6

AC5 AC4

AC3

AC2

AC1 AC0

High Order

bits

Low Order

bits

Example: DDRAM Address 4F

4D 4E 4F

DDRAM Address

....................

Display

Position

(Digit)

DDRAM

Address

Display

Position

For

Shift Left

For

Shift Right

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2-line display (N = 1) (Figure 4)

Figure 4 2-Line Display

Case 1: When the number of display characters is less than 40

�

2 lines, the two lines are

displayed from the head. Note that the

first line end address and th

e second line start address are not consecutive. For

example, when just the ST7070 is used, 16

characters

�

2 lines are displayed.

See Figure 5.

When display shift operation is performed, the DDRAM address shifts. See Figure 5.

Figure 5 2-Line by 16-Character Display Example

Case 2: For a 16-character

� 2-line display, See Figure 5.

When display shift operation is performed, the DDRAM address shifts. See Figure 5.

DDRAM

Address

(hexadecimal)

....................

Display

Position

....................

DDRAM

Address

Display

Position

For

Shift

Right

For

Shift

Left

09 0A 0B 0C 0D 0E

49 4A 4B 4C 4D 4E

09 0A 0B 0C 0D 0E 0F

49 4A 4B 4C 4D 4E 4F

09 0A 0B 0C 0D

49 4A 4B 4C 4D

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Character Generator ROM (CGROM)

The character generator ROM generates 5 x 8 dot character patterns from 9-bit character codes. It can generate 496
5 x 8 dot character patterns. User-defined character patterns are also available by mask-programmed ROM.

Character Generator RAM (CGRAM)

In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character
patterns can be written.

Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the character
patterns stored in CGRAM.

See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used
for display can be used as general data RAM.

Timing Generation Circuit

The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than
the display area.

LCD Driver Circuit

LCD Driver circuit has 16 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM is
transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is selected by
16 bit common register, segment data also output through segment driver from 80 bit segment latch. In case of 1-line
display mode, COM1 ~ COM8 have 1/8 duty, and in 2-line mode, COM1 ~ COM16 have 1/16 duty ratio.

Cursor Control Circuit

It can generate the cursor in the cursor control circuit. The cursor or the blink appears in the digit at the display data
RAM address set in the address counter.

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Character Code

(DDRAM Data)

CGRAM

Address

Character Patterns

(CGRAM Data)

b8 b7 b6 b5 b4 b3 b2 b1 b0 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

0 0 0

1 1 1 1

0 0 0

0 1 0 0

0 0 0

0 1 0 0

0 0 0

0 1 0 0

0 0 0

0 1 0 0

0 0 0

0 1 0 0

0 0 0

0 1 0 0

0 0 0 0 0 -

0 0 0

0 0 0 0

0 0 1

1 1 1 0

0 0 1

0 0 0 1

0 0 1

0 0 0 1

0 0 1

1 1 1 0

0 0 1

0 1 0 0

0 0 1

1 0

0 0 1

0 0 0 1

0 0 0 0 0 -

0 0 1

0 0 0 0

Table 5 Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns

(CGRAM Data)

Notes:
1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types).
2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the
cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to
the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bits will light up the 8th line regardless
of the cursor presence.
3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left).
4. As shown Table 5, CGRAM character patterns are selected when character code bits 4 to 7 are
all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either
character code 00H or 08H.
5. 1 for CGRAM data corresponds to display selection and 0 to non-selection.
"-": Indicates no effect.

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Instructions

There are four categories of instructions that:

Designate ST7070 functions, such as display format, data length, etc.
Set internal RAM addresses
Perform data transfer with internal RAM
Others

Instruction Table:

Instruction Code

Instruction

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description

Time

(270KHz)

EXT = 0 or 1

Clear

Display

0 0 0 0 0 0 0 0 1

Write "20H" to DDRAM. and
set DDRAM address to
"00H" from AC

1.52 ms

Return

Home

0 0 0 0 0 0 0 1 x

Set DDRAM address to
"00H" from AC and return
cursor to its original position
if shifted. The contents of
DDRAM are not changed.

1.52 ms

Display

ON/OFF

0 0 0 0 0 1 D

D=1:entire display on
C=1:cursor on
P: font table page selection

37 us

Cursor or

Display

Shift

0 0 0 0 1 S/C

R/L

x x

Set cursor moving and
display shift control bit, and
the direction, without
changing DDRAM data.

37 us

Function

Set

0 0 0 1 DL

EXT

x x

DL: interface data is 8/4 bits
N: number of line is 2/1

37 us

Read Busy

flag and

address

1 BF

AC6

AC5

AC4 AC3 AC2 AC1 AC0

Whether during internal
operation or not can be
known by reading BF. The
contents of address counter
can also be read.

0 us

Write data

to RAM

0 D7

D6 D5 D4

Write data into internal
RAM
(DDRAM/CGRAM)

37 us

Read data

from RAM

1 D7

D6 D5 D4

Read data from internal
RAM
(DDRAM/CGRAM)

37 us

EXT = 0

Entry Mode

Set

0 0 0 0 0 0 1 I/D

Sets cursor move direction
and specifies display shift.
These operations are
performed during data write
and read.

37 us

Set CGRAM

address

0 0 1

AC5

AC4 AC3 AC2 AC1 AC0

Set CGRAM address in
address counter

37 us

Set DDRAM

address

0 1

AC6

AC5

AC4 AC3 AC2 AC1 AC0

Set DDRAM address in
address counter

37 us

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EXT = 1

Bias resistor

select

0 0 0 0 0 0 1

Rb1 Rb0

Used internal resister only
provide 1/5 bias mode .
Rb[1:0]=00 External
Resister
Rb[1:0]=01~11 Internal
Resistor

37 us

COM

SEG

direction

select

0 0 1 0 0 C1

com1~8 com8~1

com9~16 com16~9

seg1~40 seg40~1

seg41~80 seg80~41

37 us

Set display

data length

0 1 L6 L5

To specify the number of
data bytes(3SPI mode)

37 us

Note:
Be sure the ST7070 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7070. If an
instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take
much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction execution time.

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Instruction Description

EXT=0 or 1

Clear

Display

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"

into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line

of the display. Make entry mode increment (I/D = "1").

Return

Home

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return

cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.

Display

ON/OFF

Control display/cursor/blink ON/OFF 1 bit register.

D : Display ON/OFF control bit

When D = "High", entire display is turned on.

When D = "Low", display is turned off, but display data is remained in DDRAM.

C : Cursor ON/OFF control bit

When C = "High", cursor is turned on.

When C = "Low", cursor is disappeared in current display, but I/D register remains its data.

P : Font table selection bit

When P = "Low", it select page 1 of font table.(set DDRAM data bit-8=0)

When P = "High", it select page 2 of font table(set DDRAM data bit-8=1)

Code

DB7

DB6

DB5

DB4

DB1

DB2

DB3

DB0

Every

32 frames

Alternating

display

Cursor

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Cursor or Display Shift

Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct

or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. Note that

display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted

individually. When display shift is performed, the contents of address counter are not changed.

S/C R/L

Description

Value

Shift cursor to the left

AC=AC-1

Shift cursor to the right

AC=AC+1

Shift display to the left. Cursor follows the display shift

AC=AC

Shift display to the right. Cursor follows the display shift AC=AC

Function

Set

DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select

8-bit or 4-bit bus mode.

When 4-bit bus mode, it needs to transfer 4-bit data by two times.

N : Display line number control bit

When N = "Low", it means 1-line display mode.

When N = "High", 2-line display mode is set.

EXT : Select basic or extended instruction set

When EXT="L" the commands `Entry Mode Set' , `Set CGRAM address' and `Set DDRAM address' can be

performed , when EXT="H" the commands `Bias resistor select' , `COM

SEG direction select' and `Set display

data length' can be performed. Other command can be executed in both cases.

When EXT="L" : disable extension instruction

When EXT="H" : enable extension instruction

S/C R/L

Code

DB7

DB6 DB5 DB4

DB1

DB2

DB3

DB0

EXT

Code

DB7

DB6

DB5 DB4

DB1

DB2

DB3

DB0

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Read Busy Flag and Address

When BF = "High", indicates that the internal operation is being processed.So during this time the next

instruction cannot be accepted.

The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR.

After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.

Write Data to CGRAM or DDRAM

Write binary 8-bit data to DDRAM/CGRAM.

The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction

: DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC

direction to RAM. DDRAM data bit-8 is come from "P"(Display on/off instruction) register setting

After write operation, the address is automatically increased/decreased by 1, according to

the entry mode.

Read Data from CGRAM or DDRAM

Read binary 8-bit data from DDRAM/CGRAM.

The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not

performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If

you read RAM data several times without RAM address set instruction before read operation, you can get correct

RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM

data.

In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address

set instruction : it also transfer RAM data to output data register. After read operation address counter is

automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display shift

may not be executed correctly.

* In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC

indicates the next address position, but you can read only the previous data by read instruction.

Code

DB7

DB6

DB5

DB4

DB1

DB2

DB3

DB0

AC6 AC5 AC4 AC3 AC2

Code

DB7

DB6

DB5

DB4

DB1

DB2

DB3

AC1 AC0

DB0

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EXT=0

Entry Mode Set

Set the moving direction of cursor and display.

I/D : Increment / decrement of DDRAM address (cursor or blink)

When I/D = "High", cursor moves to right and DDRAM address is increased by 1.

When I/D = "Low", cursor moves to left and DDRAM address is decreased by 1.

* CGRAM operates the same as DDRAM, when read from or write to CGRAM.

S: Shift of entire display

When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If S =

"High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1" : shift

left, I/D = "0" : shift right).

S I/D

Description

Shift the display to the left

Shift the display to the right

Set CGRAM Address

Set CGRAM address to AC.

This instruction makes CGRAM data available from MPU.

Set DDRAM Address

Set DDRAM address to AC.

This instruction makes DDRAM data available from MPU.

When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH".

In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and

DDRAM address in the 2nd line is from "40H" to "67H".

AC6

AC5

AC4 AC3 AC2

Code

DB7

DB6

DB5

DB4

DB1

DB2

DB3

AC1 AC0

DB0

AC5 AC4 AC3 AC2

Code

DB7

DB6

DB5

DB4

DB1

DB2

DB3

AC1 AC0

DB0

Code

DB7

DB6 DB5 DB4

DB1

DB2

DB3

I/D

DB0

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EXT=1

Bias resistor select

Set internal bias resistor value.

Rb1 Rb0

Description

External bias resistor select.

Build-in resistor select (R=2.2K).

Build-in resistor select (R=6.8K).

H H

Build-in resistor select (R=9.0K).

COM

SEG direction select

The SEG and COM output in ST7070 all have bi-direction control by the register.

COM OUTPUT :

COM output

COM1 COM8

0 COM1

Common Address COM8

1 COM8

Common Address COM1

COM output

COM9 COM16

0 COM9

Common Address COM16

1 COM16

Common Address COM9

SEG OUTPUT :

SEG output

SEG1 SEG40

SEG1 Segment Address SEG40

1 SEG40

Segment Address SEG1

SEG output

SEG41 SEG80

SEG41 Segment Address SEG80

SEG80 Segment Address SEG41

Code

DB7

DB6

DB5

DB4

DB1

DB2

DB3

Rb1 Rb0

DB0

Code

DB7

DB6

DB5

DB4

DB1

DB2

DB3

DB0

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Set display data length

L6 L5 L4 L3 L2 L1 L0 Data

length

0 0 0 0 0 0 0

0 0 0 0 0 0 1

.... ... ... ... ... ... ....

...

1 0 0 1 1 1 0

1 0 0 1 1 1 1

Only in 3line-SPI interface will use the register to set the number of display data(Max=4F).
To write data to DDRAM , send Data Direction Command in 3-pin SPI . Data is latched at the rising edge of SCLK .
And the DDRAM column address pointer will be increased by one automatically.

initial

EXT=1

No.of Data

Data0

Command

SCLK

SDI

CSB

Code

DB7

DB6

DB5

DB4

DB1

DB2

DB3

DB0

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Reset Function

Initializing by Internal Reset Circuit

An internal reset circuit automatically initializes the ST7070 when the power is turned on or hardware reset pin has

low. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until

the initialization ends (BF = 1). The busy state lasts for 40 ms after VCC rises to 4.5 V.

1. Display clear

2. Function set:

DL = 1; 8-bit interface data

N = 1; 2-line display

EXT=0;disable extension instruction.

3. Display on/off control:

D = 0; Display off

C = 0; Cursor off

P = 0; Page 1 of font table(DDRAM data b8=0)

4. Entry mode set:

I/D = 1; Increment by 1

S = 0; No shift

5. Bias resistor select:

Rb1=0;Rb2=0 select external bias resistor.

6. COM

SEG direction select:

C1=0;C2=0;S1=0;S2=0 not reverse.

Note:
If the electrical characteristics conditions listed under the table Power Supply Conditions Using
Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail
to initialize the ST7070. For such a case, initialization must be performed by the MPU as
explain by the following figure.

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Initializing by Instruction

8-bit Interface (fosc=270KHz)

POWER ON

Wait time >40mS

After Vcc >4.5V

Function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0

Wait time >37uS

Function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0

Wait time >37uS

Display ON/OFF control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0

Wait time >37uS

Display clear

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Wait time >1.52mS

Entry mode set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0

I/D

Initialization end

BF cannot be
checked before
this instruction.

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Initial Program Code Example For 8051 MPU(8 Bit Interface):

;---------------------------------------------------------------------------------
INITIAL_START:

CALL DELAY40mS

MOV A,#38H ;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot
CALL DELAY37uS

MOV A,#38H ;FUNCTION SET
CALL WRINS_NOCHK ;8 bit,N=1,5*7dot
CALL DELAY37uS

MOV A,#0FH ;DISPLAY ON
CALL WRINS_CHK
CALL DELAY37uS

MOV A,#01H ;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY1.52mS

MOV A,#06H ;ENTRY MODE SET
CALL WRINS_CHK ;CURSOR MOVES TO RIGHT
CALL DELAY37uS

;---------------------------------------------------------------------------------
MAIN_START:

XXXX
XXXX
XXXX
XXXX

.
.
.
.

;---------------------------------------------------------------------------------
WRINS_CHK:

CALL CHK_BUSY

WRINS_NOCHK:

CLR RS

;EX:Port 3.0

CLR RW

;EX:Port 3.1

SETB E

;EX:Port 3.2

MOV P1,A

;EX:Port 1=Data Bus

CLR E
MOV P1,#FFH

;For Check Busy Flag

RET

;---------------------------------------------------------------------------------
CHK_BUSY:

;Check

Busy

Flag

CLR RS
SETB RW
SETB E
JB P1.7,$
CLR E
RET

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Initial Program Code Example For 8051 MPU(4 Bit Interface):

;-------------------------------------------------------------------
INITIAL_START:

CALL DELAY40mS

MOV A,#38H ;FUNCTION SET
CALL WRINS_ONCE ;8 bit,N=1,5*7dot
CALL DELAY2mS

MOV A,#38H ;FUNCTION SET
CALL WRINS_ONCE ;8 bit,N=1,5*7dot
CALL DELAY37uS

MOV A,#38H ;FUNCTION SET
CALL WRINS_ONCE ;8 bit,N=1,5*7dot
CALL DELAY37uS

MOV A,#28H ;FUNCTION SET
CALL WRINS_NOCHK ;4 bit,N=1,5*7dot
CALL DELAY37uS

MOV A,#28H ;FUNCTION SET
CALL WRINS_NOCHK ;4 bit,N=1,5*7dot
CALL DELAY37uS

MOV A,#0FH ;DISPLAY ON
CALL WRINS_CHK
CALL DELAY37uS

MOV A,#01H ;CLEAR DISPLAY
CALL WRINS_CHK
CALL DELAY1.52mS

MOV A,#06H ;ENTRY MODE SET
CALL WRINS_CHK
CALL DELAY37uS

;-------------------------------------------------------------------
MAIN_START:

XXXX
XXXX
XXXX
XXXX

.
.
.
.
.
.
.
.
.

;-------------------------------------------------------------------
WRINS_CHK:

CALL CHK_BUSY

WRINS_NOCHK:

PUSH A
ANL A,#F0H
CLR RS

;EX:Port 3.0

CLR RW

;EX:Port 3.1

SETB E

;EX:Port 3.2

MOV P1,A

;EX:Port1=Data Bus

CLR E
POP A
SWAP A

WRINS_ONCE:

ANL A,#F0H
CLR RS
CLR RW
SETB E
MOV P1,A
CLR E
MOV P1,#FFH

;For Check Bus Flag

RET

;-------------------------------------------------------------------
CHK_BUSY:

;Check

Busy

Flag

PUSH A
MOV P1,#FFH

CLR RS
SETB RW
SETB E
MOV A,P1
CLR E
MOV P1,#FFH
CLR RS
SETB RW
SETB E
NOP
CLR E
JB A.7,$1
POP A

RET

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Serial Interface (fosc=270KHz)

POWER ON

Wait time >40mS

After Vcc >4.5V

Function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0

Wait time >37uS

Display ON/OFF control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0

Wait time >37uS

Display clear

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Wait time >1.52mS

Entry mode set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0

I/D

Initialization end

BF cannot be
checked before
this instruction.

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Interfacing to the MPU

The ST7070 can send data in either two 4-bit operations or one 8-bit operation or serial operation, thus allowing

interfacing with 4- or 8-bit or serial MPU.

For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. Bus lines DB0 to DB3

are disabled. The data transfer between the ST7070 and the MPU is completed after the 4-bit data has been

transferred twice. As for the order of data transfer, the four high order bits (for 8-bit operation, DB4 to DB7)

are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag must be

checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then

transfer the busy flag and address counter data.

Example of busy flag check timing sequence

Intel 8051 interface

P1.0 to P1.3

P3.0
P3.1
P3.2

RS
R/W
E

DB4 to DB7

COM1 to COM16

SEG1 to SEG80

Intel 8051 Serial

ST7070

Functioning

DB7

Internal
operation

R/W

Busy flag check

Instruction write

IR7

IR3

Not

Busy

IR3

IR7

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Supply Voltage for LCD Drive

There are different voltages that supply to ST7070's pin (V0 � V4) to obtain LCD drive waveform. We could use

the register command (Ra1,Ra0) to set up the Internal or External Bias Resister. The relations of the bias, duty

factor and supply voltages are shown as below. External Bias Resistor could set up to 1/4 bias and 1/5 bias,

but Internal Bias Resistor only could set up to 1/5 bias.

Duty Factor

1/8 1/8,1/16

External

Resistor

Bias

Supply Voltage

1/4 1/5

Bias Resistor Select

Ra1=0,Ra0=0 Ra1=0,Ra0=0

V0 VLCD

VLCD

V1 3/4VLCD 4/5VLCD

V2 1/2VLCD 3/5VLCD

V3 1/2VLCD 2/5VLCD

V4 1/4VLCD 1/5VLCD

1/4 bias
(1/8 duty cycle)

+5V

LCD

Vss

+5V

LCD

Vss

1/5 bias
(1/16 duty cycle)

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Duty Factor

1/8 , 1/16

Internal

Resistor

Bias

Supply Voltage

1/5 1/5 1/5

Bias Resistor Select

Ra1=0,Ra0=1 Ra1=1,Ra0=0 Ra1=1,Ra0=1

Internal Resistor

R=2.2K R=6.8K R=9.0K

VLCD

V1 4/5VLCD

4/5VLCD

V2 3/5VLCD

3/5VLCD

V3 2/5VLCD

2/5VLCD

V4 1/5VLCD

1/5VLCD

+5V

LCD

GND

1/5 bias R=2.2K
(1/8,1/16 duty cycle)

VSS

+5V

LCD

GND

VSS

1/5 bias R=6.8K
(1/8,1/16 duty cycle)

Ra1=0,Ra0=1

Ra1=1,Ra0=0

+5V

LCD

GND

1/5 bias R=9.0K
(1/8,1/16 duty cycle)

VSS

Ra1=1,Ra0=1

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OH2

OL2

CWH

CST

CWH

CWL

CL1

CL2

2.7V/4.5V

0.2V

rcc

OFF

1mS

0.1mStrcc80mS

Notes:

OFF

compensates for the power oscillation period caused by momentary power supply oscillations.

Specified at 4.5V for 5V operation,and at 2.7V for 3V operation.
For if 4.5V is not reached during 5V operation,teh internal reset circuit will not operate normally.

Interface Timing with External Driver

Internal Power Supply Reset

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AC Characteristics

In 6800 interface

(TA = 25

, VCC = 2.7V )

Symbol Characteristics

Test

Condition Min. Typ. Max. Unit

Internal Clock Operation

OSC

OSC Frequency

R = 75K

190 270 350 KHz

External Clock Operation

External

Frequency

125 270 410 KHz

Duty

Cycle

45 50 55 %

Rise/Fall

Time

- - 0.2

�

Write Mode (Writing data from MPU to ST7070)

Enable Cycle Time Pin E

Enable Pulse Width Pin E

Enable Rise/Fall Time Pin E

Address Setup Time Pins: RS,RW,E

Address Hold Time Pins: RS,RW,E

DSW

Data Setup Time

Pins: DB0 - DB7

Data Hold Time

Pins: DB0 - DB7

Read Mode (Reading Data from ST7070 to MPU)

Enable Cycle Time Pin E

1200

Enable Pulse Width Pin E

480

Enable Rise/Fall Time Pin E

Address Setup Time Pins: RS,RW,E

Address Hold Time Pins: RS,RW,E

DDR

Data Setup Time

Pins: DB0 - DB7

320

Data Hold Time

Pins: DB0 - DB7

Interface Mode with LCD Driver(ST7921)

CWH

Clock Pulse with High Pins: CL1, CL2

800

CWL

Clock Pulse with Low Pins: CL1, CL2

800

CST

Clock Setup Time Pins: CL1, CL2

500

Data Setup Time

Pin: D

300

Data Hold Time

Pin: D

300

M Delay Time

Pin: M

2000

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AC Characteristics

In 6800 interface

(TA = 25

, VCC = 5V)

Symbol Characteristics

Test

Condition Min. Typ. Max. Unit

Internal Clock Operation

OSC

OSC Frequency

R = 91K

190

270

350

KHz

External Clock Operation

External

Frequency

125

270

410 KHz

Duty

Cycle

Rise/Fall

Time

- - 0.2

�

Write Mode (Writing data from MPU to ST7070)

Enable Cycle Time Pin E

Enable Pulse Width Pin E

Enable Rise/Fall Time Pin E

Address Setup Time Pins: RS,RW,E

Address Hold Time Pins: RS,RW,E

DSW

Data Setup Time

Pins: DB0 - DB7

Data Hold Time

Pins: DB0 - DB7

Read Mode (Reading Data from ST7070 to MPU)

Enable Cycle Time Pin E

1200

Enable Pulse Width Pin E

140

Enable Rise/Fall Time Pin E

Address Setup Time Pins: RS,RW,E

Address Hold Time Pins: RS,RW,E

DDR

Data Setup Time

Pins: DB0 - DB7

100

Data Hold Time

Pins: DB0 - DB7

Interface Mode with LCD Driver(ST7921)

CWH

Clock Pulse with High Pins: CL1, CL2

800

CWL

Clock Pulse with Low Pins: CL1, CL2

800

CST

Clock Setup Time Pins: CL1, CL2

500

Data Setup Time

Pin: D

300

Data Hold Time

Pin: D

300

M Delay Time

Pin: M

2000

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AC Characteristics

In Serial interface

(TA = 25

, VCC = 2.7V )

Symbol Characteristics

Test

Condition Min. Typ. Max. Unit

Internal Clock Operation

OSC

OSC Frequency

R = 75K

190 270 350 KHz

External Clock Operation

External

Frequency

125 270 410 KHz

Duty

Cycle

45 50 55 %

Rise/Fall

Time

- - 0.2

�

Write Mode (Writing data from MPU to ST7070)

Enable Cycle Time Pin E

2000

Enable Pulse Width Pin E

950

Enable Rise/Fall Time Pin E

Address Setup Time Pins: RS,E

Address Hold Time Pins: RS,,E

DSW

Data Setup Time

Pins: DB0 - DB7

Data Hold Time

Pins: DB0 - DB7

Interface Mode with LCD Driver(ST7921)

CWH

Clock Pulse with High Pins: CL1, CL2

800

CWL

Clock Pulse with Low Pins: CL1, CL2

800

CST

Clock Setup Time Pins: CL1, CL2

500

Data Setup Time

Pin: D

300

Data Hold Time

Pin: D

300

M Delay Time

Pin: M

2000

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AC Characteristics

In Serial Interface
(TA = 25

, VCC = 5V)

Symbol Characteristics

Test

Condition Min. Typ.

Max. Unit

Internal Clock Operation

OSC

OSC Frequency

R = 91K

190

270

350

KHz

External Clock Operation

External

Frequency

125

270

410 KHz

Duty

Cycle

Rise/Fall

Time

- - 0.2

�

Write Mode (Writing data from MPU to ST7070)

Enable Cycle Time Pin E

800

Enable Pulse Width Pin E

Enable Rise/Fall Time Pin E

Address Setup Time Pins: RS,E

Address Hold Time Pins: RS,E

DSW

Data Setup Time

Pins: DB0 - DB7

Data Hold Time

Pins: DB0 - DB7

Interface Mode with LCD Driver(ST7921)

CWH

Clock Pulse with High Pins: CL1, CL2

800

CWL

Clock Pulse with Low Pins: CL1, CL2

800

CST

Clock Setup Time Pins: CL1, CL2

500

Data Setup Time

Pin: D

300

Data Hold Time

Pin: D

300

M Delay Time

Pin: M

2000

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Absolute Maximum Ratings

Characteristics Symbol

Value

Power Supply Voltage

-0.3 to +5.5

LCD Driver Voltage

LCD

Vss+7.0 to Vss-0.3

Input Voltage

-0.3 to V

+0.3

Operating Temperature

-40

C to + 90

Storage Temperature

STO

-55

C to + 125

DC Characteristics

( TA = 25

, VCC = 2.7 V � 4.5 V )

Symbol

Characteristics Test

Condition Min. Typ. Max.

Unit

Operating

Voltage

2.7 - 4.5 V

LCD

LCD Voltage

V0 - Vss

3.0

7.0

Power

Supply

Current

OSC

= 270KHz

=3.0V

- 0.1

0.25 mA

IH1

Input High Voltage

(Except OSC1)

- 0.7Vcc

IL1

Input Low Voltage

(Except OSC1)

- -

0.3

0.6

IH2

Input High Voltage

(OSC1)

- 0.7Vcc

IL2

Input Low Voltage

(OSC1)

- -

0.2Vcc

OH1

Output High Voltage

(DB0 - DB7)

= -0.1mA

0.75

Vcc

- - V

OL1

Output Low Voltage

(DB0 - DB7)

= 0.1mA

0.2Vcc

OH2

Output High Voltage

(Except DB0 - DB7)

= -0.04mA

0.8V

- V

OL2

Output Low Voltage
(Except DB0 - DB7)

= 0.04mA

0.2V

COM

Common

Resistance V

LCD

= 4V, I

= 0.05mA

SEG

Segment

Resistance V

LCD

= 4V, I

= 0.05mA

LEAK

Input Leakage

Current

= 0V to V

-1

�

PUP

Pull Up MOS Current

= 3V

120

�

NOTE :

External bias resistor select , so Idd doesn't include the follower current.

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DC Characteristics

( TA = 25

, V

= 4.5 V - 5.5 V )

Symbol Characteristics

Test Condition Min. Typ. Max.

Unit

Operating

Voltage

4.5 - 5.5 V

LCD

LCD Voltage

V0 - Vss

3.0

7.0

Power Supply Current

OSC

= 270KHz

=5.0V

- 0.2 0.5 mA

IH1

Input High Voltage

(Except OSC1)

- 2.5

IL1

Input Low Voltage

(Except OSC1)

- -0.3

0.6

IH2

Input High Voltage

(OSC1)

- V

-1

- V

IL2

Input Low Voltage

(OSC1)

- -

1.0

OH1

Output High Voltage

(DB0 - DB7)

= -0.1mA

3.9

OL1

Output Low Voltage

(DB0 - DB7)

= 0.1mA

0.4

OH2

Output High Voltage

(Except DB0 - DB7)

= -0.04mA

0.9V

- V

OL2

Output Low Voltage
(Except DB0 - DB7)

= 0.04mA

0.1V

COM

Common

Resistance V

LCD

= 4V, I

= 0.05mA

SEG

Segment

Resistance V

LCD

= 4V, I

= 0.05mA

LEAK

Input Leakage

Current

= 0V to V

-1

�

PUP

Pull Up MOS Current

= 5V

200

330

�

NOTE :

External bias resistor select , so Idd doesn't include the follower current.

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Application Circuit

ST
79

Dot Matr

ix LC

D Pa

VSS

cc(
+

5
V

)

Re
s
i
s
t
or

e
s
i
st

o
r

e
si

o
r

e
si

o
r

e
si

o
r

RS/
R

W/
E

/
DB
0-DB7

To
M
P

CL
1

CL
2

GND

VCC

e
g 1
-
80

Com

1-16

VS
S

SH
L

VC
C

DL
1

VSS

SHL

VCC

DL
1

CL
2

CL
1

DR1

DL
2

DR2

CL
2

CL
1

DR
1

DL
2

DR
2

e
g
1~
9
6

e
g

e
si

o
r
=

2
.2

K~1

0
K o
h
m

V
R

1
0
K

3
0
K

2

(
L

0
(

h
ar

r
s

)

5X8 dot

s
/
c
h
a
r
a
c
t
e
r

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THE MPU INTERFACE

The ST7070 Series can be connected to 6800 Series MPUs. Moreover, using the serial interface it is possible to
operate the ST7070 series chips with fewer signal lines.
The display area can be enlarged by using multiple ST7070 Series chips . When this is done , the chip select
signal can be used to select the individual Ics to access.
(1) 6800 8 bits Series MPUs

MPU

VCC

D0 to D7

R/W

/RES

GND

ST7070

VDD

D0 to D7

R/W

/RES

GND

PSB

VSS

VDD

VLCD

VSS

When use external bias resistor
must connect

(2) 6800 4 bits Series MPUs

VCC

D4 to D7

R/W

/RES

GND

ST7070

VDD

D4 to D7

R/W

/RES

GND

PSB

VSS

VDD

D0 to D3

VLCD

VSS

When use external bias resistor
must connect

ST7070

V0.8

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(3) Using the Serial Interface--For 4 SPI

VCC

/RES

GND

ST7070

VDD

R/W

/RES

GND

PSB

VSS

VDD

D0 to D5

D7(SI)

D6(SCL)

D5(CS)

D7(SI)

D6(SCL)

D5(CS)

VLCD

VSS

When use external bias resistor
must connect

(4) Using the Serial Interface--For 3 SPI

MPU

VCC

/RES

GND

ST7070

VDD

R/W

/RES

GND

PSB

VSS

VDD

D0 to D5

D7(SI)

D6(SCL)

D5(CS)

D7(SI)

D6(SCL)

D5(CS)

VLCD

VSS

When use external bias resistor
must connect

Электронный компонент: ST7070